Abstract: A device and method for selective placement of charge into a gate stack includes forming gate stacks including a gate dielectric adjacent to a transistor channel and a gate conductor and forming doped regions for transistor operation. A layer rich in a passivating element is deposited over the doped regions and the gate stack, and the layer rich the passivating element is removed from selected transistors. The layer rich in the passivating element is than annealed to drive-in the passivating element to increase a concentration of charge at or near transistor channels on transistors where the layer rich in the passivating element is present. The layer rich in the passivating element is removed.

Abstract: A semiconductor device includes a substrate including a high-voltage transistor area provided with a high-voltage transistor and a low-voltage transistor area provided with a low-voltage transistor; a LOCOS layer provided as a device isolation layer of the high-voltage transistor area; and a shallow-trench isolation layer provided as a device isolation layer of the low-voltage transistor area. Accordingly, a sufficient breakdown voltage level can be provided in a high-voltage transistor area, on-resistance and leakage current can be enhanced, and the chip area in a low-voltage transistor area can be reduced.

Abstract: A semiconductor resistor, method of making the resistor and method of making an IC including resistors. Buried wells are formed in the silicon substrate of a silicon on insulator (SOI) wafer. At least one trench is formed in the buried wells. Resistors are formed along the sidewalls of the trench and, where multiple trenches form pillars, in the pillars between the trenches by doping the sidewalls with an angled implant. Resistor contacts are formed to the buried well at opposite ends of the trenches and pillars, if any.

Abstract: Where the silicon active layer of an SOI substrate is used as a resistor, it is difficult to form small wells densely in a semiconductor support substrate portion under the resistor because of the presence of a buried insulation film. It is also difficult to control the potential division of the wells. Therefore, there is the problem that the resistance value is varied by potential variations. Island-like silicon active layer and buried insulation film are formed by etching. Side spacers made of polycrystalline silicon are formed on the sidewalls of step portions of the island-like silicon active layer, buried insulation film, and semiconductor support substrate. The potentials at the side spacers are controlled. Thus, resistance value variations due to variations in the potential difference between the semiconductor support substrate and the resistor can be suppressed. Furthermore, accurate potential division owing to each resistor is facilitated.

Abstract: A MIM capacitor is formed over one or more metal interconnect layers in a semiconductor device. The capacitor has a lower plate electrode and an upper plate electrode. An insulator is formed between the plate electrodes. Prior to forming the first plate electrode a first insulating layer is deposited over the metal of an interconnect layer. The first insulating layer is planarized using a chemical mechanical polish (CMP) process. A second insulating layer is then deposited over the planarized first insulating layer. The first plate electrode is formed over the second insulating layer. An insulator is formed over the first plate electrode and functions as the capacitor dielectric. A second plate electrode is formed over the insulator. Planarizing the first insulating layer and depositing a second insulating layer over the first insulating layer, reduces defects and produces a more reliable capacitor.

Abstract: In a method of manufacturing a semiconductor device including a capacitor, a first mold layer is formed on a semiconductor substrate. The first mold layer is partially etched to form a first mold layer pattern including an opening for a capacitor. A first lower electrode layer is formed on the first mold layer pattern. A second lower electrode layer including a plurality of first pores is formed on the first lower electrode layer and in the opening. Upper portions of the first lower electrode layer and the second lower electrode layer are removed to form a first lower electrode and a second lower electrode in the opening. A dielectric layer and an upper electrode are successively formed on the first lower electrode and the second lower electrode. Therefore, a capacitor having an enhanced capacitance may be obtained.

Abstract: A method of forming and resulting isolation region, which allows for densification of an oxide layer in the isolation region. One exemplary embodiment of the method includes the steps of forming a first trench, forming an oxide layer on the bottom and sidewalls of the trench, forming nitride spacers on the lined trench, and thereafter etching the silicon beneath the first trench to form a second trench area. An oxide layer is then deposited to fill the second trench. Densificiation of the isolation region is possible because the silicon is covered with nitride, and therefore will not be oxidized. Light etches are then performed to etch the oxide and nitride spacer area in the first trench region. A conventional oxide fill process can then be implemented to complete the isolation region.

Abstract: Embodiments of the present invention provide a method for reclaiming and reusing a wafer. In one embodiment, a method for reclaiming a wafer comprises providing a used, nonproductive wafer having a semiconductor substrate and a polysilicon layer formed on the semiconductor substrate; oxidizing a first part of the polysilicon layer to form a first oxide layer; removing the first oxide layer; and oxidizing a second part of the polysilicon layer to form a second oxide layer on the used wafer which is to be used as a reclaimed wafer. The nonproductive wafer is used to improve the quality of a deposition process of the polysilicon layer on one or more productive wafers.

Abstract: A peeling method is provided which does not cause damage to a layer to be peeled, and the method enables not only peeling of the layer to be peeled having a small area but also peeling of the entire layer to be peeled having a large area at a high yield. Further, there are provided a semiconductor device, which is reduced in weight through adhesion of the layer to be peeled to various base materials, and a manufacturing method thereof. In particular, there are provided a semiconductor device, which is reduced in weight through adhesion of various elements, typically a TFT, to a flexible film, and a manufacturing method thereof. A metal layer or nitride layer is provided on a substrate; an oxide layer is provided contacting with the metal layer or nitride layer; then, a base insulating film and a layer to be peeled containing hydrogen are formed; and heat treatment for diffusing hydrogen is performed thereto at 410° C. or more.

Abstract: To provide a penetration electrode having high quality. A method of manufacturing a semiconductor device includes the following steps: (a) forming a concave part from a first face of a semiconductor substrate in which an integrated circuit is formed; (b) providing a resin layer at least on the bottom face of the concave part; (c) forming a conductive part to an inner side of the resin layer of the concave part; (d) disposing the resin layer from a second face opposite to the first face of the semiconductor substrate by wet etching; and (e) exposing the conductive part from the second face of the semiconductor substrate.

Abstract: The invention relates to a method of re-forming a useful layer on a donor wafer after taking off a useful layer formed of a material chosen from among semiconductor materials. The donor wafer includes in succession a substrate and a taking-off structure, the taking-off structure includes the taken-off useful layer before taking-off. The method includes a removal of material involving a portion of the donor wafer on the side where the useful layer has been taken off. The material is removed by mechanical means so as to preserve a portion of the taking-off structure to form at least one other useful layer which can be taken off after re-forming, without adding additional material to the wafer.

Abstract: Through vias in a substrate are formed by creating a trench in a top side of the substrate and at least one trench in the back side of the substrate. The sum of the depths of the trenches at least equals the height of the substrate. The trenches cross at intersections, which accordingly form the through vias from the top side to the back side. The through vias are filled with a conductor to form contacts on both sides and the edge of the substrate. Contacts on the backside are formed at each of the trench. The through vias from the edge contacts. Traces connect bond pads to the conductor in the through via. Some traces are parallel to the back side traces. Some traces are skew to the back side traces. The substrate is diced to form individual die.

Abstract: In annealing a non-single crystal silicon film through the use of a linear laser beam emitted by a YAG laser of a light source, it is the object of the present invention to prevent heterogeneity in energy caused by an optical interference produced in the linear laser beam from having an effect on the silicon film. The laser beam is divided by a mirror 604 shaped like steps into laser beams which have an optical path difference larger than the coherence length of the laser beam between them. The divided laser beams are converged on an irradiate surface 611 by the action of a cylindrical lens array 605 and a cylindrical lens 606 to homogenize the energy of the laser beam in the length direction and to determine the length of the linear laser beam.

Abstract: A method of making an ex-situ doped semiconductor transport layer for use in an electronic device includes: growing a first set of semiconductor nanoparticles having surface organic ligands in a colloidal solution; growing a second set of dopant material nanoparticles having surface organic ligands in a colloidal solution; depositing a mixture of the first set of semiconductor nanoparticles and the second set of dopant material nanoparticles on a surface, wherein there are more semiconductor nanoparticles than dopant material nanoparticles; performing a first anneal of the deposited mixture of nanoparticles so that the organic ligands boil off the surfaces of the first and second set of nanoparticles; performing a second anneal of the deposited mixture so that the semiconductor nanoparticles fuse to form a continuous semiconductor layer and the dopant material atoms diffuse out from the dopant material nanoparticles and into the continuous semiconductor layer.

Abstract: This disclosure describes system(s) and/or method(s) enabling contacts for individual nanometer-scale-thickness layers of a multilayer film.

Abstract: Formation of an WNX film 24 constituting a barrier layer of a gate electrode 7A having a polymetal structure is effected in an atmosphere containing a high concentration nitrogen gas, whereby release of N (nitrogen) from the WNX film 24 is suppressed in the heat treatment step after the formation of the gate electrode 7A.

Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.

Abstract: A method for manufacturing a gate electrode structure for preventing abnormal oxidation of a refractory metal due to an oxidation process, includes forming an insulating film on a surface of a semiconductor substrate; forming an impurity diffused polysilicon film on the insulating film; forming an impurity diffusion preventing film on the impurity diffused polysilicon film; forming a refractory metal silicide film on the impurity diffusion preventing film; forming a first nitride film on the refractory metal silicide film; patterning the first nitride film, the refractory metal silicide film and the impurity diffusion preventing film on a gate electrode; forming a first spacer constituted by a second nitride film on side surfaces of the first gate electrode; performing anisotropic etching on the impurity diffused polysilicon film with the first and second nitride films as a mask; and performing an oxidation process.

Abstract: Disclosed herein is a method for fabricating a memory device. According to the present invention, during an etching process for forming a recess gate region, a device isolation film is etched using a mask partially exposing a channel region and its neighboring device isolation film, and then a semiconductor substrate is etched, thus preventing a silicon horn in the recess gate region from being formed. Accordingly, a margin for the etching process is increased.

Abstract: A method for fabricating a semiconductor a semiconductor device having a stacked-gate structure. A polysilicon layer is formed overlying a substrate, which is insulated from the substrate by a dielectric layer. A metal-flash layer is formed overlying the polysilicon layer, and then a tungsten nitride layer is formed overlying the titanium layer. The tungsten nitride layer is annealed using nitrogen and hydrogen gases. A tungsten layer and a cap layer are successively formed overlying the tungsten nitride layer.

Abstract: Etching is performed on an insulating layer 23 and a conductive layer 32 with a photoresist 41 as the mask, to form an opening 51 in the conductive layer 32. After removing the photoresist 41, another insulating layer 24 is formed all over, which is etched back so as to expose a surface of a conductive layer 31, to thereby cover the inner wall of the opening 51. Then etching is performed on the conductive layer 31 with the latter insulating layer 24 as the mask, so as to form another opening 52 in the conductive layer 31. Then still another insulating layer 25 is formed all over, which is then etched back so as to expose a surface of the conductive layer 32, to thereby fill the opening 52 with the last formed insulating layer 25.

Abstract: An image sensor and a method for fabricating the same are disclosed, to improve a contact quality between a contact plug and a source diffusion layer.

Abstract: The present invention provides a method of forming a plurality of bumps over a wafer. The wafer has a plurality of contact pads and a passivation layer thereon and the passivation layer exposes the contact pads. An adhesion layer is formed over the active surface of the wafer and covers both the contact pads and the passivation layer. A metallic layer is formed over the adhesion layer. The patterned adhesion layer and patterned metallic layer remain on top of the contact pads. A photoresist layer having a plurality of openings that expose the metallic layer is formed on the active surface of the wafer. A flux material is deposited into the openings and then a solder block is disposed into each of the openings. A reflow process is performed to bond the solder block with the metallic layer. Finally, the flux material and the photoresist layer are removed.

Abstract: A method for far back end of line (FBEOL) semiconductor device formation includes forming a terminal copper pad in an upper level of a semiconductor wafer, forming an insulating stack over the terminal copper pad, and patterning and opening a terminal via within a portion of the insulating stack so as to leave a bottom cap layer of the insulating stack protecting the terminal copper pad. An organic passivation layer is formed and patterned over the top of the insulating stack, and the bottom cap layer over the terminal copper pad is removed. A ball limiting metallurgy (BLM) stack is deposited over the organic passivation layer and terminal copper pad, and a solder ball connection is formed on a patterned portion of the BLM stack.

Abstract: A method of manufacturing a wiring board is disclosed. The wiring board has: a capacitor, having multiple electrode layers which oppose each other with a dielectric layer in between, that is connected to a semiconductor chip; one or more via wirings which pierce the electrode layers and which are connected to the semiconductor chip, and pattern wirings connected to the via wirings. The method includes: forming the electrode layers, each having one or more through holes which the via wirings pierce, and the dielectric layer, and forming the capacitor; installing the capacitor such that the capacitor opposes the pattern wirings over an insulating layer; forming one or more via holes which reach the pattern wirings from the through holes; and forming the via wiring in the via hole.

Abstract: Methods and apparatus for processing substrates to improve polishing uniformity, improve planarization, remove residual material and minimize defect formation are provided. In one aspect, a method is provided for processing a substrate having a conductive material and a low dielectric constant material disposed thereon including polishing a substrate at a polishing pressures of about 2 psi or less and at platen rotational speeds of about 200 cps or greater. The polishing process may use an abrasive-containing polishing composition having up to about 1 wt. % of abrasives. The polishing process may be integrated into a multi-step polishing process.

Abstract: The present invention relates to a method for fabricating a metal interconnection line with use of a barrier metal layer formed in a low temperature. The method includes the steps of: forming an inter-layer insulation layer on a substrate; etching predetermined regions of the inter-layer insulation layer to form a plurality of contact openings; forming an ohmic metal layer on the contact openings and the etched inter-layer insulation layer; forming a seed layer on the ohmic metal layer; forming a metal layer on the seed layer and nitriding the metal layer in a repeated number of times to form a barrier metal layer; and forming a metal interconnection line on the barrier metal layer by burying the contact openings.

Abstract: On first and second regions of a substrate are formed a first gate structure including a first gate electrode and a first spacer, and a second gate structure including a second gate electrode and a second spacer, respectively. The first and second spacers are removed to different depths such that side portions of the first and second gate electrodes have different exposed thicknesses. A metal silicide layer is formed on the first and second regions including the first and second gate structures. The metal silicide layer formed on the second gate electrode has a second thickness that is greater than a first thickness of the metal silicide layer formed on the first gate electrode. The spacers in the gate structures of resulting N type and P type MOS transistors are removed to different thicknesses, thereby minimizing deformation in the gate structures and also improving electrical characteristics and thermal stability of the gate electrodes.

Abstract: An interconnect comprises a trench and a number of metal layers above the trench. The trench has a depth and a width. The depth is greater than a critical depth, and the number of metal layers is a function of the width. In an alternate embodiment, a metallization structure having a trench including a metal layer and a second trench including a plurality of metal layers coupled to the metal layer is disclosed. The metal layer is highly conductive, and at least one of the plurality of metal layers is a metal layer that is capable of being reliably wire-bonded to a gold wire. The trench is narrower than the second trench, and at least one of the plurality of metal layers is copper or a copper alloy.

Abstract: A contact via to a surface of a semiconductor material is provided, the contact via having a sidewall which is produced by anisotropically etching a dielectric layer which is placed on via openings. A protective layer is provided on the surface of the semiconductor material. To protect the substrate, an initial etch through an interlayer dielectric is performed to create an initial via which extends toward, but not into the substrate. At least a portion of the protective layer is retained on the substrate. In another step, the final contact via is created. During this step the protective layer is penetrated to open a via to the surface of the semiconductor material.

Abstract: A semiconductor device may be manufactured by a method that includes forming an etch stop layer on a semiconductor substrate, sequentially forming a first interlayer insulating layer, a first diffusion barrier, a second interlayer insulating layer, and a second diffusion barrier on the etch stop layer, forming a via hole exposing the etch stop layer by etching the second diffusion barrier, the second interlayer insulating layer, the first diffusion barrier, and the first interlayer insulating layer, forming a first trench overlapping the via hole by etching the second diffusion barrier and the second interlayer insulating layer, forming a second trench continuous to the first trench by etching the first diffusion barrier and part of the first interlayer insulating layer, and removing the etch stop layer exposed through the via hole, wherein the first and second trenches are etched under different dry etching conditions.

Abstract: A method for fabricating contact holes in a semiconductor body proceeds from a structure in which: a plurality of trenches isolated from one another by mesa regions are provided in the semiconductor body, and electrodes are provided in the trenches, which electrodes are electrically insulated from the semiconductor body by a first insulation layer, and the upper ends of which electrodes are situated at a deeper level than the upper ends of the trenches. The method comprises the steps of: producing a second insulation layer by subjecting parts of the surface of the structure to a thermal oxidation process, and carrying out a planarization process in such a way that the semiconductor body is uncovered in the region of the mesa regions, and forming the contact holes in the mesa regions using the residues of the second insulation layer remaining after the planarization process as a contact hole mask.

Abstract: Numerous embodiments of a method to assay sacrificial material are disclosed. In one embodiment, a sacrificial material may be analyzed by high performance liquid chromatography. Chemical markers that correlate with material contaminants in the sacrificial material may be identified.

Abstract: By improving the purity of metal lines and the crystalline structure, the overall performance of metal lines, especially of highly scaled copper-based semiconductor devices, may be enhanced. The modification of the crystalline structure of the metal lines may be performed by a heat treatment generating locally restricted heating zones, which are scanned along the length direction of the metal lines, and/or a heat treatment comprising a heating step in a vacuum ambient followed by a heating step in a reducing ambient.

Abstract: In a method according to the present invention, a substrate thinning process is performed on a bumped substrate prior to the ultimate solder reflow process to heal bump defects caused by the substrate thinning process. Concurrently, the risk of substrate breakage is reduced compared to the prior art process since the number of process steps, requiring handling of thinned substrates, is reduced.

Abstract: An integrated circuit interconnect is fabricated by using a mask to form a via in an insulating layer for a conductive plug. After the plug is formed in the via, a thin (e.g., <100 nm) isolation layer is deposited over the resulting structure. An opening is created in the isolation layer by using the same mask at a different radiation exposure level to make the opening more narrow than the underlying plug. A conductive line is then formed which makes electrical contact with the plug through the opening in the isolation layer. By vertically separating and electrically isolating the conductive plug from adjacent conductive lines, the isolation layer advantageously reduces the likelihood of an undesired electrical short occurring between the conductive plug and a nearby conductive line.

Abstract: Recessing a trench using feed forward data is disclosed. In one embodiment, a method includes providing a region on a wafer including a trench area that includes a trench and a field area that is free of any trench, and a material applied over the region so as to fill the trench in the trench area and form a step between the trench area and the field area; etching to partially etch the trench; determining a target etch duration (tD) for etching to the target depth (DT); and etching the trench to the target depth (DT) for a period approximately equal to the target etch duration (tD). The target etch duration tD may be fed forward for recessing another trench to the target depth DT. The method does not require a send ahead wafer, is fully compatible with conventional automated processes and provides in-situ etch time correction to each wafer.

Abstract: A host and ancillary tool interface methodology for distributed processing is described. The host tool manages a process, except for the generation of a product used in the process. To generate the product, the host tool provides an indication to an ancillary tool that the product is to be generated, and the ancillary tool generates the product after detection of the indication with no further intervention by the host tool. To provide the indication, the host tool preferably activates a control line whose voltage is monitored by the ancillary tool, or alternatively, sets one or more bits in a memory which is periodically checked by the ancillary tool.

Abstract: A method to anisotropically etch an oxide/silicide/poly sandwich structure on a silicon wafer substrate in situ, is disclosed, using a single parallel plate plasma reactor chamber and a single inert cathode, with a variable gap between cathode and anode. This method has an oxide etch step and a silicide/poly etch step. The fully etched sandwich structure has a vertical profile at or near 90° from horizontal, with no bowing or notching.

Abstract: To improve the shape of a gate electrode having SiGe, after patterning a gate electrode 15G having an SiGe layer 15b by a dry etching process, a plasma processing (postprocessing) is carried out in an atmosphere of an Ar/CHF3 gas. Thereby, the gate electrode 15G can be formed without causing side etching at two side faces (SiGe layer 15b) of the gate electrode 15G.

Abstract: Methods for etching chromium and forming a photomask using a carbon hard mask are provided. In one embodiment, a method of a chromium layer includes providing a substrate in a processing chamber, the substrate having a chromium layer partially exposed through a patterned carbon hard mask layer, providing a process gas containing chlorine and carbon monoxide into the etching chamber, and maintaining a plasma of the process gas and etching the chromium layer through the carbon hard mask layer. The method of etching a chromium layer through a patterned carbon hard mask layer is useful for fabricating photomasks.

Abstract: A method and an apparatus for performing the method. The method includes: (a) providing an apparatus, wherein the apparatus comprises (i) a chamber, (ii) a plasma device being in and coupled to the chamber, (iii) a shower head being in and coupled to the chamber, and (iv) a chuck being in and coupled to the chamber; (b) placing the substrate on the chuck; (c) using the plasma device to receive a plasma device gas and generate a plasma; (d) directing the plasma at a pre-specified area on the substrate; and (e) using the shower head to receive and distribute a shower head gas in the chamber, wherein the plasma device gas and the shower head gas are selected such that the plasma and the shower head gas when mixed with each other result in a chemical reaction that forms a film at the pre-specified area on the substrate.

Abstract: A SiOC layer and/or a SiC layer of an etch stop layer may be improved by altering the process used to form them. In a bi-layer structure, a SiOC layer and/or a SiC layer may be improved to provide better reliability. A silicon carbide (SiC) layer may be used to form a single-layer etch stop layer, while also acting as a glue layer to improve interface adhesion. Preferably, the SiC layer is formed in a reaction chamber having a flow of substantially pure trimetholsilane (3MS) streamed into and through the reaction chamber under a pressure of less than about 2 torr therein. Preferably, the reaction chamber is energized with high frequency RF power of about 100 watts or more. Preferably, the SiOC layer is formed in a reaction chamber having a flow of 3MS and CO2, and is energized with low frequency RF power of about 100 watts or more.

Abstract: A transfer chamber for a cluster system includes a first body, a second body attached at one side of the first body, and a cover combined with an upper portion of the first body. The transfer chamber further includes a third body at another side of the first body, wherein the third body has the same shape as the second body.

Abstract: The present invention relates to a woven polyester fabric for use in airbags. The present invention includes a woven fabric using a polyester filament yarn, wherein the polyester filament yarn has a tenacity of about 65 cN/tex or greater and an Instantaneous Thermal Creep (ITC) at 100° C. of about 0.5% or less. Additional embodiments of the present invention include an airbag made from the woven polyester fabric. Woven fabrics of the present invention can reduce the extent of seam combing during a hot module deployment of an airbag.

Abstract: The method for making UV-absorbing glass, which transmits in a visible range, includes melting raw materials to form a melt and producing the melt under oxidative conditions. The UV-absorbing glass is free of PbO and has the following composition (in % by weight): SiO2, 55-79; B2O3, 3-25; Al2O3, 0-10; Li2O, 0-10; Na2O, 0-10; K2O, 0-10; MgO, 0-2; CaO, 0-3; SrO, 0-3; BaO, 0-3; ZnO, 0-3; ZrO2, 0-3; CeO2, 0-1; Fe2O3, 0-1; WO3, 0-3; Bi2O3, 0-3; MoO3, 0-3; with ? Li2O+Na2O+K2O=0.5 to 16 and ? MgO+CaO+SrO+BaO+ZnO=0-10. The melt composition is characterized by including 0.1 to 10 % TiO2 and from 0.01-10 % As2O3. The glass made by the method and its properties are also disclosed. The glass is useful in lamps, LCD displays, monitors and glass-to-metal seals with molybdenum, tungsten and Fe—Co—Ni alloys.

Abstract: A process for making a ceramic body that includes the following steps: providing a starting powder mixture, the starting powder mixture comprises between about 15 volume percent and about 35 volume percent boron carbide powder and at least about 50 volume percent alumina powder and no more than about 5 volume percent of a sintering aid; and consolidating the powder mixture at a temperature equal to between about 1400 degrees Centigrade and 1850 degrees Centigrade to achieve a ceramic with a density equal to greater than 99 percent of theoretical density.

Abstract: The present invention provide a high dense aluminum nitride sintered body, a preparing method thereof, and a member for manufacturing semiconductor using the sintered body which has excellent leakage current characteristic, enough adsorbing property, good detachment property and excellent thermal conductivity and so can be applied to even a member for manufacturing semiconductor requiring high volume resistivity like the coulomb type electrostatic chucks as well as the Johnsen-Rahbek type electrostatic chucks.

Abstract: A yttria sintered body is provided which includes yttria as a principal ingredient and 5 to 40 vol. % silicon nitride, and which exhibits enhanced corrosion resistance and mechanical strength.

Abstract: Catalysts comprising a combination of molecular sieve having a pore diameter of from about 4 to 8 angstroms and a catalytically-effective amount of molybdenum hydrogenation component in an amorphous aluminum phosphate binder provide processes for isomerizing xylene and dealkylating ethylbenzene in feed streams that exhibit stability, selectivity and low ring loss.