Abstract: Provided are a charge trap memory device and a method of manufacturing the same. The charge trap memory device may comprise a gate structure including a plurality of metal oxide nanodots discontinuously arranged as a charge trap site on a substrate.

Abstract: An integrated circuit system that includes: providing a substrate with an NFET device and a PFET device; forming an NFET first liner and an NFET first spacer over the NFET device; forming a PFET first liner and a PFET first spacer over the PFET device; forming a punch-through suppression layer within a PFET source/drain; forming an NFET differential spacer; and forming a PFET differential spacer.

Abstract: A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a second conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one terraced trench in the epitaxial layer. The terraced trench has a plurality of portions that differ in width to define at least one annular ledge therebetween. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material lining the annular ledge and said trench bottom and into adjacent portions of the epitaxial layer. The dopant is diffused to form at least one annular doped region in the epitaxial layer and at least one other region located below the annular doped region.

Abstract: A fin-channel recess-gate MISFET has a fin channel including a first portion configured by a portion of a silicon substrate and a second portion configured by a pair of silicon layers selectively grown on the silicon substrate. The first portion is disposed below the recess of the recess gate and above an isolation film of a STI structure formed on the silicon substrate. The second portion is disposed above the recess of the recess gate.

Abstract: The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate is formed within the semiconductor substrate between the pair of the source/drain regions.

Abstract: A power transistor includes a first semiconductor region of a first conductivity type extending over and in contact with a second semiconductor region of the first conductivity type. Gate trenches extend into the first semiconductor region. Well regions of a second conductivity type extend over the first semiconductor region and between adjacent gate trenches. A sinker trench extends through the first semiconductor region and terminates within the second semiconductor region, and is laterally spaced from an outer one of the gate trenches with no well regions abutting sidewalls of the sinker trench. Source regions of the first conductivity type extend over the well regions. A conductive material in the sinker trench makes electrical contact with the second semiconductor region along the bottom of the sinker trench and with a drain interconnect layer extending along the top of the sinker trench.

Abstract: Embodiments relate to a semiconductor device, and to a semiconductor device and a method for manufacture that may improve a performance of a MOSFET device. According to embodiments, a semiconductor device may include a gate pattern formed of a gate dielectric layer formed in an active area of a semiconductor substrate and a first gate electrode pattern formed on the gate dielectric layer, an oxide pattern formed at both sides of the first gate electrode pattern, and a second gate electrode pattern formed on the first gate electrode pattern including the oxide pattern, a lightly doping drain (LDD) area formed in the inside of the substrate of the lower area of the oxide pattern, a spacer formed on both side-walls of the gate pattern, source/drain areas formed on the surface of the substrate of both sides of the gate pattern including the spacer, and a salicide film formed in the gate pattern and the source/drain areas.

Abstract: A semiconductor device includes a gate, extension layers, source drain layers, and silicide layers. The gate is formed on one of a n-type semiconductor substrate and a n-type through a gate insulation film. The extension layers are p-type semiconductors and formed under sidewalls which are formed on both sides of the gate. The source drain layers are p-type semiconductors and formed in contact with the outsides of the extension layers. The silicide layers are formed on surface regions of the source drain layers. The extension layers include inhibitor elements which inhibit p-type impurity diffusion in the extension layers. The silicide layers do not substantially include the inhibitor elements.

Abstract: The method of the present invention includes providing a semiconductor substrate with a recess; performing a pre-cleaning step on the semiconductor substrate; and performing a first reduction step, a lateral etching step and a second reduction step on the semiconductor substrate. The MOS structure includes a semiconductor substrate, a gate structure on the semiconductor substrate, a pair of recesses with beak sections extending to and under the gate structure, and a strain material filling the recess. The recess inside the semiconductor substrate processed by the method including the lateral etching step forms a beak section.

Abstract: An object of the present invention is to apply an insulating film of cure and high quality that is suitably applicable as gate insulating film and protective film to a technique that the insulating film is formed on the glass substrate under a temperature of strain point or lower, and to a semiconductor device realizing high efficiency and high reliability by using it. In a semiconductor device of the present invention, a gate insulating film of a field effect type transistor with channel length of from 0.35 to 2.5 ?m in which a silicon nitride film is formed over a crystalline semiconductor film through a silicon oxide film, wherein the silicon nitride film contains hydrogen with the concentration of 1×1021/cm3 or less and has characteristic of an etching rate of 10 nm/min or less with respect to mixed solution containing an ammonium hydrogen fluoride (NH4HF2) of 7.13% and an ammonium fluoride (NH4F) of 15.4%.

Abstract: A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the semiconductor mesa and filling any undercut region at edges of the semiconductor mesa.

Abstract: A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area.

Abstract: Multi-gate MOS transistors and fabrication methods are described, in which the transistor semiconductor body thickness or width is lithography independent, allowing scaled triple and quad-gate devices having semiconductor bodies smaller than a lateral gate length dimension. A form structure is provided over a semiconductor wafer starting structure, and spacers are formed along one or more sidewalls of an opening in the form structure. A semiconductor material is deposited in the opening by epitaxial growth or other deposition process, and the form structure and the spacer are removed. A gate structure is then formed along the top and sides of a central portion of the formed semiconductor body. The spacer may be L-shaped, providing an undercut or recess at the bottom of the semiconductor body sidewall, and the gate may be formed in the undercut area to allow fabrication of more than three gates.

Abstract: A finFET structure and a method of fabricating the finFET structure. The method includes: forming a silicon fin on a top surface of a silicon substrate; forming a gate dielectric on opposite sidewalls of the fin; forming a gate electrode over a channel region of the fin, the gate electrode in direct physical contact with the gate dielectric layer on the opposite sidewalls of the fin; forming a first source/drain in the fin on a first side of the channel region and forming a second source/drain in the fin on a second side of the channel region; removing a portion of the substrate from under at least a portion of the first and second source/drains to create a void; and filling the void with a dielectric material. The structure includes a body contact between the silicon body of the finFET and the substrate.

Abstract: Provided is a metallization system, a method for manufacture therefore, and a semiconductor device. The metallization system, in one embodiment, comprises a dielectric layer, as well as an interconnect feature located over the dielectric layer. The interconnect feature, in this embodiment, includes one or more openings extending therethrough, the one ore more openings having a radius of curvature of greater than about 150 nm.

Abstract: Gate electrode structures used in field effect transistors and integrated circuits and methods of manufacture are disclosed. Improved work function and threshold modulation are provided by the methods and structures.

Abstract: A method is provided for electroplating a gate metal or other conducting or semiconducting material directly on a dielectric such as a gate dielectric. The method involves selecting a substrate, dielectric layer, and electrolyte solution or melt, wherein the combination of the substrate, dielectric layer, and electrolyte solution or melt allow an electrochemical current to be passed from the substrate through the dielectric layer into the electrolyte solution or melt. Methods are also provided for electrochemical modification of dielectrics utilizing through-dielectric current flow.

Abstract: An IC is provided that includes at least one SRAM cell in which the performance of the SRAM cell is enhanced, yet maintaining good stability and writability. In particular, the present invention provides an IC including at least one SRAM cell wherein the gamma ratio is about 1 or greater. In the present invention, the gamma ratio is increased with degraded pFET device performance. Moreover, in the inventive IC there is no stress liner boundary present in the SRAM region and ion variation for all devices is reduced as compared to that of a conventional SRAM structure. The present invention, solves the above by providing an integrated circuit (IC) that comprises at least one static random access memory cell including at least one nFET and at least one pFET; and a continuous relaxed stressed liner located above and adjoining the at least one nFET and the at least one pFET.

Abstract: An integrated circuit (IC) structure including a SRAM cell is provided in which the performance of the pass-gate transistors is degraded in order to increase the beta ratio of the transistors within the SRAM cell. In particular, the increased beta ratio is obtained in the present invention by intentionally improving only the performance of the pull-down transistors, while degrading the performance of the pass-gate transistors. This result is achieved in the present invention by implementing stress memorization technique on logic complementary metal oxide semiconductor (CMOS) nFETs and SRAM pull-down transistors to improve the nFET performance. The stress memorization technique is not performed at the pFET region to avoid performance degradation as well as at the SRAM pass-gate transistors to avoid the improvement. With performance improvement at the pull-down transistors and no performance improvement at the pass-gate transistors, the beta ratio of the SRAM transistors is improved.

Abstract: An integrated circuit system is provided including forming a circuit element on a wafer, forming a stress formation layer having a non-uniform profile over the wafer, and forming an interlayer dielectric over the stress formation layer and the wafer.

Abstract: An integrated circuit includes: a first well of a first conductivity type; a second well of a second conductivity type coming into contact with the first well at a well boundary extending in a gate length direction; a first transistor having a first active region of the second conductivity type provided in the first well; and a second transistor which has a second active region of the second conductivity type provided in the first well and differing from the first active region in length in a gate width direction. The center location of the first active region in the gate width direction is aligned with the center location of the second active region in the gate width direction with reference to the well boundary.

Abstract: Radiation hardened integrated circuit devices may be fabricated using conventional designs and process, but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. An exemplary BGR structure includes a high-dose buried guard ring (HBGR) layer which is contacted to ground through the backside of the wafer or circuit die, thus forming a Backside BGR (BBGR) structure. In certain embodiments, the starting wafer may be highly doped to reduce the resistance from the HBGR to the back of the wafer, which is then further contacted to ground through the package. The performance of such devices may be further improved by using an electrically conductive adhesive to attach the die and to electrically connect the silicon substrate region to the package's conductive header, substrate, or die attach pad, which in turn is typically connected to one or more package pins/balls.

Abstract: Provided are an abrupt metal-insulator transition (MIT) device for bypassing super-high voltage noise to protect an electric and/or electronic system, such as, a high-voltage switch, from a super-high voltage, a high-voltage noise removing circuit for bypassing the super-high voltage noise using the abrupt MIT device, and an electric and/or electronic system including the high-voltage noise removing circuit. The abrupt MIT device includes a substrate, a first abrupt MIT structure, and a second abrupt MIT structure. The first and second abrupt MIT structures are formed on an upper surface and a lower surface, respectively, of the substrate. The high-voltage noise removing circuit includes an abrupt MIT device chain connected in parallel to the electric and/or electronic system to be protected. The abrupt MIT device chain includes at least two abrupt MIT devices serially connected to each other.

Abstract: A method of manufacture of a semiconductor device includes forming a gate insulating film and gate electrode made of polycrystalline silicon over a semiconductor substrate; implanting ions into the semiconductor substrate to form a semiconductor region as a source or drain; forming a cobalt film and a titanium nitride film over the semiconductor substrate to cover the gate electrode; carrying out annealing to cause a reaction between Co and Si and the semiconductor region to form a CoSi layer; carrying out wet cleaning to remove the titanium nitride film and unreacted cobalt film to leave the CoSi layer over the gate electrode and semiconductor region; carrying out annealing to cause a reaction between the CoSi layer and the gate electrode and semiconductor region to form a CoSi2 layer; carrying out HPM cleaning; and forming over the semiconductor substrate a silicon nitride film by low-pressure CVD to cover the gate electrode.

Abstract: A metal-oxide-semiconductor (MOS) transistor device is disclosed. The MOS transistor device comprises a semiconductor substrate; a gate structure on the semiconductor substrate; source/drain regions on the semiconductor substrate adjacent to the gate structure; an ultra-high tensile-stressed nitride film having a hydrogen concentration of less than 1E22 atoms/cm3 covering the gate structure and the source/drain regions; and an inter-layer dielectric (ILD) film over the ultra-high tensile-stressed nitride film.

Abstract: A semiconductor device and a method for manufacturing the same is disclosed, in which a spacer containing nitrogen therein has a tensile stress and enables device reliability improvement by improving the On-current without regard to the kind of transistor. The semiconductor device includes a semiconductor substrate; a gate insulating layer and a gate electrode on the semiconductor substrate; spacers at sidewalls of the gate electrode, wherein the spacer contains nitrogen to obtain or increase its tensile stress; and source and drain regions in the semiconductor substrate adjacent to the gate electrode.

Abstract: A field effect transistor includes a buried gate pattern that is electrically isolated by being surrounded by a tunneling insulating film. The field effect transistor also includes a channel region that is floated by source and drain regions, a gate insulating film, and the tunneling insulating film. The buried gate pattern and the tunneling insulating film extend into the source and drain regions. Thus, the field effect transistor efficiently stores charge carriers in the buried gate pattern and the floating channel region.

Abstract: A semiconductor device including: a semiconductor layer including an element formation region including an element; a dielectric layer above the semiconductor; an electrode pad above the dielectric; a passivation layer above the pad and having an opening exposing part of the pad; and a bump in the opening and covering part of the element, the bump including first, second, third and fourth edges, the semiconductor having a forbidden region including: a first distance outward from a first line below the first edge, a second distance inward from the first line, a third distance outward from a second line below the second edge, a fourth distance inward from the second line, a fifth distance outward from a third line below the third edge, a sixth distance inward from the third line, a seventh distance outward from a fourth line below the fourth edge, and an eighth distance inward from the fourth line.

Abstract: A semiconductor device comprising: a semiconductor layer including an element formation region, and first and second spaced apart isolation regions; an element in the element formation region; an interlayer dielectric layer above the semiconductor layer; an electrode pad above the interlayer dielectric layer; a passivation layer above the electrode pad and having an opening which exposes part of the electrode pad; and a bump in the opening and covering part of the element when viewed from a top side, the bump including a first edge when viewed from the top side, the first isolation region being formed in a first region, the first region including a first specific distance outward from a first line directly below the first edge of the bump, the second isolation region being formed in a second region, the second region including a second specific distance inward from the first line.

Abstract: An electronic circuit on a semiconductor substrate having isolated multiple gate field effect transistor circuit blocks is disclosed. In some embodiments, an electronic circuit has a substrate having a buried oxide insulating region. A MuGFET device may be formed above the buried oxide region and coupled to a first source of reference potential. A semiconductor device may be formed above the substrate and coupled to a second source of reference potential. A coupling network may be formed to couple the MuGFET device to the semiconductor device.

Abstract: A method of using an III-V semiconductor material as a gate electrode is provided. The method includes steps of providing a substrate; forming a gate dielectric layer on the substrate; and forming the III-V semiconductor material on the gate dielectric layer.

Abstract: The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is an upper source layer of the first conductivity type that is heavily doped. The trench structure includes a sidewall oxide or other suitable insulating material that covers the sidewalls of the trench. The bottom of the trench is filled with a doped polysilicon shield. An interlevel dielectric such as silicon nitride covers the shield. The gate region is formed by another layer of doped polysilicon. A second interlevel dielectric, typically borophosphosilicate glass (BPSG) covers the gate. In operation, current flows vertically between the source and the drain through a channel in the well when a suitable voltage is applied to the gate.

Abstract: Embodiments relate to a semiconductor device and fabricating method thereof. In embodiments, a method of fabricating a semiconductor device may include forming a first gate insulating layer on a semiconductor substrate, performing first plasma nitridation on the first gate insulating layer, forming a second gate insulating layer on the first gate insulating layer, performing second plasma nitridation on the second gate insulating layer, forming a gate electrode metal material on the second gate insulating layer, and forming a metal gate electrode pattern by sequentially etching the gate electrode metal material, the second gate insulating layer, and the first gate insulating layer.

Abstract: A high-frequency Electromagnetic Bandgap (EBG) motion sensor device, and a method for making such a device are provided. The device includes a substantially planar substrate including multiple conducting vias forming a periodic lattice in the substrate. The vias extend from the lower surface of the substrate to the upper surface of the substrate. The device also includes a movable defect positioned in the periodic lattice. The movable defect is configured to move relative to the plurality of vias. A resonant frequency of the Electromagnetic Bandgap (EBG) motion sensor device varies based on movement of the movable defect.

Abstract: A method is for manufacturing a microeletromechanical system resonator having a semiconductor device and a microelectromechanical system structure unit formed on a substrate. The method includes: forming a lower electrode of an oxide-nitride-oxide capacitor unit included in the semiconductor device using a first silicon layer; forming, using a second silicon layer, a substructure of the microelectromechanical system structure unit and an upper electrode of the oxide-nitride-oxide capacitor unit included in the semiconductor device; and forming, using a third silicon layer, a superstructure of the microelectromechanical system structure unit and a gate electrode of a complementary metal oxide semiconductor circuit unit included in the semiconductor device.

Abstract: A microelectromechanical system (MEMS) device with a mechanism layer and a base. The top surface of the base is bonded to the mechanism layer and defines a gap in the top surface of the base. A portion of the mechanism layer is deflected into the gap until it contacts the base, and is bonded to the base.

Abstract: Provided is a micro-electromechanical-system (MEMS) device including a substrate; at least one semiconductor layer provided on the substrate; a circuit region including at least one chip containing drive/sense circuitry, the circuit region provided on the at least one semiconductor layer; a support structure attached to the substrate; at least one elastic device attached to the support structure; a proof-mass suspended by the at least one elastic device and free to move in at least one of the x-, y-, and z-directions; at least one top electrode provided on the at least one elastic device; and at least one bottom electrode located beneath the at least one elastic device such that an initial capacitance is generated between the at least one top and bottom electrodes, wherein the drive/sense circuitry, proof-mass, supporting structure, and the at least one top and bottom electrodes are fabricated on the at least one semiconductor layer.

Abstract: A ferroelectric memory device includes a field effect transistor formed over a semiconductor substrate and including first and second diffusion regions, an interlayer insulation film formed over the semiconductor substrate so as to cover the field effect transistor, a conductive plug formed in the interlayer insulation film in contact with the first diffusion region, and a ferroelectric capacitor formed over the interlayer insulation in contact with the conductive plug. The ferroelectric capacitor includes a ferroelectric film and upper and lower electrodes sandwiching the ferroelectric film respectively from above and below.

Abstract: An obstacle sensor operating by collimation and focusing of the emitted wave comprises: a device (I) for insulating the electromagnetic waves emitted by a generator (1); a device for the automatic control (12, 12?) of the transmitter and of the sensor status; a device (15?÷15??) for amplifying the power of the signals emitted and/or received; different shapes of output lens (14?÷14??) of the antenna, with or without peripheral lobes (16), associated or non associated to microwave sensors (19). The sensor is associable to passive and/or active obstacle warning reflectors with the possibility of discriminating them not only if front but also side and above and below the horizon central azimuth, for road, aircraft and naval applications.

Abstract: Provided is an image sensor module including a lower substrate having a plurality of electrode pads formed on the outer portion of the top surface thereof; an upper substrate installed on the top surface of the lower substrate, the upper substrate having a window formed in the central portion thereof and a plurality of electrode pads formed on the bottom surface thereof to correspond to the respective electrode pads of the lower substrate, the window exposing the central portion of the top surface of the lower substrate; a conductive member interposed between the electrode pads of the lower substrate and the electrode pads of the upper substrate so as to form a conductive line for electrically connecting the electrode pads; and an image sensor module mounted on the top surface of the upper substrate.

Abstract: A protective photochromic barrier film for a light-sensitive printed electronic substrate. Light-sensitive semiconductor devices on a dielectric substrate are electrically connected by conductors. A barrier layer containing photochromic dyes covers some or all of the light-sensitive semiconductor devices. Upon exposure to visible, infrared, or ultraviolet light, the photochromic dyes change chemical structure and decrease the amount of visible or non-visible light that can impinge upon the light-sensitive electronic devices. Upon removal of the visible or non-visible light, the photochromic dyes either revert to their original structure or maintain their altered state.

Abstract: An image sensor includes a semiconductor substrate including an active pixel region and an optical black region, a wiring pattern on the active pixel region and on the optical black region, and a light shielding pattern on the wiring pattern in the optical black region, the light shielding pattern including an opening therein. A dummy pattern is in the optical black region and is spaced apart from the light shielding pattern. The dummy pattern blocks light incident through the openings of the light shielding patter. An inter-metal dielectric layer fills spaces between the patterns, and a passivation layer is on the inter-metal dielectric layer. The dummy pattern includes an opening therein, and a hydrogen diffusion path is provided from the passivation layer, through the opening in the light shielding pattern and the opening in the dummy pattern, to the semiconductor substrate. The dummy pattern may be on the same level as the wiring pattern.

Abstract: According to the present invention, a highly sensitive photo-sensing element and a sensor driver circuit are prepared by planer process on an insulating substrate by using only polycrystalline material. Both the photo-sensing element and the sensor driver circuit are made of polycrystalline silicon film. As the photo-sensing element, a photo transistor is formed by using TFT, which comprises a first electrode 11 prepared on an insulating substrate 10, a photoelectric conversion region 14 and a second electrode 12, and a third electrode 13 disposed above the photoelectric conversion region 14. An impurity layer positioned closer to an intrinsic layer (density of active impurities is 1017 cm?3 or lower) is provided on the regions 15 and 16 on both sides under the third electrode 13 or on one of the regions 15 or 16 on one side.

Abstract: To fabricate a Schottky barrier diode in which a decrease in on current due to parasitic resistance is suppressed, variations in on current are suppressed, and an increase in off current is suppressed. The fabricating method includes the steps of forming an island-shape semiconductor film; doping the island-shape semiconductor film with a first impurity element to form a first impurity region; forming an insulating film so as to cover the island-shape semiconductor film; etching the insulating film to form a first opening and a second opening that partly expose the first impurity region; forming a mask over the insulating film so as to cover the first opening and expose the second opening; doping the first impurity region with a second impurity element to form a second impurity region; and forming a first wiring in contact with the first impurity region exposed at the first opening, and forming a second wiring in contact with the second impurity region exposed at the second opening.

Abstract: Provided is a semiconductor chip (1) including: at least one fuse element (21); a fuse opening (17) formed above the fuse element (21); and a discharge electrode (31) that is formed below a bottom portion (17a) of the fuse opening (17), and is formed in one of the same layer with the fuse element (21) and the above layer of the fuse element (21). Accordingly, the current caused to flow due to the electrostatic discharge generated at the time of assembling the semiconductor chip can be discharged through the discharge electrode (31). As a result, the current caused to flow due to the electrostatic discharge generated at the time of assembling the semiconductor chip can be prevented from being discharged through the fuse element, whereby a problem in that a functional failure occurs in the semiconductor chip can be solved.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a semiconductor structure having a silicon-on-insulator (SOI) substrate and a dielectric region is disclosed. The dielectric region is adjacent to the active layer of the SOI substrate and the dielectric region includes a portion of a buried oxide (BOX) layer of the SOI substrate. At least a portion of the dielectric region extends from a surface of the active layer of the SOI substrate to a depth of at least about three microns or greater below the surface of the active layer. Other embodiments are described and claimed.

Abstract: The invention discloses a decoupling capacitor circuit, comprising a plurality of coupled deep trench capacitors connected in series and a plurality of push-pull circuits. The decoupling capacitor circuit controls the voltage across each deep trench capacitor via the push-pull circuit so that it will not be influenced by the defect (leakage current) of the deep trench capacitor or the bias voltage of the parasitic devices.

Abstract: The present invention relates to a memory cell comprising: a resistive structure; at least two electrodes coupled to the resistive structure, and at least one hydrogen reservoir structure, wherein the application of an electrical signal to one of the at least two electrodes causes the electrical resistance of the resistive structure to be modified by altering a hydrogen-ion concentration in the resistive structure.

Abstract: Nanowhiskers are grown in a non-preferential growth direction by regulation of nucleation conditions to inhibit growth in a preferential direction. In a preferred implementation, <001> III-V semiconductor nanowhiskers are grown on an (001) III-V semiconductor substrate surface by effectively inhibiting growth in the preferential <111>B direction. As one example, <001> InP nano-wires were grown by metal-organic vapor phase epitaxy directly on (001) InP substrates. Characterization by scanning electron microscopy and transmission electron microscopy revealed wires with nearly square cross sections and a perfect zincblende crystalline structure that is free of stacking faults.

Abstract: Scribe-line structures and methods of forming such scribe-line structures on a face of a semiconductor substrate are provided. By means of the scribe-line structures and the methods of this invention, physical shock and cracking tendencies along a semiconductor substrate can be minimized during performance of a cutting process on the semiconductor substrate as part of post-fabrication processing. A representative method according to this invention comprises the sequential steps of: forming a lower layer on a semiconductor substrate; forming a molding layer on the lower layer such that the molding layer includes at least one protective contact hole; subsequently forming a dielectric layer and an upper layer on the molding layer so as to fill the protective contact hole, such dielectric layer being formed of a material having a greater mechanical intensity than that of the molding layer; and then forming protective layer patterns on the upper layer.