Abstract: A semiconductor device includes a semiconductor substrate having an upper surface and a lower surface opposed to the upper surface. Integrated circuitry is formed at the upper surface of the semiconductor substrate. A plurality of active through-vias are electrically coupled to the integrated circuitry and extend from the upper surface to the lower surface of the semiconductor substrate. In addition, a plurality of other through-vias extend from the upper surface to the lower surface of the semiconductor substrate and are electrically isolated from any integrated circuitry in the substrate.

Abstract: A porous dielectric element is produced by forming a first dielectric and a second dielectric. The second dielectric is dispersed in the first dielectric. The second dielectric is then removed from the second dielectric by using a chemical dissolution. The removal of the second dielectric from the first dielectric leaves pores in the first dielectric. The pores, which are filled with air, improves the overall dielectric constant of the resulting dielectric element.

Abstract: A low-k organic dielectric material having stable nano-sized porous is provided as well as a method of fabricating the same. The porous low-k organic dielectric material is made from a composition of matter having a vitrification temperature (Tv-comp) which includes a b-staged thermosetting resin having a vitrification temperate (Tv-resin), a pore generating material, and a reactive additive. The reactive additive lowers Tv-comp below Tv-resin.

Abstract: An impurity region having a box-shaped impurity profile is formed. An impurity introducing method includes a step of introducing a desired impurity into a surface of a solid base body, and a step of radiating plasma to a surface of the solid base body after the impurity introducing step thus forming an impurity profile having an approximately box-shape.

Abstract: A semiconductor device with a plastic housing composition includes a semiconductor chip and an internal wiring. The plastic housing composition is electrically conductive and electrically connected to a first contact pad of the internal wiring. A first side of the semiconductor chip is electrically insulated from the plastic housing composition by an insulation layer.

Abstract: A semiconductor device and fabricating method thereof are provided. A first substrate with an inductor cell and a through-electrode is connected to a second substrate having an RF device circuit unit. A connecting electrode can electrically connect the inductor cell to the RF device circuit unit.

Abstract: An integrated circuit package system includes an elevated edge leadframe array, isolating leadframes of the elevated edge leadframe array, validating integrated circuit die attached to the leadframes, and forming integrated circuit packages including the integrated circuit die.

Abstract: A lead-frame circuit package comprises a die and a substrate located thereon to route radio frequency signals to/from the die. The package preferably comprises an exposed pad on the die to receive a power amplifier device wherein the substrate is used to provide high-Q elements such as RF chokes on signal paths to/from the power amplifier device. In this manner, the design benefits from the power capabilities and improved grounding of a lead-frame conductor, whilst also achieving the routeing capabilities and small scale advantages provided by a multi-layer printed circuit substrate.

Abstract: Embodiments in accordance with the present invention relate to the fabrication of packages for semiconductor devices, and in particular to the use of electroplating techniques to form features on the surface of a metal lead frame. In accordance with one embodiment, electroplating is used to fabricate non-integral pin portions shaped to remain securely encapsulated within the plastic molding of the package. In accordance with another embodiment, electroplating may be used to fabricate protrusions on the underside of the lead frame for elevating the package above the PC board, thereby preserving the rounded shape of solder balls used to secure the diepad to the PC board. In accordance with yet another embodiment, electroplating may be used to fabricate raised patterns on the upper surface of the diepad for ensuring uniform spreading of adhesive used to secure the die to the diepad, thereby ensuring level attitude of the die within the package.

Abstract: The invention relates to leadframe semiconductor packages mounted on a heat-sink and fabrication thereof. A system in package (SiP) comprises a leadframe having extension leads, configured with divisional heat sinks serving as power and ground nets. A set of semiconductor dies is attached by adhesive on the central region of the lead frame. Pluralities of wire bonds electrically connect the set of semiconductor dies to the leadframe and to the divisional heat sinks respectively. An encapsulation encloses the leadframe, but leaves the extension leads and the divisional heat sink uncovered, exposing a heat dissipating surface.

Abstract: An integrated circuit package system that includes: providing an electrical interconnect system including a support structure and a lead-finger system; and processing a top edge of the support structure to include a recess for preventing mold bleed.

Abstract: The present invention discloses a tool structure for chip redistribution and method of chip redistribution. The tool structure comprises a base substrate, a separable adhesion film formed on the base substrate, and the patterned glues placed on the separable adhesion film for fixating the dice covered by the core paste materials formed on a fixed substrate. The fixed substrate is bonding on the core paste materials and dice to form the panel wafer. The method comprises printing the pluralities of patterned glues placed on the separable adhesion film and the bonding pluralities of dice covered by the core paste materials, and then, the fixed substrate is bonding on the core paste materials and pluralities of dice. The method further comprises curing and separating the glues and the pluralities of dice with the fixed substrate, and then cleaning the residual glues on the panel wafer (pluralities of dice).

Abstract: A semiconductor system having a substrate (101) including a rigid insulating interposer (110) with a high modulus and a top (140) and a bottom (150) low-modulus tape with flip-attached semiconductor chips (120, 130). The assembled chips, with the passive surfaces facing each other, are located in an opening (114) of the interposer, which has a thickness (111) equal to or smaller than the sum of the assembled two chips. Adhesive material (160) holds the tapes parallel to the interposer and the chip surfaces together. Solder balls (180) and discrete components (170) may be attached to the outside surfaces of the tapes.

Abstract: The present invention proposes a 3D electronic packaging structure with enhanced grounding performance and embedded antenna, and the packaging unit can achieve multi-chip stacking through the signal contacts on the top and bottom surfaces of the unit. A single or multiple grounding layers are on the back of the substrate in the packaging unit to facilitate the grounding for the semiconductor element; further, the packaging unit is applicable to a wafer level packaging process, so the manufacturing cost of each individual packaging unit is reduced. The above grounding layers are also the signal transmission paths of the electronic elements in the packaging structure of the invention, and a single or multiple via holes around the electronic element layers allow electrical signal connection between the top and bottom surfaces of the packaging structure, and thus enable more functionality in the packaging unit.

Abstract: A method and apparatus are provided for multi-chip packaging. A multi-chip package (100) includes a substrate (105) and a plurality of semiconductor dice (110, 120, 130). A first semiconductor die (110) is physically coupled to an upper face of the substrate (105), the first semiconductor die (110) being a smallest one of the plurality of semiconductor dice (110, 120, 130).

Abstract: An integrated circuit package system includes providing a plurality of substrates; inserting a receptor in one of the substrates, the receptor held in and not extending through the one of the substrates; inserting a conductive post in another of the substrates; mounting the one of the substrates and the another of the substrates over one another with the conductive post engaging the receptor to thermally interlock without a separate bonding material; and mounting an integrated circuit mounted on the one of the substrates or the another of the substrates.

Abstract: In a stacked package in which a plurality of packages having semiconductor elements mounted on substrates are stacked, while being electrically connected together, by use of connection sections, wherein the connection sections are formed from pillar-like members and solder joint sections and the upper package is supported on the lower package by pillar-like members.

Abstract: Provided are a semiconductor package in which wiring layers connected to a semiconductor chip electrically contact circuit patterns of a substrate and a method of manufacturing the same. The semiconductor package includes the substrate and the semiconductor chip. The substrate includes a first concave portion disposed on the upper surface thereof and a plurality of the circuit patterns disposed adjacent to the first concave portion. The semiconductor chip is mounted in the substrate to correspond to the concave portion. The semiconductor chip comprises a wafer, pads disposed on the wafer, and wiring layers disposed on the upper surface and on one side surface of the wafer, wherein first portions disposed on the upper surface of the wafer are connected to the pads and second portions disposed on the one side surface of the wafer contact the circuit patterns of the substrate.

Abstract: The present invention provides a structure of package comprising a substrate with a pre-formed die receiving cavity formed and/or terminal contact metal pads formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. At least one re-distribution built up layer (RDL) is formed on the dielectric layer and coupled to the die via contact pad. Connecting structure, for example, UBM is formed over the redistribution built up layer. Terminal Conductive bumps are coupled to the UBM.

Abstract: A chip package including a metal layer, a film-like circuit layer, a chip, a lead matrix and an encapsulant is provided. The film-like circuit layer disposed on the metal layer includes an insulating film disposed on the metal layer and a circuit layer disposed on the insulating film. The circuit layer has a plurality of conductive traces. The chip disposed above the metal layer is electrically connected to the conductive traces. The lead matrix having a plurality of leads is disposed outside the chip. At least part of the leads are electrically connected to the conductive traces. The encapsulant at least encapsulates the chip, the film-like circuit layer, at least part of the leads, and at least part of the metal layer.

Abstract: On a case member of a semiconductor device, a screw block terminal or the like for connection to external equipment is attached. The screw block terminal or the like arranged on a region inside a base plate is attached to a terminal attachment member. Terminal attachment member has wall-like bodies, similar to wall-like bodies formed on a sidewall portion, formed along the direction of extension of terminal attachment member. On one end of terminal attachment member in the direction of extension, a side fitting portion is formed that corresponds to the wall-like body, and by fitting the side fitting portion to a space between sidewall portion and the wall-like body, terminal attachment member is fixed on case member. Thus, a semiconductor device is provided that allows high degree of freedom with simpler structure, as to the position of attaching a screw block terminal or a pin terminal to the case member.

Abstract: A semiconductor device with a chip (505), its position defining a plane, and an insulating substrate (503) with first and second surfaces; the substrate is substantially coplanar with the chip, without warpage. One of the chip sides is attached to the first substrate surface using adhesive material (504), which has a thickness. The thickness of the adhesive material is distributed so that the thickness (504b) under the central chip area is equal to or smaller than the material thickness (504a) under the peripheral chip areas. Encapsulation compound (701) is embedding all remaining chip sides and the portions of the first substrate surface, which are not involved in the chip attachment. When reflow elements (720) are attached to the substrate contact pads, they are substantially coplanar with the chip.

Abstract: Integrated circuit packages that connect solder balls between solder ball pads of a die and substrate pads of a printed circuit board (PCB). The solder balls are electrically disconnected from any circuit of the die, i.e., “dummy” solder balls, and are used to temporarily hold the die in position with respect to the PCB until the circuit is wire bonded and an underfill material is cured between the die and the PCB to more permanently connect them together. The underfill material is selected to have a coefficient of thermal expansion (CTE) that is substantially equal to the CTE of the solder balls to prevent thermal mismatch problems. An overmolding compound is disposed about the die and the underfill material and about the wire bonds to complete the package. Various arrangements of the solder ball pads on the die include columnar and row, corner, diagonal, cross, and periphery arrangements.

Abstract: The invention provides a printed circuit board having an embedded semiconductor chip, includes: a carrier board having a first and an opposing second surface and a through hole penetrating the first and second surfaces; a semiconductor chip disposed in the through hole and having an active surface and an inactive surface, wherein the active surface includes a plurality of electrode pads; at least one non photoimagable laminating layer formed on the first surface of the carrier board and with a through hole to expose the inactive surface of the semiconductor chip; a dielectric layer and a circuit layer formed on the second surface of the carrier board and the active surface of the semiconductor chip, wherein the circuit layer electrically connects to the electrode pads of the semiconductor chip, thereby preventing the carrier board from warpage due to temperature variations and an asymmetric structure during a single-side circuit formation process of the carrier board.

Abstract: There is provided a semiconductor package including: a substrate having a plurality of electrode pads on a surface thereof; a semiconductor chip mounted on the substrate, the semiconductor chip electrically connecting with the plurality of electrode pads; and a stiffener arranged on the substrate so as to surround the semiconductor chip. The stiffener includes: an insulating material layer; and a rigid plate mounted substantially parallel to a surface of the substrate in the insulating material layer, the rigid plate having formed therein a plurality of through holes, at least a part of the through holes being filled with the insulating material.

Abstract: With a conventional semiconductor device, there occurs deterioration in adhesion strength of bonded parts between a lid and a substrate. A semiconductor device according to an embodiment of the invention includes a substrate, a semiconductor chip with one of surfaces thereof, facing downward, mounted on the substrate, and a lid having a depressed part for accommodating the semiconductor chip, and a flange linked with the depressed part. Parts of the flange of the lid are bonded to the substrate by means of a binder. The flange is warped arcuately against the substrate, as seen in a side view. The bottom surface of the depressed part of the lid is bonded to the other surface of the semiconductor chip by means of a binder.

Abstract: A multi-chip package may include at least one integrated circuit die disposed on a substrate, and a local heat spreader is thermally coupled with the die. A global heat spreader is thermally coupled with this local heat spreader. The global heat spreader may also be coupled with one or more other local heat spreaders that are each coupled with another die disposed in the multi-chip package. Other embodiments are described and may be claimed.

Abstract: A heat-dissipating structure and a heat-dissipating semiconductor package having the same are disclosed in the present invention. The heat-dissipating semiconductor package includes a chip carrier, a flip chip semiconductor chip attached and electrically connected to the chip carrier, and a heat sink bonded to the flip chip semiconductor chip via a thermal interface material, such as a solder material, wherein a groove is formed on the heat sink around the bonding area of the thermal interface material, and a blocking layer, such as a metal oxide layer, is formed on the surface of the groove to reduce the wetting capability of the thermal interface material, thus further prevents the thermal interface material from wetting the groove in the fusion process performed the thermal interface material, therefore, it ensures the thermal interface material has sufficient thickness for forming solder bonding between the heat sink and the flip chip semiconductor chip.

Abstract: The present semiconductor structure includes a substrate having a planar surface, a semiconductor chip attached to the planar surface of the substrate, the chip preferably being of the same thickness as or thinner than the substrate, and a package body attached to the substrate and to the semiconductor chip. The semiconductor chip and substrate are sufficiently rigidly attached so that substantial force applied parallel to the planar surface of the substrate may be transmitted therebetween, reducing temperature-change stress on solder balls which connect the substrate with a PCB. The semiconductor chip with advantage is thinned to reduce the stress on the solder balls.

Abstract: The present invention relates to a three-dimensional package and method of making the same. The package includes a first substrate, a first chip, a second substrate, a second chip, a spacer, and a first molding compound. The first chip is electrically connected to the first substrate. The second substrate is electrically connected to the first substrate. The second chip is electrically connected to the second substrate. One end of the spacer is attached to the first chip, and the other end of the spacer is attached to the second chip. The first molding compound encapsulates the first substrate, the first chip, the second substrate, the second chip, and the spacer. In the present invention, the adhesion between the spacer and the second chip is enhanced, and the overall thickness of the three-dimensional package is reduced.

Abstract: A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure.

Abstract: The process begins with separate device wafers having complimentary chips. Thin metal capture pads, having a preferred thickness of about 10 microns so that substantial pressure may be applied during processing without damaging capture pads, are deposited on both device wafers, which are then tested and mapped for good chip sites. A handle wafer is attached to one device wafer, which can then be thinned to improve via etching and filling. Capture pads are removed and replaced after thinning. The device wafer with handle wafer is diced, and good chips with attached portions of the diced handle wafer are positioned and bonded to the good chip sites of the other device wafer, and the handle wafer portions are removed. The device wafer having known good 3-D chips then undergoes final processing.

Abstract: A circuit device is placed within an opening of a conductive layer which is then partially encapsulated with an encapsulant so that the active surface of the circuit device is coplanar with the conductive layer. At least a portion of the conductive layer may be used as a reference voltage plane (e.g. a ground plane). Additionally, a circuit device may be placed on a conductive layer such that an active surface of circuit device is between conductive layer and an opposite surface of circuit device. The conductive layer has at least one opening to expose the active surface of circuit device. The encapsulant may be electrically conductive or electrically non-conductive.

Abstract: A ceramic package substrate has a recess. This allows a device in that recess to be close to a die attached to the substrate's top side, for better performance. The device may be an array capacitor, an in-silicon voltage regulator, or another device or devices.

Abstract: An integrated circuit package includes a first capacitor supported by a surface of a substrate, and a second capacitor supported by the surface of the substrate. The first capacitor is within a die shadow region, and the second capacitor lies outside of the die shadow region.

Abstract: A semiconductor package for power transistors and the like has a heat sink flange with at least one die mounted thereon, a non-ceramic based window frame mounted thereon adjacent the die, and a plurality of leads mounted on the window frame and electrically coupled to the die by wire bonds. The non-ceramic based window frame is thermally matched to copper or other highly conductive material typically used for the flange, to facilitate assembly of the semiconductor package at high temperatures. The non-ceramic based window frame is flexible and is thermally matched to the highly conductive flange so as to expand and contract at a rate similar to the flange to prevent failure during assembly of the semiconductor package. The non-ceramic based material of the window frame includes a matrix of principally organic material, such as polytetrafluorethylene, filled with fibers which may be glass fibers or ceramic fibers.

Abstract: An integrated circuit die includes one or more tubular-shaped conductive bumps disposed on one side thereof. The tubular-shaped bumps may comprise copper, and may be used for input/output (I/O) signaling. The die may also include solid bumps for I/O and/or power delivery. The tubular-shaped bumps are relatively more compliant than the solid bumps, and may alleviate the effects of thermally induced stresses. Other embodiments are described and may be claimed.

Abstract: A chip package includes: a circuit board formed with conductive traces; a semiconductor chip formed with conductive pads; a bridging member sandwiched between the circuit board and the semiconductor chip and including an elastic dielectric body and spaced apart flexible conductive lines, each of which extends through the elastic dielectric body to contact a respective one of the conductive traces of the circuit board and a respective one of the conductive pads of the semiconductor chip; and a holding member pressing the semiconductor chip against the elastic dielectric body so as to result in pressing action of the elastic dielectric body against the circuit board.

Abstract: There is provided a composition that is suitably used for a flip chip mounting process or a bump-forming process. The composition comprises a first component 3a, a second component 3b, metal particles 1,1? and a convection additive. The metal particles 1,1? are dispersed in the second component 3b. The convection additive is contained in the second component 3b. The first component 3a is contained in an interior of at least one particle 1. When such at least one metal particle 1 melts upon heating, the first component 3a comes in contact with the second component 3b to form a thermoset resin 3c. The convection additive is capable of generating a gas upon heating, so that the gas provides a convection effect in the composition.

Abstract: A semiconductor device including: a semiconductor layer including an element formation region including an element; an interlayer dielectric layer above the semiconductor layer; an electrode pad above the interlayer dielectric layer; a passivation layer above the electrode pad and having an opening exposing at least part of the electrode pad; and a bump in the opening and covering at least part of the element, the bump including first and second edges, the semiconductor layer having a forbidden region including: a first specific distance outward from a first line directly below the first edge, a second specific distance inward from the first line, a third specific distance outward from a second line directly below the second edge, and a fourth specific distance inward from the second line.

Abstract: A structure for controlled collapse chip connection disposed above a substrate. The substrate has two faces, with the second face being disposed substantially parallel to the first face. A contact pad in signal communication with the integrated circuit is disposed on the second face. A first passivation layer forms a first angled aperture substantially above the contact pad. The angled aperture increasing in circumference with increasing distance from the contact pad. A ball-limiting metallurgy (BLM) disposed within the aperture, with a center section in signal communication with the contact pad, an angled section extending away from the center portion and terminated in an edge section. A second passivation layer disposed on the first passivation layer, and partially encapsulating the edge region of the BLM with a second angled aperture. The shape and slope of the BLM and the second angled aperture controls the formation of a solder ball.

Abstract: The objective of the invention is to present a mounting method by which mounting at higher densities and finer pitches can be handled so as to mount extremely small conductive balls. The mounting method of the present invention may be used to prepare porous base member 210 and mask set 220 with a 2-layer structure to be placed on base member 210, on which multiple through-holes 222a and 224a are created; vacuum adsorption is applied to base member 210 so as to form an adsorption surface on the surface of base member 210 that is exposed by through-holes 222a and 224a; microballs 260 are dropped into through-holes 222a and 224a of mask set 220; and microballs 260 are adsorbed by base member 210. Then, adsorbed microballs 260 are pressed against multiple terminal regions 108 that are formed on one surface of substrate 100 in order to transfer them there.

Abstract: A planarized nanowire structure and a method for planarizing a nanowire structure are presented. The method provides nanowires with tips, formed overlying a substrate. A first insulator layer is deposited partially covering the nanowires. The first insulator layer is coated with a spin-on insulator layer, completely covering the nanowires. In some aspects of the method, the spin-on insulator layer is annealed. The spin-on insulator layer is then polished with a slurry and, in response to the polishing, a planarized insulator surface is formed with exposed nanowire tips.

Abstract: An interconnect structure is provided, including a layer of dielectric material having at least one opening and a first barrier layer on sidewalls defining the opening. A ruthenium-containing second barrier layer overlays the first barrier layer, the second barrier layer having a ruthenium zone, a ruthenium oxide zone, and a ruthenium-rich zone. The ruthenium zone is interposed between the first barrier layer and the ruthenium oxide zone. The ruthenium oxide zone is interposed between the ruthenium zone and the ruthenium-rich zone.

Abstract: The present invention relates to methods and systems for the metallization of semiconductor devices. One aspect of the present invention is a method of depositing a copper layer onto a barrier layer so as to produce a substantially oxygen free interface therebetween. In one embodiment, the method includes providing a substantially oxide free surface of the barrier layer. The method also includes depositing an amount of atomic layer deposition (ALD) copper on the oxide free surface of the barrier layer effective to prevent oxidation of the barrier layer. The method further includes depositing a gapfill copper layer over the ALD copper. Another aspect of the present invention is a system for depositing a copper layer onto barrier layer so as to produce a substantially oxygen-free interface therebetween. In one embodiment, the integrated system includes at least one barrier deposition module. The system also includes an ALD copper deposition module configured to deposit copper by atomic layer deposition.

Abstract: A micronized wiring structure is obtained by optimizing film forming modes of barrier metal films as being adapted respectively to a via-hole and a wiring groove, wherein sputtering processes are adopted herein, which are specifically the multi-step sputtering process for formation of the barrier metal film over the via-hole, and the one-step, low-power sputtering process for formation of the barrier metal film over the wiring groove, to thereby realize improved electric characteristics such as via-hole resistance and wiring resistance, and improved wiring reliabilities such as Cu filling property and electro-migration resistance.

Abstract: This invention discloses a semiconductor device including an insulating film having a recess therein; an electric conductor formed inside the recess; a manganese silicate film formed on an upper surface of the conductor, the manganese silicate film being formed of a reaction product of a manganese with a silicon oxide insulating film. A method for manufacturing such a semiconductor device is also described.

Abstract: A method for fabricating a semiconductor device. The method includes providing a semiconductor substrate including a surface region. The method forms a first interlayer dielectric overlying the surface region and forms an interconnect layer overlying the first interlayer dielectric layer. The method also forms a low K dielectric layer overlying the interconnect layer, which has a predetermined shape. The method forms a copper interconnect layer overlying the low K dielectric layer. In a preferred embodiment, the low K dielectric layer maintains the predetermined shape using a dummy pattern structure provided within a portion of the low K dielectric layer to mechanically support and maintain the predetermined shape of the low K dielectric layer between the interconnect layer and the copper interconnect layer.

Abstract: Means for Solution: This interposer (10) comprises the silicon substrate (12), a plurality of through-hole conductors (20) formed on the above-described silicon substrate, and a capacitor (15) formed with the upper electrodes (14) and the lower electrodes (18) formed by extending the land portions of the above-described through-hole conductors and the dielectric layer (16) formed between the both electrodes. The rewiring layers (23-1, 23-2) formed as desired are formed on the layers other than the above-described capacitor layer.

Abstract: A semiconductor device has a multilayer interconnection structure, wherein the multilayer interconnection structure comprises at least a first interconnection layer and a second interconnection layer formed over the first interconnection layer, the first interconnection layer comprises a first conductor pattern embedded in a first interlayer insulation film and constituting a part of an interconnection pattern and a second, another interconnection pattern embedded in the first interlayer insulation film, the second interconnection layer comprises a third conductor pattern embedded in a second interlayer insulation film and constituting a part of said interconnection pattern, the third conductor pattern has an extension part in a part thereof so as to extend in a layer identical to the third conductor pattern, the third conductor pattern being electrically connected to the first conductor pattern at a first region of the extension part via a first via plug, the extension part making a contact with the second c