Abstract: A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.

Abstract: The present invention is directed to a system that programmably interconnects integrated circuit chips and other components at near-intra-chip density. The system's contact structure allows it to adapt to components with a wide variety of contact spacings and interconnection requirements, the use of releasable attachment means allows component placement to be modified as needed, the system identifies the contacts and the components to facilitate specifying the inter-component connections, and the system provides signal conditioning and retiming to minimize issues with signal integrity and signal skew.

Abstract: A logic circuit is disclosed that is tolerant of logic signals with voltages different from the voltage of the logic circuit power supply. In one embodiment, the logic circuit has an inverting amplifier therein, the amplifier having at least one input and an output and is powered by the power supply. A first transistor, in responsive to the output of the amplifier, biases the input of the amplifier to assure substantially no static current flows through the amplifier when a logic-low is present on the amplifier output. A second transistor couples at least one logic input of the logic circuit to the input of the amplifier. In one embodiment, the second transistor impedes static current flow from the first transistor, through the second transistor, to the logic input. Various other embodiments of the logic circuit include a latch/flip-flop, multiplexer, and a complex logic gate.

Abstract: Hardware cells inside of an IC device, such as in a processor circuit, for characterization that replace functional flip-flops that capture inputs or drive outputs in the device. The cells are circuits that are used, in conjunction with a software method, to generate test programs for testing exact I/O transitions for timing measurements at various operating conditions.

Abstract: The invention relates to a programming matrix for the switching of one of n logical inputs to one of j outputs, whereby the programming matrix comprises a slot system with magnetic elements in selected positions, the magnetic and/or electrical properties of which can change or be changed.

Abstract: A circuit including a first stage register that operates in response to a first clock having a period TCYCLE, a programmable delay circuit that introduces a programmable delay to the first clock, thereby creating a second clock, a second stage register that operates in response to the second clock, combinational logic coupled between the first register output and the second register input, and a third register having an input coupled to the second register output. The programmable delay is selected: (1) to have a positive value if the signal delay between the first and second registers exceeds TCYCLE, and (2) such that the signal delay between the second and third registers is less than TCYCLE minus the programmable delay. Additional delayed clocks generated in response to the second clock signal can be used to operate additional second stage registers, thereby staggering the outputs of these second stage registers within TCYCLE.

Abstract: A printed circuit unit implementing with organic transistors is provided. The printed circuit unit includes an input signal circuit, a load circuit and a level shifter. The input signal circuit includes N serially connected organic transistors. When one of the serially connected organic transistors is cut-off, the signal input circuit is cut-off, so that the circuit is maintained to output a correct voltage level. The level shifter circuit includes an organic transistor having a gate for receiving the input signal. The organic transistor can also serve as a load for improving a gain of the level shifter.

Abstract: Disclosed are various embodiments of a differential logic to CMOS logic translator including a level-shifting and buffering stage configured to receive differential inputs and to provide resulting signals with lower common mode voltage. Further, a gain stage is included to receive the resulting signals and to provide increased swing signals. A CMOS buffer is also included and is configured to receive the increased swing signals and to provide a CMOS logic output. Also disclosed is a method of translating a differential logic signal to a CMOS logic signal including level-shifting and buffering differential input signals to provide resulting signals with lower common mode voltage. The method also includes using a gain stage to provide increased swing signals from the resulting lower common mode signals and using a CMOS buffer to provide a CMOS output from the increased swing signals.

Abstract: An apparatus interfaces a first circuit using a first supply voltage and a second circuit using a second supply voltage different from the first supply voltage. The apparatus includes a driver circuit having a driver network comprising driver supply voltage terminals connected to controllable switches. The controllable switches include resistive elements or are separated from resistive elements. A receiver circuit has a receiving network comprising a resistive element and receiver supply voltage terminals and a connection line connecting the driver circuit and the receiving circuit. The controllable switches have two switch configurations, a first switch configuration resulting in a high voltage on the connection line and a second switch configuration resulting in a low voltage on the connection line.

Abstract: An electrically programmable multiple selectable function integrated circuit module has a plurality of optionally selectable function circuits, which receive and manipulate a plurality of input data signals. The outputs of the plurality of optionally selectable function circuits are either interconnected to each other or connected to a plurality of output connectors to transmit manipulated output data signals to external circuitry. The electrically programmable multiple selectable function integrated circuit module has at least one configuration connector, which may be multiplexed with input control and timing signals, connected to a function configuration circuit to receive electrical configuration signals indicating the activation of a program mode and which of the optionally selectable function circuits are to be elected to manipulate the input data signals.

Abstract: Various logic gates and methods for using such are disclosed herein. For example, some embodiments of the present invention provide parallel differential logic gates. Such logic gates include two or more differential input pairs. The collectors of the first transistors in each of the differential pairs are all electrically coupled to an upper voltage via a first load resistor. Similarly, the collectors of the second transistors in each of the differential pairs are all electrically coupled to an upper voltage via a second load resistor. Depending upon the relative values selected for the first and second load resistors, the gate operates as an AND gate or an OR gate.

Abstract: In accordance with some embodiments, logical circuits comprising carbon nanotube field effect transistors are disclosed herein.

Abstract: A sense amplifier circuit provides for high speed sensing with a high speed read operation, with a low capacitance and a low resolution time. The sense amplifier circuit includes a latch circuit having a first inverter circuit and a second inverter circuit cross coupled with each other. The amplifier circuit includes a first discharge device and a second discharge device operatively coupled to the first inverter circuit and the second inverter circuit respectively. The amplifier circuit further includes a first PMOS transistor operatively coupled between the first discharge device and a bit line, and a second PMOS transistor operatively coupled between the second discharge device and a complementary bit line. The amplifier circuit further includes a first NMOS transistor operatively coupled between the first discharge device and a ground voltage, a second NMOS transistor operatively coupled between the second discharge device and the ground voltage.

Abstract: In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.

Abstract: An envelope detector operable to detect and record the minimum and maximum values present in a data stream. In various embodiments, the envelope detector includes a memory operable to store first and second data values, a first comparator, and a second comparator. The first comparator is generally operable to compare the first data value to a first input from the data stream and output a first control signal to cause the memory to store the first input as the first data value if the first input is greater than the first data value. The second comparator is generally operable to compare the second data value to the second input from the data stream and output a second control signal to cause the memory to store the first input as the second data value if the first input is less than the first data value.

Abstract: The present invention provides an output signal driving circuit, which includes: a comparator coupled to a reference voltage for comparing the reference voltage and a voltage level of an output terminal to output a comparison signal; a first switch having a terminal coupled to a first supply voltage and having another terminal coupled to an output terminal, wherein the conductivity of the first switch depends on a first input signal and the comparison signal, for selectively conducting the second supply voltage to the output terminal; wherein the first supply voltage is not less than the reference voltage.

Abstract: A sawtooth voltage generator has a first capacitor that is charged with a variable feedback control current to provide a sawtooth output signal with a controlled amplitude. A feedback loop includes a comparator that compares a version of the sawtooth output signal with a fixed voltage reference to provide a comparator output signal to a phase frequency comparator, the output of which controls a source of the variable feedback control current. A method includes controlling the amplitude of a sawtooth output signal by charging a capacitor in a sawtooth voltage generator with a variable feedback control current; comparing a version of the sawtooth output signal with a fixed reference voltage to provide a comparator output signal; processing the comparator output signal in a phase frequency comparator to provide up/down control signals; and controlling the variable feedback control current with the up/down control signals from the phase frequency comparator.

Abstract: Apparatus, systems, and methods are disclosed that operate to trigger a reference voltage generator from a supply voltage detector, compare an output voltage level from the reference voltage generator with the a supply voltage, and to generate an enable signal when the supply voltage is greater than the output voltage level. Additional apparatus, systems, and methods are disclosed.

Abstract: A data signal is generated in a pattern generation logic built in a TX port and given to a serializer, and a path is provided for looping an output of the serializer back to a deserializer and a CDR circuit of an RX port, whereby a BIST configuration enabling jitter measurement inside a high-speed serial transmission input/output section is adopted.

Abstract: The present invention discloses a de-jittering method for a clock signal, which is implemented by adopting a controllable frequency divider and includes: taking the clock signal to be de-jittered as a reference signal, and comparing a feedback clock signal outputted by the controllable frequency divider with the reference signal; generating the control signal that is then transmitted to the controllable frequency divider; the controllable frequency divider performs frequency division upon the input high-frequency signal to generate a stable clock, and the stable clock is outputted as the feedback clock signal which has been de-jittered. The present invention also discloses a de-jittering apparatus for implementing the above-mentioned method, which includes: a circuit for generating a control signal and a controllable frequency divider. By applying the present invention, the de-jittering circuit for clock signal can be simple.

Abstract: A PLL circuit has an averaging device for averaging a rectangular wave signal output from a phase comparator at every period of a reference clock signal, and for outputting the average value. After the establishment of the phase synchronization of the PLL circuit, the average value of the averaging device becomes a stationary reference level. Accordingly, the output clock signal generated by a voltage controlled oscillator can reduce its output frequency fluctuations in accordance with the reference level.

Abstract: A PLL and DLL are designed such that the power consumption can be reduced, the size can be easily reduced, the band of the locked loop can be a higher one, and the reliability can be improved. There are provided a phase comparator for measuring a feedback signal in synchronism with an input signal and outputting a phase signal representing the lead or lag of the phase of the feedback signal, a counter for increasing the number of bits representing “H” in a control signal when the phase signal represents the lead or decreasing the number of bits representing “H” in the control signal when the phase signal represents the lag, and a ring oscillator for increasing the oscillation period when the number of bits representing “H” increases or decreasing the oscillation period when the number of bits representing “H” decreases.

Abstract: A DLL circuit includes a buffer control unit configured to detect whether or not a DLL power supply exceeds a reference level and output a buffer control signal. A clock buffer buffers an external clock to generate an internal clock when the buffer control signal is enabled.

Abstract: This invention offers a charge pump circuit that solves problems of deterioration of a device (a capacitive device or a charge transfer device) composing the charge pump circuit caused by leftover charges and malfunctioning due to the leftover charges. N-channel type charge transfer MOS transistors T0-TM, each of which has a gate and a drain connected together, are connected in series between an input terminal IN and an output terminal OUT. A terminal of each of capacitive devices C1-CM is connected to each of connecting nodes A-X between the charge transfer MOS transistors, respectively. Each of the nodes A-X is connected with a voltage reduction circuit through each of N-channel type MOS transistors N1-NM, each of which has a gate and a drain connected together. That is, the charge pump circuit has paths to release the leftover charges actively from the nodes A-X to outside when a boosting operation of the charge pump circuit is terminated.

Abstract: A digital pulse-width control apparatus including an input module, a digital delay locked loop, a plurality of programmable delay circuits connected in series, and a pulse-width modulation module is provided. The present invention uses the input module to vary a clock signal to reduce the limitation of a duty cycle of the clock signal to the digital pulse-width control apparatus.

Abstract: A digital delay locked loop including a plurality of controllable delay circuits connected in series, a phase detecting unit, and a delay control unit is disclosed. As an output end of each of the controllable delay circuits is coupled to the phase detecting unit, the phase detecting unit samples a positive received signal at the transition points of a specific period signal transmitted by each of the controllable delay circuits.

Abstract: A delay locked loop circuit for a semiconductor memory apparatus includes a duty cycle correcting part that corrects and outputs duty cycles of internal clocks. A clock pulse width detecting part detects a pulse width of an external clock and outputs a pulse width detecting signal. A driving part divides a phase of the output of the duty cycle correcting part, adjusts a pulse width of at least one of two signals, which are obtained by dividing the phase, in accordance with the pulse width detecting signal, and outputs the two signals as delay locked loop clocks.

Abstract: A delay compensation circuit for a delay locked loop which includes a main delay line having a fine delay line comprising fine delay elements and a coarse delay line comprising coarse delay elements, the main delay line being controlled by a controller, the delay compensation circuit comprising: an adjustable fine delay for modeling a coarse delay element, a counter for controlling the adjustable fine delay to a value which is substantially the same as that of a coarse delay element, a circuit for applying a representation of the system clock to the delay compensation circuit, and a circuit for applying the fine delay count from the counter to the controller for adjusting the fine delay line of the main delay line to a value which is substantially the same as that of a coarse delay element of the main delay line.

Abstract: A slew-rate adjusting apparatus for use in a semiconductor memory device includes: a slew-rate modulation signal generator for generating a slew-rate modulation signal according to the number of control codes having a first logic level among a plurality of control codes, which are programmable at an exterior; and a pre-driver for adjusting a slew rate of a data signal by changing the number of switching elements turned on in response to the slew-rate modulation signal.

Abstract: Embodiments of a signal generating circuit are generally described herein. Other embodiments may be described and claimed.

Abstract: In accordance with some embodiments, a pulse width modulator having a comparator with an applied adjustable waveform to generate a bit stream with a controllably adjustable duty cycle is provided.

Abstract: The present invention discloses a level shift circuit and a control pulse shaping unit therewith. A level shift circuit for transition of a low-voltage input signal into a high-voltage output signal, the circuit comprising two pairs of transistors and a control unit. Two pairs of transistors, wherein the transistors in one of the pairs are both turned on in response to the input signal so that a voltage on a reference voltage node is coupled to a gate of one of the transistors in the other pair; a control unit decoupling a reference voltage from the reference voltage node during a first phase, and partially and fully coupling the reference voltage to the reference voltage node respectively during a second and third phases.

Abstract: A clock input/output device has three-state inverters Iv1 to Iv3 and an inverter Iv4, which cooperate to make equal the on-state resistance through a supply-voltage-side (VDD-side) transistor and the on-state resistance through a ground-voltage-side (0-side) transistor so as to make equal to VDD/2 the threshold voltage with reference to which the clock input/output device evaluates the input thereto to determine whether or not to change the state of the output thereof.

Abstract: Various systems and methods for comparing signals are disclosed herein. For example, some embodiments of the present invention provide comparator circuits with a preamplifier circuit, a latch circuit and a current re-use circuit. The current re-use circuit applies a current to the preamplifier circuit during a transparent phase, and applies a similar current to the latch circuit during a latch phase.

Abstract: In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value has been selected using a selection signal S0, a first node N1 is L and a second node N2 of a second dynamic circuit 1B is H, so that an output signal Q has an H level. In this case, when none of a plurality of pieces of data D0 to D2 is selected using selection signals S0 to S2, the first node N1 is H, so that the electric charge of the second node N2 is discharged and the output signal Q erroneously has an L level. However, in this case, an output node N3 is H and a fourth node N4 is L, so that an n-type transistor Tr6 of the second dynamic circuit 1B is turned OFF, thereby preventing the second node N2 from being discharged. Therefore, a normal operation is performed while securing a satisfactorily high-speed operation even when none of the pieces of data is selected.

Abstract: A programmable delay circuit including a first inverter, a second inverter, a variable resistance unit, and a variable capacitance unit is provided. The first inverter receives a positive-phase received signal, and transmits an anti-phase output signal through an anti-phase output signal line. The second inverter receives an anti-phase received signal, and transmits a positive-phase output signal through a positive-phase output signal line. The variable resistance unit regulates an equivalent resistance between the anti-phase output signal line and the positive-phase output signal line according to M bits in a delay-controlled code. The variable capacitance unit regulates an equivalent capacitance between the anti-phase output signal line and the positive-phase output signal line according to N bits in the delay-controlled code.

Abstract: A clock signal generator including: a signal generation unit that outputs a first clock signal composed of a single frequency component; and a phase angle detection unit that detects phase angles of the first clock signal by comparing a plurality of threshold values set within the amplitude of the first clock signal with instantaneous values of the first clock signal by using window comparators, and generates a second clock signal by determining rising and/or falling edges of the signal according to the detected phase angles.

Abstract: A circuit, method, and system are disclosed. In one embodiment the circuit comprises a ring oscillator circuit having a plurality of delay elements, the ring oscillator circuit to generate a clock signal frequency, a checker circuit to compare a count of clock signal oscillations observed per complete loop of the ring oscillator circuit to a reference count, and to set a flag signal if the clock signal oscillation count is above a high threshold amount or below a low threshold amount.

Abstract: A clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.

Abstract: In one embodiment, an apparatus comprises a circuit supplied by a first supply voltage during use, the circuit having at least a first input signal; and a level shifter supplied by the first supply voltage during use and coupled to provide the first input signal to the circuit. The level shifter is coupled to receive a second input signal sourced from circuitry supplied by a second supply voltage during use, and is configured to generate the first input signal by level shifting the second input signal. Coupled to receive a power control signal indicating, when asserted, that the second supply voltage is to be powered down, the level shifter is configured to assert a predetermined level on the first input signal independent of the second input signal and responsive to an assertion of the power control signal.

Abstract: This invention discloses a voltage level shifter, which comprises a first P-type metal-oxide-semiconductor (PMOS) transistor having a gate, a source and a bulk coupled to an input terminal, a first positive voltage power supply and a second positive voltage power supply, respectively, and a second PMOS transistor having a source, a drain and a bulk coupled to a third positive voltage power supply, an output node and the second positive voltage power supply, respectively, wherein the first and second PMOS transistors are formed in a single Nwell.

Abstract: The present invention provides for a system comprising a level shifter configured to receive a first clock signal from a first power domain, to receive a counter signal, to select one of a plurality of intermediate voltages in response to the received counter signal, and to generate a second clock signal in response to the received first clock signal and the selected intermediate voltage. A counter is coupled to the level shifter and configured to receive a divided clock signal and a comparison result signal, and to generate the counter signal in response to the received divided clock signal and comparison result signal. A divider is coupled to the counter and configured to receive the first clock signal and to generate the divided clock signal in response to the received first clock signal. A filter is coupled to the level shifter and configured to receive the second clock signal and to generate a first comparison signal in response to the received second clock signal.

Abstract: An internal power voltage trimming circuit and its method individually or simultaneously perform level trimming for a plurality of power voltages in a semiconductor memory device. The internal power voltage trimming circuit includes a trimming control signal generator for generating a trimming selection signal and a trimming enable signal by using an inputted address signal, and an internal power voltage level controller for controlling the levels of the internal power voltages by using the trimming selection signal that is outputted under control of the trimming enable signal.

Abstract: A bidirectional switch comprises a first FET, a second FET, and a switch controller for controlling a conductive state in which current from a bidirectional power supply electrically connected to drain terminals bidirectionally flows, and a nonconductive state in which the current does not flow. In the conductive state, the switch controller applies, to gate terminals of the first FET and the second FET, a voltage higher than a threshold voltage with reference to a potential at a node to which source terminals of the first FET and the second FET are connected. In the nonconductive state, the switch controller causes the bidirectional power supply and each gate terminal to be electrically insulated from each other, and applies a voltage lower than or equal to the threshold voltage with reference to the potential at the node.

Abstract: The invention relates to techniques for programming trimming circuitry of a power integrated circuit without the need for separate programming pins. We describe a power supply controller IC with internal circuitry, a plurality of external connections, the IC further comprising trimming circuitry with no external connections to said IC other than via shared ones of said external connections. The shared external connections comprise a first connection comprising a data input for receiving data for programming said trimming circuitry, and a second, different connection comprising a select input to select between a data receiving mode for receiving data from said data input and a programming mode for programming said trimming circuitry using said received data.

Abstract: The present invention is directed to realize high manufacture yield and compensate variations in threshold voltage of a MOS transistor with small overhead. A semiconductor integrated circuit includes a CMOS circuit for processing an input signal in an active mode, a control switch, and a control memory. The control switch supplies a pMOS body bias voltage and an nMOS body bias voltage to an N well in a pMOS transistor and a P well in an nMOS transistor, respectively, in the CMOS circuit. The control memory stores control information indicating whether or not the pMOS body bias voltage and the nMOS body bias voltage are supplied from the control switch to the N well in the pMOS transistor and the P well in the nMOS transistor, respectively, in the CMOS circuit in the active mode.

Abstract: Dual edge modulated charge pumping circuit has an output terminal, a charge pumping conversion circuit, and a dual edge modulated control circuit. The charge pumping conversion circuit has a first capacitor, a second capacitor, and a switch combination circuit. The second capacitor is coupled between the output terminal and a ground potential. The dual edge modulated control circuit controls the switch combination circuit such that the charge pumping conversion circuit operates with a first phase, a second phase, a third phase, and a fourth phase. During the first phase, a first electrode of the first capacitor is floated. During the second phase, the first capacitor is coupled between the ground potential and an input voltage. During the third phase, the first capacitor is coupled between the input voltage and the output terminal. During the fourth phase, the first electrode of the first capacitor is floated.

Abstract: It is an object to provide a DC/DC converter that can stabilize power supply potential in use. It is another object to provide a semiconductor device in which circuit operation is stabilized. In addition to a power supply that supplies potential to be reference potential of boosting in a DC/DC converter, a power supply for charging a capacitor in the DC/DC converter is provided. Accordingly, loads to the power supply that supplies the reference potential of boosting can be reduced. Further, as power for charging the capacitor in the DC/DC converter, power supplied from not an antenna but a secondary battery is used. More specifically, a secondary battery is used as a power supply that supplies power to a buffer circuit or an inverter circuit. Thus, power supplied from the antenna can be stabilized. In other words, operation of a logic circuit and an analog circuit can be stabilized.

Abstract: An exemplary method for reducing leakage current of thin film transistors (TFTs) of a TFT array substrate (200) includes: providing a TFT array substrate, the TFT array substrate including a number of gate lines, a number of data lines, and a number of TFTs, each TFT including a gate electrode, a source electrode and a drain electrode, the gate electrodes being connecting to the gate lines, the source electrodes being connecting to the data lines; providing a same direct current voltage to the source electrodes and the drain electrodes; and providing another direct current voltage to the gate electrodes to turn off the TFTs, and continuing to provide said same direct current voltage to the source electrodes for a predetermined time.

Abstract: An integrated circuit includes a circuit for adjusting a voltage drop. The circuit includes a reference voltage node, an output node and a driver circuit coupled between the reference voltage node and the output node. The driver circuit includes an impedance causing a current flow through the driver circuit when a reference voltage is applied to the reference voltage node. A current source is coupled to the driver circuit to impress an adjustment current based on a control current such that the current flow through the driver circuit is adjusted to yield a desired voltage drop across the driver circuit.