Patents Issued in June 24, 2008
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Patent number: 7390706Abstract: A method of forming a high quality channel region of a TFT by forming a large size monocrystalline silicon thin film using a patterned metal mask and a grain boundary filtering region is provided. The method includes sequentially stacking a first buffer layer and an amorphous silicon layer on a substrate, forming a first silicon region in which crystallization begins, a second silicon region having a width smaller than a width of the first silicon region and located on a central portion of a side of the first silicon region, and a third silicon region having a width than greater the width of the second silicon region and contacting the second silicon region, forming a metal mask partly on the first silicon region, and crystallizing the amorphous silicon layer by cooling the amorphous silicon layer after melting the entire amorphous silicon layer except for a portion of the amorphous silicon layer under the metal mask by radiating laser beams to the patterned amorphous silicon layer.Type: GrantFiled: November 30, 2005Date of Patent: June 24, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Hans S. Cho, Takashi Noguchi, Do-young Kim
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Patent number: 7390707Abstract: The semiconductor device fabrication method comprising the step of forming a gate electrode on a semiconductor substrate; the step of forming a source/drain diffused layer in the semiconductor substrate on both sides of the gate electrode; the step of burying a silicon germanium layer in the source/drain diffused layer; the step of forming an amorphous layer at an upper part of the silicon germanium layer; the step of forming a nickel film on the amorphous layer; and the step of making thermal processing to react the nickel film and the amorphous layer with each other to form a silicide film on the silicon germanium layer.Type: GrantFiled: September 8, 2005Date of Patent: June 24, 2008Assignee: Fujitsu LimitedInventors: Kazuo Kawamura, Yosuke Shimamune
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Patent number: 7390708Abstract: A method is provided for the patterning of a stack comprising elements that do not form volatile compounds during conventional reactive ion etching. More specifically the element(s) are Lanthanide elements such as Ytterbium (Yb) and the patterning preferably relates to the dry etching of silicon and/or germanium comprising structures (e.g. gates) doped with a Lanthanide e.g. Ytterbium (Yb doped gates). In case the silicon and/or germanium comprising structure is a gate electrode the silicon and/or germanium is doped with a Lanthanide (e.g. Yb) for modeling the work function of a gate electrode.Type: GrantFiled: October 22, 2007Date of Patent: June 24, 2008Assignee: Interuniversitair Microelektronica Centrum (IMEC) vzwInventors: Marc Demand, Denis Shamiryan, Vasile Paraschiv
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Patent number: 7390709Abstract: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, a trench within the first dielectric layer, and a second dielectric layer on the substrate. The second dielectric layer has a first part that is formed in the trench and a second part. After a first metal layer with a first workfunction is formed on the first and second parts of the second dielectric layer, part of the first metal layer is converted into a second metal layer with a second workfunction.Type: GrantFiled: September 8, 2004Date of Patent: June 24, 2008Assignee: Intel CorporationInventors: Mark L. Doczy, Justin K. Brask, Jack Kavalieros, Uday Shah, Matthew V. Metz, Suman Datta, Ramune Nagisetty, Robert S. Chau
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Patent number: 7390710Abstract: Layers of epitaxial silicon are used to protect the tunnel dielectric layer of a floating-gate memory cell from excessive oxidation or removal during the formation of shallow trench isolation (STI) regions. Following trench formation, the layers of epitaxial silicon are grown from silicon-containing layers on opposing sides of the tunnel dielectric layer, thereby permitting their thickness to be limited to approximately one-half of the thickness of the tunnel dielectric layer. The epitaxial silicon may be oxidized prior to filling the trench with a dielectric material or a dielectric fill may occur prior to oxidizing at least the epitaxial silicon covering the ends of the tunnel dielectric layer.Type: GrantFiled: September 2, 2004Date of Patent: June 24, 2008Assignee: Micron Technology, Inc.Inventors: Garo Derderian, Nirmal Ramaswamy
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Patent number: 7390711Abstract: A MOS transistor including a gate insulation layer and a gate electrode layer on a channel region of a semiconductor substrate. A gate spacer layer is formed on a sidewall of the electrode layer and the insulation layer. The transistor includes a deep extended source/drain region, a first source/drain region that is deeper than the extended source/drain region, and a second source/drain region that is shallower than the extended source/drain region.Type: GrantFiled: December 15, 2005Date of Patent: June 24, 2008Assignee: Dongbu Electronics Co., Ltd.Inventor: Dong-Il Byun
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Patent number: 7390712Abstract: Systems, devices, structures, and methods are described that inhibit dielectric degradation at high temperatures. An enhanced capacitor is discussed. The enhanced capacitor includes a first electrode, a dielectric that includes ditantalum pentaoxide, and a second electrode having a compound. The compound includes a first substance and a second substance. The second electrode includes a trace amount of the first substance. The morphology of the semiconductor structure remains stable when the trace amount of the first substance is oxidized during crystallization of the dielectric. In one embodiment, the crystalline structure of the dielectric describes substantially a (001) lattice plane.Type: GrantFiled: April 30, 2007Date of Patent: June 24, 2008Assignee: Micron Technology, Inc.Inventors: Cem Basceri, Vishnu K. Agarwal, Dan Gealy
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Patent number: 7390713Abstract: One embodiment of the invention relates to a method for forming trench memory cell structures having trench capacitors and planar selection transistors. An implantation for forming a reinforcement implant for improving the electrical connection of a storage electrode of a trench capacitor to a first source/drain zone of the respective selection transistor is effected in a self-aligned manner with respect to gate stacks provided above a substrate surface of the semiconductor substrate. In order to form the reinforcement implant, the deposition process for a first insulator layer, from which dielectric spacer structures of the gate stacks emerge, is divided into at least two substeps, the implantation being preceded by application of a base layer of the first insulator layer, the layer thickness of which defines the distance between the reinforcement implant and the gate stacks.Type: GrantFiled: June 14, 2005Date of Patent: June 24, 2008Assignee: Infineon Technologies AGInventor: Anke Krasemann
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Patent number: 7390714Abstract: Disclosed herein is a method of manufacturing semiconductor devices. The method includes the steps of forming a gate oxide film, a polysilicon film and a nitride film on a semiconductor substrate, and patterning the gate oxide film, the polysilicon film and the nitride film to form poly gates, forming a spacer at the side of the poly gate, forming a sacrifice nitride film on the entire surface, and then forming an interlayer insulation film on the entire surface, polishing the sacrifice nitride film formed on the interlayer insulation film and the poly gates so that the nitride film is exposed, removing top portions of the sacrifice nitride film while removing the nitride film, forming an insulation film spacer at the side exposed through removal of the nitride film, and filling a portion from which the sacrifice oxide film is removed with an insulation film, and forming the tungsten gates in portions from which the nitride films are moved.Type: GrantFiled: December 6, 2005Date of Patent: June 24, 2008Assignee: Hynix Semiconductor Inc.Inventors: Cheol Mo Jeong, Whee Won Cho, Jung Geun Kim
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Patent number: 7390715Abstract: A method of fabricating an active layer thin film by a metal-chalcogenide precursor solution is provided, including the steps of: synthesizing a metal-chalcogenide precursor containing benzyl or benzyl derivative; dissolving the precursor in a solvent to produce a precursor solution, wherein a chalcogen element or compound can be added to the precursor solution to adjust the molar ratio of metal ion to chalcogen; and then applying the precursor solution onto a substrate in a specific coating manner, to form a film of the metal-chalcogenide after a curing process. Thereby, the existing method wherein an amorphous silicon active layer film is fabricated by plasma enhanced chemical vapor deposition (PECVD) is replaced.Type: GrantFiled: June 5, 2006Date of Patent: June 24, 2008Assignees: Taiwan TFT LCD Association, Chunghwa Picture Tubes, Ltd., Au Optronics Corp., Quanta Display Inc., Hannstar Display Corp., Chi Mei Optoelectronics Corp., Industrial Technology Research Institute, Toppoly Optoelectronics Corp.Inventors: Chun-Yao Ou, Hua-Chi Cheng, Ming-Nan Hsiao, Bor-Chuan Chuang, Chao-Jen Wang
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Patent number: 7390716Abstract: A method of manufacturing a flash memory device. An etch process for controlling the effective field height of isolation layers is performed using a dry etch process on condition that an excessive amount of polymer is generated, thus forming first spacers on sidewalls of a floating gate pattern. The first spacers serve as an etch barrier layer when the isolation layers of regions exposed when a control gate and a floating gate are formed subsequently are etched, so that a second spacer is formed on sidewalls of the semiconductor substrate of an active region. Accordingly, exposure and damage of the sidewalls of the semiconductor substrate can be prevented and the reliability of devices can be improved.Type: GrantFiled: October 18, 2006Date of Patent: June 24, 2008Assignee: Hynix Semiconductor Inc.Inventor: In No Lee
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Patent number: 7390717Abstract: A fabrication process for a trench type power semiconductor device includes forming inside spacers over a semiconductor surface. Using the spacers as masks, trenches with gates are formed in the semiconductor body. After removing the spacers, source implants are formed in the semiconductor body along the trench edges and are then driven. Insulation caps are then formed over the trenches. Outside spacers are next formed along the sides of the caps. Using these spacers as masks, the semiconductor surface is etched and high conductivity contact regions formed. The outside spacers are then removed and source and drain contacts formed. Alternatively, the source implants are not driven. Rather, prior to outside spacer formation a second source implant is performed. The outside spacers are then formed, portions of the second source implant etched, any remaining source implant driven, and the contact regions formed. The gate electrodes are either recessed below or extend above the semiconductor surface.Type: GrantFiled: February 9, 2005Date of Patent: June 24, 2008Assignee: International Rectifier CorporationInventors: Jianjun Cao, Paul Harvey, David Kent, Robert Montgomery, Kyle Spring
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Patent number: 7390718Abstract: An embedded semiconductor memory is fabricated by: forming diffusion bit line regions in a semiconductor substrate; then thermally oxidizing the upper surface of the substrate, thereby forming a bottom oxide layer over the substrate and simultaneously forming bit line oxide regions over each of the diffusion bit line regions; and then forming an intermediate dielectric layer (e.g., silicon nitride), over the bottom oxide layer and the bit line oxide regions. CMOS well implants are then performed in a CMOS section of the device through the silicon nitride layer and bottom oxide layer. The silicon nitride layer and bottom oxide layer are then removed in the CMOS section, and a top dielectric layer, such as a high-temperature oxide or a high-k dielectric, is deposited. The top dielectric layer completes a memory stack of the memory device, and forms a gate dielectric layer of a high voltage transistor in the CMOS section.Type: GrantFiled: February 20, 2004Date of Patent: June 24, 2008Assignee: Tower Semiconductor Ltd.Inventors: Yakov Roizin, Zmira Shterenfeld-Lavie, Itzhak Edrei
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Patent number: 7390719Abstract: A semiconductor device having a dual gate is formed on a substrate having a dielectric layer. A first metallic conductive layer is formed on the dielectric layer to a first thickness, and annealed to have a reduced etching rate. A second metallic conductive layer is formed on the first metallic conductive layer to a second thickness that is greater than the first thickness. A portion of the second metallic conductive layer formed in a second area of the substrate is removed using an etching selectivity. A first gate structure having a first metallic gate including the first and the second metallic conductive layers is formed in a first area of the substrate. A second gate structure having a second metallic gate is formed in the second area. A gate dielectric layer is not exposed to an etching chemical due to the first metallic conductive layer, so its dielectric characteristics are not degraded.Type: GrantFiled: August 1, 2006Date of Patent: June 24, 2008Assignee: Samsung Electronics, Co., Ltd.Inventors: Taek-Soo Jeon, Yu-Gyun Shin, Sang-Bom Kang, Hag-Ju Cho, Hye-Lan Lee, Sang-Yong Kim
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Patent number: 7390720Abstract: A bipolar transistor structure includes an intrinsic base layer formed over a collector layer, an emitter formed over the intrinsic base layer, and an extrinsic base layer formed over the intrinsic layer and adjacent the emitter. A ring shaped collector implant structure is formed within an upper portion of the collector layer, wherein the ring shaped collector implant structure is disposed so as to be aligned beneath a perimeter portion of the emitter.Type: GrantFiled: October 5, 2006Date of Patent: June 24, 2008Assignee: International Business Machines CorporationInventor: Francois Pagette
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Patent number: 7390721Abstract: Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.Type: GrantFiled: September 21, 2005Date of Patent: June 24, 2008Assignee: International Business Machines CorporationInventors: Peter J. Geiss, Marwan H. Khater, Qizhi Liu, Randy W. Mann, Robert J. Purtell, BethAnn Rainey, Jae-Sung Rieh, Andreas D. Stricker
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Patent number: 7390722Abstract: An oxidation process is used to produce a positional reference structure on a semiconductor wafer. A photolithographic mask layer used to define the positional reference structure can be combined with a photolithographic mask layer used to define an active device layer on the wafer, whereby both patterns can be printed in a single photolithographic operation. The same oxidation process used to produce an isolating oxide between active device regions of the active device layer can also be used to produce the positional reference structure.Type: GrantFiled: August 18, 2004Date of Patent: June 24, 2008Assignee: National Semiconductor CorporationInventor: Richard Wendell Foote, Jr.
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Patent number: 7390723Abstract: A method for stacking and bonding wafers in precision alignment by detecting alignment marks provided on wafer edges, comprising the steps of: (a) providing at least a first wafer having at least a first pattern and at least a second pattern disposed on the cross-section thereof, at least a second wafer having at least a third pattern and at least a fourth pattern disposed on the cross-section thereof, and at least a sensing device, while pairing the first pattern with the third pattern and pairing the second pattern with the fourth pattern; (b) actuating the first wafer and the second wafer for enabling the first to parallel the second wafer and to be a distance apart from the second wafer; (c) actuating the first wafer and the second wafer for bringing the two wafers to move toward each other while enabling the sensing device for detecting and determining whether or not the first pattern is in a position capable of matching with the third pattern and the second pattern in another position capable of matchinType: GrantFiled: May 27, 2005Date of Patent: June 24, 2008Assignee: Industrial Technology Research InstituteInventor: Chiu-Wang Chen
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Patent number: 7390724Abstract: A system for manufacturing multilayered substrates. The system has a support member is adapted to process a film of material comprising a first side and a second side from a first state to a second state. The support member is attached to the first side of the film of material. The second state comprises a stressed state. The system has a handle substrate comprising a face, which is adapted to be attached to the second side of the film of material. The support member is capable of being detached from the first side of the film of material thereby leaving the handle substrate comprising the film of material in the second state being attached to the face of the handle substrate.Type: GrantFiled: April 11, 2005Date of Patent: June 24, 2008Assignee: Silicon Genesis CorporationInventors: Francois J. Henley, Philip James Ong, Igor J. Malik
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Patent number: 7390725Abstract: Transistors fabricated on SSOI (Strained Silicon On Insulator) substrate, which comprises a strained silicon layer disposed directly on an insulator layer, have enhanced device performance due to the strain-induced band modification of the strained silicon device channel and the limited silicon volume because of the insulator layer. The present invention discloses SSOI substrate fabrication processes comprising various novel approaches. One is the use of a thin relaxed SiGe layer as the strain-induced seed layer to facilitate integration and reduce processing cost. Another is the formation of split implant microcracks deep in the silicon substrate to reduce the number of threading dislocations reaching the strained silicon layer. And lastly is a two step annealing/thinning process for the strained silicon/SiGe multilayer film transfer without blister or flaking formation.Type: GrantFiled: November 21, 2005Date of Patent: June 24, 2008Assignee: Sharp Laboratories of America, Inc.Inventors: Jer-shen Maa, Jong-Jan Lee, Douglas J. Tweet, David R. Evans, Allen W. Burmaster, Sheng Teng Hsu
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Patent number: 7390726Abstract: A metal-to-metal antifuse is disposed between two metal interconnect layers in an integrated circuit. An insulating layer is disposed above a lower metal interconnect layer. The insulating layer includes a via formed therethrough containing a tungsten plug in electrical contact with the lower metal interconnect layer. An antifuse material layer comprising amorphous carbon is disposed above the upper surface of the tungsten plug. The antifuse material layer is disposed between adhesion-promoting layers. A layer of a barrier metal, consisting of either tantalum or tantalum nitride, is disposed over the antifuse layer to form an upper electrode of the antifuse. An oxide or tungsten hard mask provides high etch selectivity and the possibility to etch barrier metals without affecting the dielectric constant value and mechanical properties of the antifuse.Type: GrantFiled: March 10, 2005Date of Patent: June 24, 2008Assignee: Actel CorporationInventors: A. Farid Issaq, Frank Hawley
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Patent number: 7390727Abstract: The present invention is related to a polycrystalline silicon film containing Ni which is formed by crystallizing an amorphous silicon layer containing nickel. The present invention includes a polycrystalline silicon film wherein the polycrystalline film contains Ni atoms of which density ranges from 2×1017 to 5×1019 atoms/cm3 in average and comprises a plurality of needle-shaped silicon crystallites. In another aspect, the present invention includes a polycrystalline silicon film wherein the polycrystalline film contains Ni atoms of which density ranges from 2×1017 to 5×1019 atoms/cm3, comprises a plurality of needle-shaped silicon crystallites and is formed on an insulating substrate. Such a polysilicon film according to the present invention avoids metal contamination usually generated in a conventional method of metal induced crystallization.Type: GrantFiled: July 24, 2006Date of Patent: June 24, 2008Assignees: LG Display Co., Ltd.Inventors: Jin Jang, Seong-Jin Park
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Patent number: 7390728Abstract: The present invention is to reduce display unevenness in a display device caused by dispersion of energy density of a laser beam. It is difficult for a periodical pattern to be recognized as display unevenness in display image. The display device of the present invention can visually reduce the display unevenness in the display image by utilizing the visual advantage described above. The display device can be manufactured using a TFT array substrate in which electric characteristic of plural TFTs arranged in a line in the minor axis direction of an linear shaped laser beam periodically fluctuates depending on the place in which each TFT is formed.Type: GrantFiled: December 24, 2003Date of Patent: June 24, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Masaki Koyama
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Patent number: 7390729Abstract: A method of fabricating semiconductor device is provided. A transistor is formed on a substrate, and a metal silicide layer is formed on the surface of a gate conductor layer and a source/drain region. Next, a surface treatment process is performed to selectively form a protection layer on the surface of the metal silicide layer. Then, a spacer of the transistor is partially removed using the protection layer as a mask, so as to reduce the width of the spacer. Then, a stress layer is formed on the substrate.Type: GrantFiled: September 21, 2006Date of Patent: June 24, 2008Assignee: United Microelectronics Corp.Inventors: Chao-Ching Hsieh, Chun-Chieh Chang, Tzung-Yu Hung
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Patent number: 7390730Abstract: A semiconductor structure having a body capacitance plate, which is formed with a process that assures that the body capacitance plate is self-aligned to both the source line (SL) diffusion and the bitline diffusion is provided. Thus the amount of overlap between the SL and the bitline diffusions and the body capacitance plate is precisely controlled. More specifically, the present invention forms the structure of a 1T-capacitorless SOI body charge storage cell having sidewall capacitor plates using a process that assures that there is 1) minimal overlap between plate and source/drain diffusions, and 2) that the minimal overlap obtained in the present invention is precisely controlled and is not subject to alignment tolerances. The inventive cell results in larger signal margin, improved performance, smaller chip size, and reduced dynamic power dissipation relative to the prior art.Type: GrantFiled: April 30, 2007Date of Patent: June 24, 2008Assignee: International Business Machines CorporationInventors: Jack A. Mandelman, Louis C. Hsu, Rajiv V. Joshi
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Patent number: 7390731Abstract: The process according to the invention makes it possible to deposit a transparent conductive oxide film on a toughened glass substrate placed inside a chamber. It consists in providing sources containing an oxygen-based liquid compound, a liquid compound of the metal intended to form the oxide, and a dopant in gaseous or liquid form, respectively; establishing a temperature between 130 and 300° C. and a pressure between 0.01 and 2 mbar in the chamber; and then bringing said sources into communication with the chamber, which has the effect of vaporizing the liquids at their surface, of drawing them up into the chamber without having to use a carrier gas, and of making them react therein with the dopant so that the oxide layer is formed on the substrate.Type: GrantFiled: August 23, 2002Date of Patent: June 24, 2008Assignee: Universite de Neuchatel, Institut de MicrotechniqueInventors: Ulrich Kroll, Johannes Meier
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Patent number: 7390732Abstract: A semiconductor device capable of facilitating high density mounting at low cost without causing any defective conduction at the time of connection to a substrate, a mounting structure thereof and a method of fabrication thereof, characterized in that pyramidal bump electrodes are bonded onto pad electrodes arranged on a semiconductor chip to form the semiconductor device.Type: GrantFiled: July 15, 1998Date of Patent: June 24, 2008Assignee: Hitachi, Ltd.Inventors: Takayoshi Watanabe, Hidetaka Shigi, Susumu Kasukabe, Terutaka Mori
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Patent number: 7390733Abstract: To enhance bonding accuracy of a bump electrode, while coping with narrowing pitch of the bump electrodes, a protruding electrode, whose leading end is sharpened, is provided to a semiconductor chip, and the protruding electrode is bonded to a lead electrode, while having a leading end of the protruding electrode bite into the lead electrode.Type: GrantFiled: May 26, 2004Date of Patent: June 24, 2008Assignee: Seiko Epson CorporationInventor: Munehide Saimen
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Patent number: 7390734Abstract: A thin film transistor (TFT) substrate includes a glass substrate, a thin film transistor, an electrode pad, and a conductive bump. The TFT and the electrode pad are formed on the glass substrate, and the electrode pad is used for electrically connecting with the thin film transistor. The conductive bump includes several insulating bumps and a conductive layer. The insulating bumps are formed on the electrode pad dividedly, and the conductive layer covers the top surfaces of the insulating bumps, the inward surfaces of the insulating bumps, and the electrode pad between the insulating bumps for electrically connecting with the electrode pad. The outward side surfaces of the insulating bumps are exposed out of the conductive layer.Type: GrantFiled: June 4, 2007Date of Patent: June 24, 2008Assignee: AU Optronics Corp.Inventors: Hui-Chang Chen, Chun-Yu Lee, Shih-Ping Chou
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Patent number: 7390735Abstract: A method of forming packages containing SiC or other semiconductor devices bonded to other components or conductive surfaces utilizing transient liquid phase (TLP) bonding to create high temperature melting point bonds using in situ formed ternary or quaternary mixtures of conductive metals and the devices created using TLP bonds of ternary or quaternary materials. The compositions meet the conflicting requirements of an interconnect or joint that can be exposed to high temperature, and is thermally and electrically conductive, void and creep resistant, corrosion resistant, and reliable upon temperature and power cycling.Type: GrantFiled: January 7, 2005Date of Patent: June 24, 2008Assignee: Teledyne Licensing, LLCInventor: Vivek Mehrotra
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Patent number: 7390736Abstract: A circuit element that may generate or be affected by noise or electromagnetic interference may be substantially surrounded by one or more encircling plugs. The encircling plug may be closed by an interconnection layer. The plug may be grounded to reduce the electromagnetic interference or noise generated by or coupled to said passive circuit element.Type: GrantFiled: September 10, 2004Date of Patent: June 24, 2008Assignee: Intel CorporationInventor: Harry Q. Pon
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Patent number: 7390737Abstract: A method in which a base layer is deposited in a contact hole region under a protective gas, where base layer contains a nitride as main constituent. After the deposition of the base layer, a covering layer is deposited under gaseous nitrogen. An adhesion promoting layer results which is simple to produce and has good electrical properties.Type: GrantFiled: March 17, 2003Date of Patent: June 24, 2008Assignee: Infineon Technologies AgInventors: Jürgen Förster, Klemens Prügl, Berthold Schuderer
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Patent number: 7390738Abstract: Techniques are disclosed for fabricating a device using a photolithographic process. The method includes providing a first anti-reflective coating over a surface of a substrate. A layer which is transparent to a wavelength of light used during the photolithographic process is provided over the first anti-reflective coating, and a photosensitive material is provided above the transparent layer. The photosensitive material is exposed to a source of radiation including the wavelength of light. Preferably, the first anti-reflective coating extends beneath substantially the entire transparent layer. The complex refractive index of the first anti-reflective coating can be selected to maximize the absorption at the first anti-reflective coating to reduce nothing of the photosensitive material.Type: GrantFiled: May 1, 2006Date of Patent: June 24, 2008Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Zhiping Yin
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Patent number: 7390739Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case (particularly in the latter), capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, such as silane-based SAMs, can be used to form the masking layer. The capping layer can be formed of an electrically conductive material (e.g.Type: GrantFiled: May 18, 2005Date of Patent: June 24, 2008Inventors: David E. Lazovsky, Sandra G. Malhotra, Thomas R. Boussie
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Patent number: 7390740Abstract: Methods for forming vias are disclosed. The methods include providing a substrate having a first surface and an opposing, second surface. The vias are formed within the substrate to have a longitudinal axis sloped at an angle with respect to a reference line extending perpendicular to the first surface and the second surface of the substrate. The vias may be formed from the first surface to the opposing second surface, or the via may be formed as a first blind opening from the first surface, then a second opening may be formed from the second surface to be aligned with the first opening. Vias may be formed completely through a first substrate and a second substrate, and the substrates may be bonded together. Semiconductor devices including the vias of the present invention are also disclosed. A method of forming spring-like contacts is also disclosed.Type: GrantFiled: September 2, 2004Date of Patent: June 24, 2008Assignee: Micron Technology, Inc.Inventors: James M. Wark, Syed S. Ahmad
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Patent number: 7390741Abstract: A method for fabricating a semiconductor device comprises the steps of: forming interconnection grooves 38 in an inter-layer insulation film 34; forming an interconnection layer 44 of Cu as the main material in the interconnection grooves 38; and concurrently injecting nitrogen gas and water to the surface of the interconnection layer 44 buried in the interconnection groove 38.Type: GrantFiled: April 5, 2004Date of Patent: June 24, 2008Assignee: Fujitsu LimitedInventors: Yukio Takigawa, Tamotsu Yamamoto, Yoshiyuki Okura, Takahiro Kono, Tsutomu Hosoda
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Patent number: 7390742Abstract: The invention relates to a method for producing a rewiring printed circuit board with a substrate wafer having passage connections between a first and a second surface. One embodiment of the method comprises applying and patterning masking layers on the first and the second surfaces, thereby uncovering a first contact location on the first surface and a second contact location on the second surface; applying a protective layer to the second surface in order to protect the corresponding masking layer and the second contact location during subsequent method steps; applying a first conductor structure to the first surface, the first conductor structure on the first surface covering the first contact location; removing the protective layer on the second surface; and applying a second conductor structure to the second surface, the second conductor structure on the second surface covering the second contact location.Type: GrantFiled: October 14, 2005Date of Patent: June 24, 2008Assignee: Infineon Technologies AGInventors: Axel Brintzinger, Stefan Ruckmich, Octavio Trovarelli, Fritz Uhlendorf, legal representative, David Wallis, Ingo Uhlendorf
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Patent number: 7390743Abstract: A method for forming a structured tungsten layer and a method for forming a semiconductor device using the same. A first tungsten layer is formed with an atomic layer deposition (ALD) method. A second tungsten layer is formed on the first tungsten layer with a chemical vapor deposition (CVD) method. A third tungsten layer is formed on the second tungsten layer with the ALD method to complete the structured tungsten layer.Type: GrantFiled: November 21, 2005Date of Patent: June 24, 2008Assignee: Samsung Electronics Co., Ltd.Inventor: Yun-Chul Shin
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Patent number: 7390744Abstract: Polishing compositions and methods for removing conductive materials and barrier materials from a substrate surface are provided. Polishing compositions are provided for removing at least a barrier material from a substrate surface by a chemical mechanical polishing process or by an electrochemical mechanical polishing process. The polishing compositions used in barrier removal may further be used after a process for electrochemical mechanical planarization process of a conductive material. The polishing compositions and methods described herein improve the effective removal rate of materials from the substrate surface with a reduction in planarization type defects.Type: GrantFiled: May 16, 2005Date of Patent: June 24, 2008Assignee: Applied Materials, Inc.Inventors: Renhe Jia, Feng Q. Liu, Stan D. Tsai, Liang-Yuh Chen
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Patent number: 7390745Abstract: A method for producing predetermined shapes in a crystalline Si-containing material that have substantially uniform straight sides or edges and well-defined inside and outside corners is provided together with the structure that is formed utilizing the method of the present invention. The inventive method utilizes conventional photolithography and etching to transfer a pattern, i.e., shape, to a crystalline Si-containing material. Since conventional processing is used, the patterns have the inherent limitations of rounded corners. A selective etching process utilizing a solution of diluted ammonium hydroxide is used to eliminate the rounded corners providing a final shape that has substantially straight sides or edges and substantially rounded corners.Type: GrantFiled: September 23, 2005Date of Patent: June 24, 2008Assignee: International Business Machines CorporationInventors: Thomas W. Dyer, Kenneth T. Settlemyer, Jr., James J. Toomey, Haining Yang
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Patent number: 7390746Abstract: Pitch multiplication is performed using a two step process to deposit spacer material on mandrels. The precursors of the first step react minimally with the mandrels, forming a barrier layer against chemical reactions for the deposition process of the second step, which uses precursors more reactive with the mandrels. Where the mandrels are formed of amorphous carbon and the spacer material is silicon oxide, the silicon oxide is first deposited by a plasma enhanced deposition process and then by a thermal chemical vapor deposition process. Oxygen gas and plasma-enhanced tetraethylorthosilicate (TEOS) are used as reactants in the plasma enhanced process, while ozone and TEOS are used as reactants in the thermal chemical vapor deposition process. The oxygen gas is less reactive with the amorphous carbon than ozone, thereby minimizing deformation of the mandrels caused by oxidation of the amorphous carbon.Type: GrantFiled: August 25, 2005Date of Patent: June 24, 2008Assignee: Micron Technology, Inc.Inventors: Jingyi Bai, Gurtej S. Sandhu, Shuang Meng
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Patent number: 7390747Abstract: A nitride semiconductor substrate having a rugged surface being lapped by whetting granules to roughness between Rms5 nm and Rms200 nm, which has a function of reducing dislocations of a GaN, InGaN or AlGaN layer epitaxially grown on the lapped substrate by gathering dislocations in the epi-layer to boundaries of holes, pulling the dislocations to bottoms of the holes. Higher roughness of the nitride substrate degrades morphology of an epitaxially-grown layer thereon but reduces dislocation density to a lower level. Morphology of the epi-layer contradicts the dislocation density of the epi-layer. The nitride semiconductor substrate can reduce dislocation density and can be low cost and useful substrates.Type: GrantFiled: November 1, 2005Date of Patent: June 24, 2008Assignee: Sumitomo Electric Industries, Ltd.Inventors: Masato Irikura, Yasushi Mochida, Masahiro Nakayama
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Patent number: 7390748Abstract: A polishing inhibiting layer forming additive for a slurry, the slurry so formed, and a method of chemical mechanical polishing are disclosed. The polishing inhibiting layer is formed through application of the slurry to the surface being polished and is removable at a critical polishing pressure. The polishing inhibiting layer allows recessed or low pattern density locations to be protected until a critical polishing pressure is exceeded based on geometric and planarity considerations, rather than slurry or polishing pad considerations. With the additive, polishing rate is non-linear relative to polishing pressure in a recessed/less pattern dense location. In one embodiment, the additive has a chemical structure: [CH3(CH2)xN(R)]M, wherein M is selected from the group consisting of: Cl, Br and I, x equals an integer between 2 and 24, and the R includes three carbon-based functional groups, each having less than eight carbon atoms.Type: GrantFiled: August 5, 2004Date of Patent: June 24, 2008Assignee: International Business Machines CorporationInventor: Michael J. MacDonald
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Patent number: 7390749Abstract: A method for providing features in an etch layer with a memory region and a peripheral region is provided. A memory patterned mask is formed over a first sacrificial layer. A first set of sacrificial layer features is etched into the first sacrificial layer and a second sacrificial layer. Features of the first set of sacrificial layer features are filled with filler material. The first sacrificial layer is removed. The spaces are shrunk with a shrink sidewall deposition. A second set of sacrificial layer features is etched into the second sacrificial layer. The filler material and shrink sidewall deposition are removed. A peripheral patterned mask is formed over the memory region and peripheral region. The second sacrificial layer is etched through the peripheral patterned mask. The peripheral patterned mask is removed. Features are etched into the etch layer from the second sacrificial layer.Type: GrantFiled: November 9, 2006Date of Patent: June 24, 2008Assignee: Lam Research CorporationInventors: Ji Soo Kim, Sangheon Lee, Daehan Choi, S. M. Reza Sadjadi
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Patent number: 7390750Abstract: A method is provided which includes forming a hardmask feature adjacent to a patterned sacrificial structure of a semiconductor topography, selectively removing the patterned sacrificial structure to expose a lower layer and etching exposed portions of the lower layer in alignment with the hardmask feature. In some embodiments, forming the hardmask feature may include conformably depositing a hardmask material above the patterned sacrificial structure and lower layer as well as blanket etching the hardmask material such that upper surfaces of the patterned sacrificial structure and portions of the lower layer are exposed and portions of the hardmask material remain along sidewalls of the patterned sacrificial structure. The method may be applied to produce an exemplary semiconductor topography including a plurality of gate structures each having a width less than approximately 70 nm, wherein a variation of the widths among the plurality of gate structures is less than approximately 10%.Type: GrantFiled: March 23, 2005Date of Patent: June 24, 2008Assignee: Cypress Semiconductor Corp.Inventors: Krishnaswamy Ramkumar, Alain P. Blosse, James A. Hunter
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Patent number: 7390751Abstract: A dry etching method includes loading a wafer on a lower electrode having at least two cooling paths. Cooling fluids having different temperatures are supplied to each of the cooling paths of the lower electrode so that the multiple cooling paths are at different temperatures from one another. The wafer is etched during cooling.Type: GrantFiled: December 22, 2005Date of Patent: June 24, 2008Assignee: Dongbu Electronics Co., Ltd.Inventor: Sang-Kwon Kim
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Patent number: 7390752Abstract: The present invention relates to a self-aligning patterning method which can be used to manufacture a plurality of multi-layer thin film transistors on a substrate. The method comprises firstly forming a patterned mask 20 on the surface of a sacrificial layer 18 which is part of a multi-layer structure 10 which comprises the substrate 12, a conductive layer 14, an insulating layer 16 and the sacrificial layer 18. Unpatterned areas are then etched to remove the corresponding areas of the sacrificial layer, the insulating layer 16 and the conductive layer 14 thereby leaving voids. A layer of dielectric 22 is then deposited over the etched multi-layer structure to at least substantially fill the voids. The deposited dielectric is then etched in order to at least partially expose the sides of the remaining areas 28 of the sacrificial layer. Conductive material 30 is then deposited on the surface of the etched dielectric.Type: GrantFiled: October 20, 2005Date of Patent: June 24, 2008Assignee: Seiko Epson CorporationInventors: Shunpu Li, Thomas Kugler, Christopher Newsome, David Russell
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Patent number: 7390753Abstract: A novel, in-situ plasma treatment method for eliminating or reducing striations caused by standing waves in a photoresist mask, is disclosed. The method includes providing a photoresist mask on a BARC (bottom anti-reflective coating) layer that is deposited on a feature layer to be etched, etching the BARC layer and the underlying feature layer according to the pattern defined by the photoresist mask, and subjecting the photoresist mask to a typically argon or hydrogen bromide plasma before, after, or both before and after etching of the BARC layer prior to etching of the feature layer. Preferably, the photoresist mask is subjected to the plasma both before and after etching of the BARC layer.Type: GrantFiled: November 14, 2005Date of Patent: June 24, 2008Assignee: Taiwan Semiconductor Mfg. Co., Ltd.Inventors: Li-Te Lin, Yui Wang, Huan-Just Lin, Yuan-Hung Chiu, Hun-Jan Tao
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Patent number: 7390754Abstract: A method of stripping a remnant metal is disclosed. The remnant metal is formed on a transitional silicide of a silicon substrate. Firstly, a surface oxidation process is performed on the transitional silicide, so as to form a protective layer on the transitional silicide. Then, a HPM stripping process is performed on the silicon substrate in order to strip the remnant metal.Type: GrantFiled: July 20, 2006Date of Patent: June 24, 2008Assignee: United Microelectronics Corp.Inventors: Chun-Chieh Chang, Tzung-Yu Hung, Chao-Ching Hsieh, Yi-Wei Chen, Yu-Lan Chang
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Patent number: 7390755Abstract: The current invention provides methods for performing a cleaning process that provides greater cleaning efficiency with less damage to device structures. After etching and photoresist stripping, a first plasma clean is performed. The first plasma clean may comprise one or more steps. Following the first plasma clean, a first HO based clean is performed. The first HO based clean may be a de-ionized water rinse, a water vapor clean, or a plasma clean, where the plasma includes hydrogen and oxygen. Following the first HO based clean, a second plasma clean is performed, which may comprise one or more steps. A second HO based clean follows the second plasma clean, and may be a de-ionized water rinse, a water vapor clean, or a plasma clean, where the plasma includes hydrogen and oxygen. For plasma processes, an RF generated plasma, a microwave generated plasma, an inductively coupled plasma, or combination may be used.Type: GrantFiled: May 1, 2002Date of Patent: June 24, 2008Assignees: Novellus Systems, Inc., STMicroelectronics S.R.L.Inventors: David L. Chen, Yuh-Jia Su, Eddie Ka Ho Chiu, Maria Paola Pozzoli, Senzi Li, Giuseppe Colangelo, Simone Alba, Simona Petroni