Abstract: An integrated fluxgate-induction sensor is formed of a combined fluxgate sensor and induction sensor using a common core. The sensor may be in serial operation where it switches between a fluxgate mode for measuring static magnetic fields and an induction mode for measuring alternating magnetic fields. Additionally, the sensor may be used in an interleaved operation where the sensor operates from the fluxgate mode during the transition period where its core is changing from a high permeability state to a low permeability state or vice versa, while the sensor operates in the induction mode when the core is in its high permeability state. The resulting sensor provides for a compact magnetic sensor system capable of sensing magnetic fields which oscillate from zero frequency to 10 kHz and higher.

Abstract: A circuit for a fluxgate magnetometer includes a plurality of digital function blocks that are programmed as functions within a microcontroller. The microcontroller includes and implements the functions of an analog circuit to lower the cost and complexity of a digital fluxgate magnetometer circuit.

Abstract: A resonator apparatus and a method for electron spin resonance (ESR) measurements are disclosed. The resonator apparatus comprises a dielectric resonator and a sample vessel extending through the resonator. The sample vessel is configured as one single flexible tube. Means are provided for conveying a liquid sample substance through the flexible tube. According to the method a liquid sample substance is guided through the sample vessel, wherein the sample substance is gated by cyclically conveying and stopping, resp., a flow of the sample substance. A measurement is conducted within the resonator when the flow of sample substance is stopped.

Abstract: A radio frequency coil assembly for use in a magnetic resonance system comprises a set of conductors for detecting magnetic resonance signals in three orthogonal planes and capacitors for resonating the set of conductors at a predetermined frequency. A conductor of the set of conductors is placed on each edge of a cube-shaped volume and the capacitors are placed on each conductor of the set of conductors such that each conductor has substantially equal effective capacitance. A four element band pass birdcage coil comprises two square end ring segments, each end ring segment comprising four sides of equal length, and four rungs of length equal to a side of the end ring segment, and wherein four rungs join in respective corners of the end ring segments.

Abstract: A magnetic resonance imaging apparatus includes a receiver coil, at least one transmitter antenna, receiver antennas, a signal selection unit and a processing unit. The receiver coil receives a nuclear magnetic resonance signal from an object as a reception signal. The transmitter antenna transmits the reception signal by radio. The receiver antennas are arranged to receive the reception signal. The signal selection unit selects a reception signal received by a specific receiver antenna. The processing unit reconstructs an image of the object from the reception signal selected by the signal selection unit.

Abstract: A magnetic assembly for a nuclear magnetic resonance apparatus includes a number of primary permanent magnets 1 disposed in an array about a longitudinal axis, the arrangement and/or characteristics of the plurality of magnets being such so as to create a zone of homogeneous magnetic field at some location along the axis forward of the array (and into the material when provided). A secondary permanent magnet 7 may be located along the longitudinal axis within the array of primary magnets and may be moveable. The primary magnets 1 have a north pole and a south pole with an axis therebetween, and may be arranged such that the axis between the poles is at an angle to the longitudinal axis.

Abstract: An arrangement and an associated method are described in which a boring tool is moved through the ground within a given region along a path in which region a cable is buried. The boring tool and the cable transmit a boring tool locating signal and a cable locating signal, respectively. Intensities of the boring tool locating signal and the cable locating signal are measured along with a pitch orientation of the boring tool. Using the measured intensities and established pitch orientation, a positional relationship is determined to relative scale including at least the boring tool and the cable in the region. The positional relationship is displayed to scale in one view. The positional relationship may be determined and displayed including the forward locate point in scaled relation to the boring tool and the cable. Cable depth determination techniques are described including a two-point ground depth determination method.

Abstract: Metal detectors include a sense coil coupled to an analog to digital converter that produces a numeric representation of an electrical signal associated with a conductive object situated in an active region of a sense coil. The numeric representation is processed to obtain a noise contribution associated with random noise, fixed pattern noise, and/or thermal drift. The noise is subtracted from the numeric representation to produce a numeric difference. The numeric difference includes contributions associated with conductive objects located in a sense volume defined by the sense coil. The numeric difference (or the numeric representation) can be digitally processed with, for example, a matched filter to enhance the conductive object contribution. The matched filter can be based on a measured sense coil speed or can be based on typical sense coil speeds.

Abstract: A method and an apparatus detect series and/or parallel arc faults in AC and DC systems. The method according to one embodiment inputs an AC current signal; extracts a fundamental component of the AC current signal and monitoring an amplitude variation profile for the fundamental component, thereby generating a first arc fault detection measure; detects non-stationary changes in the AC current signal applying at least one measure of order higher than one, thereby generating a second arc fault detection measure; and determines whether an arc fault exists based on the first arc fault detection measure and the second arc fault detection measure.

Abstract: A chip type electronic component for test is provided with an element body, and four or more terminal electrodes placed on the exterior of the element body. The element body has a plurality of laminated insulator layers, and a plurality of internal electrodes arranged to be opposed to each other with the insulator layer in between. Each of the internal electrodes is connected to at least one same terminal electrode out of the four or more terminal electrodes and connected to any one terminal electrode except for the at least one same terminal electrode.

Abstract: A method and device for detecting defects of an electromagnetic protection for an electric harness (H). The device (D) includes elements (M1) for generating stimulating electric signals, elements (M2) for bringing the signals up to a predetermined power level, elements (M3) for applying the signals to the harness (H) and generating an electromagnetic field, elements (M4) for converting the electromagnetic field into thermal field and elements (M5) for detecting a rise in of temperature at a point of the electromagnetic protection defect (DF).

Abstract: One exemplary device has a plurality of leads with termination impedances, and a standard impedance. Among the termination impedances are master impedances arranged to be calibrated by comparison with the standard impedance and slave impedances arranged to be calibrated in accordance with an associated master impedance.

Abstract: A deflector which enables to have a sufficient degree of freedom of designing and also to detect accurately a displacement angle of a movable plate can be provided. In order to accomplish this, the deflector includes a mirror, a base frame, a pair of torsion bars which pivotably support the mirror with respect to the base frame, a drive coil which is provided on the mirror, two permanent magnets which generate a magnetic flux which acts in the drive coil, two capacitive sensors which output an angle of oscillation of the mirror as electrical characteristics, a connecting portion which electrically connects on the mirror a first end out of two ends of the drive coil and one end of electric terminals of the two capacitive sensors, and a first wire which is drawn from the connecting portion up to the torsion bars via the base frame.

Abstract: A sensor assembly has a plurality of sensing elements configured to be positioned within a seat of a vehicle. Each of the sensing elements include an output signal indicating the presence or absence of an occupant. The sensor assembly includes a cable with a plurality of conductors that are in electrical communication with the output signals of the sensing elements. The sensor assembly further provides a non-conductive spacer positioned between the cable and the plurality of sensing elements. A method for providing a sensor assembly having a spacer between sensing elements and conductors attached thereto to reduce unwanted coupling of signals onto the conductors is also disclosed.

Abstract: The invention relates to planar sensor arrangements, in particular seat mat sensors, for recognition of seat occupancy in a motor vehicle, comprising several pressure sensitive sensor elements, arranged in a planar distribution, the electrical properties of which are dependent on the local value of a measured parameter and having at least one non-rotationally symmetrical sensor element on an insulation-dependent fold line of the sensor arrangement, with a longest sectional line through the active surface of the sensor element arranged along the fold line.

Abstract: A system and method for determining the time to change the oil of an automobile engine including a power source unit for converting power into necessary power and supplies power at the startup time. A degradation detection unit is installed in an engine oil chamber and is formed using carbon nanotubes as a sensor capable of detecting degradation of the engine oil. A small signal amplification unit amplifies the signals detected from the oil conditions and amplifies the minute signal output from the degradation detection unit. The oil-condition determination unit compares value, corresponding to the degraded state of the engine oil, with a set reference value, to determine the time to change the engine oil. The display unit displaying the oil-condition in text form as information about the time to change oil.

Abstract: The present invention is directed to a contact resistance test structure and methods of using same. In one illustrative embodiment, the method includes forming a test structure comprised of two gate electrode structures, forming a plurality of conductive contacts to a doped region between the two gate electrode structures, forcing a current through the test structure and determining a resistance of at least one of the conductive contacts based upon, in part, the forced current.

Abstract: Disclosed herein are a sheet-like probe capable of surly preventing positional deviation between electrode structures and electrodes to be inspected by temperature changes in a bum-in test, even when the object of inspection is a wafer having a large area of 8 inches or greater in diameter or a circuit device, the pitch of electrodes to be inspected of which is extremely small, and thus capable of stably retaining a good electrically connected state, and a production process and applications thereof. The sheet-like probe of the present invention comprises a contact film obtained by holding a plurality of electrode structures arranged in accordance with a pattern corresponding to respective electrodes to be connected and having a front-surface electrode part exposed to a front surface and a back-surface electrode part exposed to aback surface by an insulating film composed of a flexible resin, and a frame plate supporting the contract film.

Abstract: Techniques are provided for controlling on-chip termination (OCT) impedance using OCT calibration blocks that serially transmit OCT control signals to input/output (IO) blocks. The OCT control signals are serially transmitted through a shared conductor. An OCT calibration block can transmit OCT control signals to one or multiple IO blocks. The IO blocks can be programmed to select OCT control signals from one of the calibration blocks. Enable signals enable one or more of the IO blocks to receive the selected OCT control signals. The OCT control signals are used to control the on-chip termination impedance at one or more IO buffers.

Abstract: The on-die termination circuit of the present invention includes a main resistance circuit and an adjustment circuit. The main resistance circuit is provided with a resistance element and a transistor that is turned OFF when the on-die termination circuit is to be placed in the OFF state and turned ON when the on-die termination circuit is to be placed in the ON state. The adjustment circuit is provided with transistors that are both connected together in parallel and connected in parallel to the main resistance circuit, and that are turned ON or OFF when the on-die termination circuit is placed in the ON state so as to adjust the termination resistance of the entire on-die termination circuit.

Abstract: An active terminator is configured with switches to select between terminating two lines for transmitting one differential signal pair or two single ended signals terminated in a pseudo-differential receiver. The receiver circuitry is configured with three differential comparators. One differential comparator receives both signal lines and other two differential comparators each receive one signal line and a reference voltage. The signal lines are terminated in a resistive voltage divider with electronic switches coupling the positive and ground voltages. The top and bottom nodes of the resistor divider in both terminators are cross-coupled with pass gates. In the pseudo-differential mode the pass gates are OFF and the electronic switches are ON with known resistances. In the differential mode, the electronic switches are OFF and the pass gates are ON with known resistances. The pass gate and switch resistances are sized with the resistors to insure a desired termination impedance.

Abstract: An apparatus for extending lifetime reliability of CMOS circuitry includes a logic high supply rail, a logic low supply rail, and a virtual supply rail. In an intense recovery mode of operation, a first switching device is rendered nonconductive so as to isolate the virtual supply rail from the one of the logic high supply rail and the logic low supply rail, and the second switching device is rendered conductive so as to equalize the voltage on the virtual supply rail and the other of the logic high supply rail and the logic low supply rail. At least one device within the circuitry provides one of the logic high voltage and the logic low voltage to a gate terminal of an FET within the circuitry, with a source terminal of the FET coupled to the virtual supply rail, such that the FET is subjected to a reverse bias condition.

Abstract: An apparatus for extending lifetime reliability of CMOS circuitry includes a first switching device between a logic high supply rail/logic low supply rail, and a virtual supply rail coupled to the CMOS circuitry. In a first mode of operation the first switching device supplies the full voltage value between the logic high supply rail and the logic low supply rail, and in a second mode of operation, the first switching device isolates the virtual supply rail from the logic high supply rail/logic low supply rail, thereby reducing the voltage supplied to the CMOS circuitry. A second switching device coupled between the virtual supply rail and the logic low supply rail/logic high supply rail, in a third mode of operation, equalizes the voltage on the virtual supply rail and the logic low supply rail/logic high supply rail.

Abstract: A network structure configures a blocking network having constraint against such a combination of said network input terminal and network output terminal as to make it unfeasible to further connect, when connecting first network input terminals to first network output terminals, second network input terminals to any one of the second network output terminals, and operation elements and the network output terminals are connected so as to minimize a constraint strength between the plurality of network output terminals inputting to the same operation element with respect to the constraint strength defined as the number of network input terminals contained in tuples of network input terminals to which the two network output terminals in the network output terminals can not be simultaneously connected.

Abstract: A device including a crossbar array including a programmable material layer and an array of op-amps connected to outputs of the crossbar array.

Abstract: Circuitry for facilitating the use of the memory elements in the look-up tables (“LUTs”) of a field programmable gate array (“FPGA”) as user-accessible, distributed RAM. For example, a register associated with a LUT and that is not needed in the read data path in user RAM mode can be used to register data for writing in user RAM mode. As another example, an otherwise unneeded register associated with a LUT can be used to provide a synchronous read address signal for user RAM mode. Several other features are shown for similarly facilitating user RAM mode with minimal (if any) additional circuitry being required in the FPGA.

Abstract: A system for FPGA (Field Programmable Gate Array) upgrade includes: an FPGA, a FLASH memory and a CPLD. The FLASH memory includes a first section configured to store a workable version of bit files for the FPGA and a second section configured to store a backup version of bit files for the FPGA. The CPLD is coupled to the FPGA and the FLASH memory. The CPLD is configured to download the bit files from the FLASH memory to the FPGA to provide the FPGA with functionality. As a result, the CPLD communicates with CPU to upgrade the bit files in the FLASH memory, and indicates to the CPU which version of bit files has been downloaded to the FPGA.

Abstract: A semiconductor memory device includes a primary output driver which outputs a data signal through an output terminal; a secondary output driver which is connected to the output terminal and performs a pre-emphasis operation; and a pre-emphasis signal generator which outputs a pre-emphasis signal to enable the secondary output driver The pre-emphasis signal generator includes a auto pulse generator which generates an auto pulse in response to a transition of a control signal; a delay circuit which receives the auto pulse output from the auto pulse generator, delays the auto pulse by a predetermined period, and outputs a pre-emphasis signal; and a delay control unit which applies a delay control signal to the delay circuit and controls a delay amount of the delay circuit.

Abstract: A solution for increasing the switching speed of a bus driver circuit includes a pair of transistors controlled by a pair of control circuits. Pumping circuits are placed between the control electrodes of the transistors to speed up the conduction of one of the transistors immediately after the other is in an off state. An output interface for a differential bus is produced using two bus driver circuits, the control signals of one of the circuits being inverted relative to the other of the circuits.

Abstract: A clock anomaly detection circuit includes: a dividing unit configured to output a divided target clock by dividing frequency of a target clock; a first time width measurement unit configured to obtain values of the divided target clock using rising edges of a monitoring clock that is synchronized with the target clock, and to measure an H level time with and an L level time width; a second time width measurement unit configured to obtain values of the divided target clock using falling edges of the monitoring clock, and to measure an H level time with and an L level time width; and an anomaly determination unit configured to determine that the target clock is abnormal when an anomaly is detected in the H level time width or the L level time width measured in the first time width measurement unit and when an anomaly is detected in the H level time width or the L level time width measured in the second time width measurement unit.

Abstract: A deglitch circuit utilizes a first flip-flop coupled to the input signal and a second flip-flop coupled to the output of a circuit with feedback from the output to gates to control first and second inputs to the first flip-flop. In an alternative arrangement, a counter is provided between the output of the first flip-flop and the input to the second flip-flop in order to provide flexibility and the possibility of a longer delay for the circuit.

Abstract: A sawtooth waveform generator includes an operational amplifier that generates a ramp signal. The ramp signal charges a capacitor connected between the output of the operational amplifier and the inverting input of the operational amplifier. The inverting input is maintained at a substantially constant voltage, which provides a substantially constant charging current through a timing resistor. The connections to the capacitor are switched when the ramp voltage reaches a predetermined level. A control circuit switches the connections to the capacitor in response to a voltage on one terminal of the capacitor to assure that the connections to the capacitor are switched to a configuration to cause the direction of current flow through the capacitor to be reversed as a result of the switching.

Abstract: A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase detector, which compares the phase of the output clock signal to the phase of the input clock signal. The output clock signal is generated by a voltage controlled oscillator having a control input coupled to receive an output from the phase detector, and a frequency multiplier coupled to the output of the voltage controlled oscillator. As a result, the CLKOUT signal generated by the frequency multiplier has a relatively high frequency while the voltage controlled oscillator, by operating at a relatively low frequency, uses relatively little power.

Abstract: This invention relates to a delay locked loop comprising a line of delay cells (R1, R2, . . . , Rn) mounted in series, the delay signal output by the loop being output from the output of one of the delay cells, the input of the delay cells line being connected to a first input of a phase/frequency detector (1), for which a second input is connected to an output from the delay cell. The loop comprises control means (4) capable of modifying the output from the delay cell connected to the second input of the phase/frequency detector (1), at the rate of a clock signal (H) when stimulated by control information (I). The invention is particularly applicable to generating and measuring delays and for frequency synthesis in mobile applications.

Abstract: A delay locked loop includes a delay chain that contains a plurality of series-connected delay cells, a phase detector arrangement that contains a plurality of phase detector cells and a control unit. The delay locked loop delays an input signal by a delay time via the delay chain depending on the number of delay cells in the series that are activated for delay. The phase detector arrangement detects the phase of the signal at the output of each delay cell in the delay chain. The control unit activates a number Z of the delay cells of the delay chain based on the difference in phase of the original signal and the delayed signal.

Abstract: A digital high speed programmable delayed locked loop (DLL) includes a zero degree phase shift digital delay line, at least one intermediate phase shift digital delay line, a three hundred and sixty degree phase shift digital delay line, and a digital control module. The zero degree phase shift, intermediate phase shift, and 360 degree phase shift digital delay lines are operably coupled to produce, from a clock signal, zero phase shifted, intermediate phase shifted, and 360 phase shifted representations, respectively, of the clock signal. The digital control module is operably coupled to produce an intermediate control signal for the intermediate phase shift digital delay line and a 360 degree control signal for the 360 degree phase shift digital delay line based on a phase difference between the zero phase shifted representation of the clock signal and the three hundred and sixty degree phase shifted representation of the clock signal.

Abstract: A method for synchronizing a plurality of programmable timing verniers with a reference pulse signal, each of the verniers being programmable to one of a plurality of timing steps within a delay range determined by a control signal applied to a bias input. A first and second control vernier is selected from the plurality of verniers, the first control vernier is programmed to a first delay, and the second control vernier is programmed to a second delay. The first and second control verniers are triggered together to generate respective first and second delay signals. A difference pulse signal is generated with a duty cycle corresponding to a difference between the generated first delay signal and second delay signal. The duty cycle of the pulse signal is compared to a duty cycle of the reference pulse signal to generate a difference signal pulse.

Abstract: Provided is a digital duty cycle corrector capable of generating a clock signal with the rate of duty 50:50, by means of three or more duty cycle correction circuits assigning different weight values to first and second clock signals that are different in duty cycle each other in order to reduce a phase difference between the first and second clock signals, and one or more duty cycle correction circuits assigning the same weight value to the first and second clock signals in order to eliminate a phase difference between the first and second clock signals.

Abstract: Provided is a multi-threshold complementary metal oxide semiconductor (MTCMOS) latch circuit including: a data inverting circuit for inverting and outputting input data under the control of a sleep control signal; a transmission gate for transferring the data signal output from the data inverting circuit under the control of a clock control signal; a signal control circuit for outputting the data signal output from the transmission gate under the control of a reset control signal and the sleep control signal; and a feedback circuit for feeding back the signal output from the signal control circuit and preserving the data in a sleep mode. The MTCMOS latch circuit can minimize power consumption caused by a leakage current due to elements scaled down to nano scale and also contribute to high-speed operation of a logic circuit by using an element having a low threshold voltage.

Abstract: For retaining an output data signal of a data retention cell in a power-saving mode, a slave latch unit of the data retention cell is powered with a real power for preserving the output data signal. The output data signal is furnished backward to an input control circuit of the data retention cell. The data signal furnished to a master latch unit of the data retention cell is controlled to switch between an input data signal and the output data signal by the input control circuit in response to a retention signal. The switching of the data signal for refreshing the master latch unit is delayed by a delay unit of the input control circuit, which functions to make sure that the data-preserving process is properly operated on any transition from the power-saving mode to a power-active mode.

Abstract: An adjustable-delay filter performs wave shaping to emulate pre-emphasis or de-emphasis of transmission-line signals. The adjustable-delay filter uses analog components and does not need a clock. The receiver does not have to recover a bit-clock from the data stream, eliminating a clock recovery circuit. An input buffer receives the input signal and drives current to a summer and to an adjustable delay. The adjustable delay inverts and delays the current and drives a delayed, inverted current to the summer. The summer combines the delayed, inverted current and the current from the input buffer to generate an output signal. The delay time of the adjustable delay can be programmed by a user and is less than the bit period. After a signal transition, the output signal initially spikes higher, then falls back to a nominal level after the delay time has expired. The initial signal spike emulates de-emphasis or pre-emphasis.

Abstract: A circuit arrangement in which the temperature dependency of the short-circuit current and/or the influence of the output signal by the load current are at least partially avoided has first and second input connections, first and second output connections, a supply voltage connection as well as with a voltage-controlled voltage source, an output stage and a short-circuit protective circuit, whereby the output signal from an input voltage applied to input connections is generated via voltage-controlled voltage source and output stage. The circuit arrangement is characterized in that a voltage sequencing circuit and a shunting resistor connected in parallel to voltage sequencing circuit are part of the short-circuit protective circuit and in that a parallel circuit formed of the voltage sequencing circuit and a shunting resistor is connected to the second output connection and second input connection.

Abstract: To save power consumption in a semiconductor integrated circuit 2A increased due to a leak current caused by a variation in a manufacturing process, temperature, and a power supply voltage. A semiconductor integrated circuit 2A, a leak current detection circuit 3, a comparison operation circuit 4 and an applied voltage output circuit 5A are provided. The semiconductor integrated circuit 2A has a circuit body 21 Including a plurality of functional MOSFETs for performing predetermined functional operations, and a monitor circuit 22A including a plurality of monitor NMOSFETs 23 for monitoring properties of the functional MOSFETs. The leak current detection circuit 3 detects leak data corresponding to leak currents from the monitor NMOSFETs 23, and outputs the detected leak data. The comparison operation circuit 4 extracts, from a plurality of pieces of leak data, one piece of leak data minimizing a leak current in the circuit body 21, and outputs the extracted leak data as applied voltage data.

Abstract: An internal supply voltage generation circuit includes first and second driving circuits and a resistive device. The first driving circuit receives a feedback voltage from a first node and generates a first output voltage based on first and second reference voltages to provide the first output voltage to the first node. The first output voltage is maintained between the first and second reference voltages. The second driving circuit receives a feedback voltage from a second node voltage and generates a second output voltage based on third and fourth reference voltages to provide the second output voltage to the second node. The second output voltage is maintained between the third and fourth reference voltages, and the second output voltage of the second node is provided as an internal supply voltage. The resistive device is coupled between the first and second nodes.

Abstract: A module includes a semiconductor device, a phase adjustment circuit generating a second clock so that a phase adjustment signal output from the semiconductor device and a first clock have a predetermined phase relationship, and an output circuit that is provided in the semiconductor device and generates the phase adjustment signal from the second clock.

Abstract: The present disclosure relates generally to systems and methods for direct current (DC) correction in wireless devices. In one example, a method includes setting a cutoff frequency of a filter at a first frequency, where a signal entering the filter is attenuated based on the cutoff frequency. If a qualified change is detected in a DC component of the signal, the cutoff frequency is set at a second frequency that attenuates more of the signal than the first frequency for a defined time period. The cutoff frequency may then be set to the first frequency after the defined time period.

Abstract: This disclosure describes a chopper stabilized instrumentation amplifier. The amplifier is configured to achieve stable measurements at low frequency with very low power consumption. The instrumentation amplifier uses a differential architecture and a mixer amplifier to substantially eliminate noise and offset from an output signal produced by the amplifier. Dynamic limitations, i.e., glitching, that result from chopper stabilization at low power are substantially eliminated through a combination of chopping at low impedance nodes within the mixer amplifier and feedback. The signal path of the amplifier operates as a continuous time system, providing minimal aliasing of noise or external signals entering the signal pathway at the chop frequency or its harmonics. The amplifier can be used in a low power system, such as an implantable medical device, to provide a stable, low-noise output signal.

Abstract: The invention relates to a self-oscillating circuit comprising comparator means (CM) comprising at least one input means (IM) and at least one output means (OM), at least one of said at least one output means (OM) is coupled to at least one of said at least one input means (IM) via at least one filtering means (FM), said at least one filtering means (FM) at least partly comprising demodulation means (DM), wherein said filtering means (FM) is of at least fifth order.

Abstract: Embodiments of the present invention comprise methods and devices for amplifying a signal by amplifying a first signal and by then amplifying a second signal only if the first signal exceeds a predetermined threshold. The first and second amplified signals are then combined, and the combination is fed back to a signal source and used to control the values of the first and second signal. The combination is further transmitted to a load. In the preferred embodiment, the first amplified signal is transmitted through an impedance inverter before it is combined with the second amplified signal.

Abstract: An analog variable gain amplifier (VGA) adjusting a signal level of a mobile communication system is provided. More particularly, design of a VGA using an operational transconductance amplifier (OTA) having a wide linear input/output range is disclosed. The VGA includes two double-differential-pair OTAs and feedback resistors. A first differential input of a first double differential pair OTA receives an input signal from the forward stage, and a second differential input is negatively fed back through a differential output and a passive resistor. An input in which a first block of the connection structure and first and second differential inputs of a second double differential pair OTA are connected receives an output signal of the first block stage. The output is negatively fed back in series through a variable resistor whose resistance varies exponentially with an adjustment voltage from outside.