Patents Issued in June 24, 2008
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Patent number: 7391613Abstract: A memory module assembly includes a printed circuit board (10) having a main heat-generating electronic component (52) thereon, first and second heat sinks (20), (30) attached on opposite sides of the printed circuit board and a clamp (40) clamping the first, second heat sinks and the printed circuit board together. The first heat sink comprises a pair of positioning poles (24). The second heat sink comprises a heat pipe (36) disposed therein and thermally connecting therewith. The clamp comprises a connecting portion (42) and a pair of elastic pressing portions (44). The clamp resiliently presses the second heat sink toward the main heat-generating electronic component and the first heat sink engages with the second heat sink via the positioning poles of the first heat sink extending in and engaging with the second heat sink.Type: GrantFiled: May 12, 2006Date of Patent: June 24, 2008Assignees: Fu Zhun Precision Industry (Shen Zhen) Co., Ltd., Foxconn Technology Co., Ltd.Inventors: Cheng-Tien Lai, Zhi-Yong Zhou, Qiao-Li Ding
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Patent number: 7391614Abstract: A thermal dissipation apparatus includes a primary heat sink. The primary heat sink includes a first base member having a component coupling surface and a secondary heat sink coupling surface, and a plurality of fins extending from the first base member. A secondary heat sink may be provided such that the primary heat sink is operable to provide thermal dissipation in a low profile form factor chassis while the secondary heat sink may be coupled with the primary heat sink to provide more optimal thermal dissipation in a high profile form factor chassis.Type: GrantFiled: March 24, 2005Date of Patent: June 24, 2008Assignee: Dell Products L.P.Inventor: Paul T. Artman
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Patent number: 7391615Abstract: A clip includes a body with opposite first and second legs, a movable fastener, an actuating member and a sliding axle. The movable fastener has a retaining hole defined therein for engaging with a retention module and an elongated slot above the retaining hole. The actuating member includes a curving slot and is pivotally coupled to the movable fastener via a pivot. The sliding axle extends through the second leg of the body and the elongated slot of the movable fastener to couple them together, and the sliding axle has one portion inserted into the curving slot of the actuating member. When the actuating member is rotated about the pivot, the movable fastener is driven to move relative to the sliding axle between a relaxed position and a locked position.Type: GrantFiled: October 10, 2006Date of Patent: June 24, 2008Assignees: Fu Zhun Precision Industry (Shen Zhen) Co., Ltd., Foxconn Technology Co., Ltd.Inventors: Meng Fu, Shi-Wen Zhou, Chun-Chi Chen
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Patent number: 7391616Abstract: A plasma display device includes: a Plasma Display Panel(PDP); a chassis base adapted to support the PDP attached to one surface thereof, a plurality of Integrated Circuit (IC) modules respectively included on driving circuit boards attached to another surface of the chassis base and adapted to control the PDP; and a reinforcing member arranged on the chassis base, one surface of each of the IC modules being in contact with the reinforcing member. The integrated circuit module is attached to the reinforcing member which reinforces the mechanical strength of the chassis base, so that a heat sink is not needed. The thickness of a plasma display device is thereby reduced and the appearance of the plasma display device is improved.Type: GrantFiled: July 6, 2005Date of Patent: June 24, 2008Assignee: Samsung SDI Co., Ltd.Inventors: Ki-Jung Kim, Won-Kyu Bang
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Patent number: 7391617Abstract: A cooling arrangement for a computer system includes a base plate, a system board which coupled to the base plate, a processor arranged on the system board, and a cooling apparatus arranged on the processor. A holding plate is provided between the base plate and the system board in the region of the processor, and the cooling apparatus is connected, via connectors, to the holding plate such that the cooling apparatus can move relative to the holding plate.Type: GrantFiled: July 17, 2006Date of Patent: June 24, 2008Assignee: Fujitsu Siemens Computers GmbHInventor: Günther Veh
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Patent number: 7391618Abstract: Airflow is introduced into an enclosure through an air inlet in an electronic component unit. The airflow runs toward a first electronic component. The airflow absorbs heat from the first electronic component. The first electronic component is thus sufficiently cooled. A second electronic component is mounted on a printed wiring board at a position remoter from the air inlet than the position of the first electronic component. An air intake opening is formed in the enclosure. The air intake opening is defined at a section of the enclosure opposed to the printed wiring board at least between the first and second electronic components. Airflow is introduced toward the second electronic component through the air intake opening. The second electronic opening is thus sufficiently cooled. In this manner, the first and second electronic components are cooled equally to the utmost.Type: GrantFiled: March 24, 2006Date of Patent: June 24, 2008Assignee: Fujitsu LimitedInventors: Hiromitsu Fujiya, Hideki Kimura
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Patent number: 7391619Abstract: A structure of a latch for an interface card is provided. The latch has a base plate including a plurality of pins formed on two sides thereof, a horn and a spring portion. The spring portion has a supporting portion with an inclined face at a frontal side thereof, and a wing and a block respectively formed at two sides thereof. The wing and the supporting portion are bent towards opposite sides, and said spring portion has a protrusion.Type: GrantFiled: September 14, 2007Date of Patent: June 24, 2008Inventor: Ching-Yao Lee
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Patent number: 7391620Abstract: A method and system for improving power distribution and/or current measurement on a printed circuit board is disclosed. According to the invention, a first power plane adapted for current measurement includes a first segment to which a current source is connected and a second segment to which other devices may be connected, forming the current load. A third segment is used to measure the current between the first segment and the second segment through two vias that link two points of the third segment to, preferably, two pads of the external layer. In a preferred embodiment, vias are connected to the first segment so that current flow in the third segment is linear, to improve and simplify current determination. The resistivity between the pair of vias may be computed or estimated using calibrated currents.Type: GrantFiled: December 17, 2003Date of Patent: June 24, 2008Assignee: International Business Machines CorporationInventors: Jean-Francois Fauh, Claude Gomez, Andre Lecerf, Denis G. Roman
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Patent number: 7391621Abstract: In an electronic device printed circuit boards in a housing are kept parallel to each other by guiding means. One or a plurality of these printed circuit boards is connected with a housing part each on their corresponding edge by means of electronic plug-in connections. To secure the electronic plug-in connections, spring means are provided which exert pressure on opposite edges of the printed circuit boards in the direction of the plug-in connection.Type: GrantFiled: November 1, 2006Date of Patent: June 24, 2008Assignee: Thomson LicensingInventors: Wolfgang Metje, Nicolaas Johannes Damstra
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Patent number: 7391622Abstract: A composite structural member with an integrated electrical circuit is provided. The structural member includes a plurality of layers of structural reinforcement material, and two or more electrical devices are disposed at least partially between the layers with an intermediate layer of the structural reinforcement material disposed between the electrical devices. At least one electrical bus is disposed in the structural member, and each electrical device is connected to the bus by a conductive electrode. Thus, the electrodes can extend through the intermediate layer of the structural reinforcement material to connect each of the electrical devices to one or more of the buses.Type: GrantFiled: September 6, 2007Date of Patent: June 24, 2008Assignee: The Boeing CompanyInventors: Joseph A. Marshall, Douglas B. Weems, Richard C. Bussom, David M. Anderson
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Patent number: 7391623Abstract: The present invention provides a display module having: a display board on which a display element displaying an image is mounted; and a chassis on which the display board is mounted and which is placed on a circuit board. The chassis has a support board and a frame plate. The support board includes: a support section which supports a portion of the display board except for a corner section of the display board; and a depressed section which continuously expands from the support section and is formed such that a surface on a side supporting the display board is lower than the support section. The frame plate is placed on the circuit board while supporting the support board at a predetermined height with respect to the circuit board.Type: GrantFiled: September 23, 2005Date of Patent: June 24, 2008Assignee: Fujitsu LimitedInventors: Yoshihiko Kaito, Shigeru Yamaguchi
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Patent number: 7391624Abstract: An adjustable mounting bracket for secure adhesive mounting onto an exposed edge of a substrate, wherein the mounting bracket is adapted for subsequently supporting a selected structure such as tubing, wire bundles, etc., relative to the substrate. The mounting bracket includes slidably interfitting, generally L-shaped bracket members which cooperatively define a slidably overlying pair of mounting plates and an associated pair of slidably separable clamp jaw plates having inboard faces carrying a selected bonding agent and adapted to seat firmly against opposed substrate edge surfaces. A resilient fixture pin is carried by the mounting plates and can be actuated to apply a positive force urging the clamp jaw plates against the opposed surfaces of the substrate edge of the duration of a bonding agent cure time, after which the fixture pin can be forcibly removed from the mounting bracket.Type: GrantFiled: May 11, 2006Date of Patent: June 24, 2008Assignee: Physical Systems, Inc.Inventor: Charles G. Hutter, III
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Patent number: 7391625Abstract: The present disclosure relates to a rack for telecommunications equipment. The rack includes a frame defining a bay opening sized and shaped for receiving a plurality of jack modules. The rack also includes a first set of cable management brackets that define a first vertical channel arranged and configured for receiving and vertically managing a plurality of cross-connect cables. Each of the cable management brackets includes a pivot portion that is pivotally movable relative to the frame. The pivot portions are pivotally movable between first positions in which the pivot portions extend partially across a front of the bay opening, and second positions in which the pivot portions are generally offset from the front of the bay opening. The present disclosure also relates to a rack for telecommunications equipment that includes rear cable management structure that defines a plurality of vertical channels along a back side of the rack.Type: GrantFiled: September 27, 2004Date of Patent: June 24, 2008Assignee: ADC Telecommunications, Inc.Inventor: Jose-Filonel Tawag Mendoza
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Patent number: 7391626Abstract: A chop-wave control circuit includes a feedback unit, a ramp generation unit, a latchup unit and a voltage transformation unit that is used on a forward transformation circuit which includes at least a main output unit and at least one auxiliary output unit. The feedback unit captures a feedback signal from an output end of the auxiliary output unit to generate a slope regulation signal. The ramp generation unit alters the trigger time sequence of the latchup unit through the slope regulation signal to set an auxiliary flywheel switch ON or OFF. The voltage transformation unit detects potential variations of the latchup unit to set a chop-wave switch ON or OFF. By controlling the auxiliary flywheel switch and the chop-wave switch a power output cycle of the auxiliary output unit can be formed.Type: GrantFiled: June 8, 2007Date of Patent: June 24, 2008Assignee: FSP Technology Inc.Inventor: Kuo-Fan Lin
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Patent number: 7391627Abstract: A power converter comprises an inductor (LP) and a controllable switch (CF) coupled to the inductor. A switch controller (1) supplies a periodic switching signal (VC1) which has a repetition time and a duty cycle to the controllable switch (CF) to generate a periodical inductor current (IL) through the inductor. A generator (2) generates an emulated signal (IE) based on timing information (TI) which represents the repetition time and the duty cycle to emulate a current signal being representative of the inductor current. A comparator (3) compares the emulated signal (IE) with the current signal (CS) to obtain an error signal (E). A generator controller (4) receives the error signal (E) to supply a control signal (VD) to the generator (2) to adapt a property of the emulated signal (IE) to become substantially equal to a property of the current signal (CS).Type: GrantFiled: May 21, 2003Date of Patent: June 24, 2008Assignee: NXP B.V.Inventors: Johan Christiaan Halberstadt, Gerrit Van Der Horn
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Patent number: 7391628Abstract: A switching controller having frequency hopping is used for reducing the EMI of a power supply. A pattern generator generates a digital pattern code in response to a clock signal. An oscillator generates an oscillation signal for determining a switching frequency of a switching signal. A programmable capacitor coupled to the oscillator modulates the switching frequency in response to the variation of the digital pattern code. An attenuator connected to a voltage feedback loop attenuates a feedback signal. The feedback signal controls the pulse width of the switching signal. A programmable resistor coupled to the attenuator determines an attenuation rate of the attenuator in response to the digital pattern code. The attenuation rate is increased as the switching frequency increases. The pulse width of the switching signal is thus reduced, which compensates the decrease of the switching period and keeps the output power and the output voltage constant.Type: GrantFiled: February 27, 2007Date of Patent: June 24, 2008Assignee: System General Corp.Inventors: Ta-yung Yang, Guo-Kiang Hung, Song-Yi Lin
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Patent number: 7391629Abstract: Disclosed is an SMPS for preventing abnormal overcurrents. A circuit having a short circuit delay is used to generate a control signal for turning off a main switch (i.e., a switching MOS transistor) when the overcurrent occurs, that is, in an initial startup or when a protection circuit is operated. Accordingly, a drain-source voltage of the main switch is reduced when the main switch is turned off, and a switching MOS transistor with a low withstanding voltage can be used.Type: GrantFiled: August 5, 2005Date of Patent: June 24, 2008Assignee: Fairchild Korea Semiconductor, Ltd.Inventors: Young-Chul Ryu, Jin-Ho Choi
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Patent number: 7391630Abstract: A Power Factor Correction (PFC) system providing near unity power factor for an AC power source (VAC) connected to a complex load. The system includes a bridge rectifier, boost or buck-boost converter, complex load, and pulse width modulation (PWM) controller to provide pulses with variable duty cycle to a power switch. The invention is a constant pulse proportional current (CPPC) PWM controller that generates trains of pulses constant in frequency and duty cycle for one semi-cycle of the VAC. The duty cycle of the driving signal is modified by applying open-loop correction signals to summing nodes of PWM circuits. Since the PWM provides a constant train of driving pulses with constant duty cycle for one semi-cycle of the VAC, the current absorbed by the converter is contingent and linearly proportional to the voltage. Thus, the output current follows the voltage resulting in a power factor of near unity.Type: GrantFiled: October 25, 2004Date of Patent: June 24, 2008Assignee: PF1, Inc.Inventor: Benjamin Acatrinei
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Patent number: 7391631Abstract: A switching power source device is provided which comprises a drive controller 40 connected between an error amplifier 26 and changeover circuit 37. A second comparator 52 of drive controller 40 compares an output voltage or an equivalent signal thereto from error amplifier 26 with a numerical value from a sweep circuit 57 and produces an output to changeover circuit 37 to stop the on-operation of a switching element 4 and restrict an undesirable rise in output voltage during the light load period when the numerical value exceeds the output voltage or an equivalent signal thereto from error amplifier 26.Type: GrantFiled: March 14, 2006Date of Patent: June 24, 2008Assignee: Sanken Electric Co., Ltd.Inventor: Masaaki Shimada
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Patent number: 7391632Abstract: A Fast Fourier Transform (FFT) apparatus for selectively performing Fast Hadamard transform (FHT), and a complementary code keying (CCK) modulation/demodulation apparatus using the same. An OFDM module and CCK module are integrated as one module having lower complexity compared to conventional scheme by embodying the CCK modulation using FFT structure in the OFDM module, and embodying the suboptimal and the optimized CCK modulations using FFT structure in OFDM module. CDMA, OFDM, CCK modules may be integrated as single module.Type: GrantFiled: November 14, 2005Date of Patent: June 24, 2008Assignee: Electronics and Telecommunications Research InstituteInventors: Tae-Joon Kim, Ik-Soo Eo, Kyung-Soo Kim, Hee-Bum Jung
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Patent number: 7391633Abstract: A sensing circuit for use with a CAM circuit including multiple match lines and multiple CAM cells connected to the match lines includes at least one charge sharing circuit and at least one switching circuit connected to the charge sharing circuit. The switching circuit is operative to selectively connect the charge sharing circuit to a corresponding one of the match lines as a function of a first control signal supplied to the switching circuit. The sensing circuit further includes at least one comparator circuit connected to the corresponding match line and operative to generate an output signal indicative of a match between search data supplied to at least a given one of the CAM cells connected to the corresponding match line and data stored in the given CAM cell. The charge sharing circuit is operative to remove an amount of charge on the corresponding match line so as to reduce a voltage on the corresponding match line in conjunction with a search operation of the CAM cell.Type: GrantFiled: July 26, 2006Date of Patent: June 24, 2008Assignee: Agere Systems Inc.Inventors: Dennis E. Dudeck, Donald Albert Evans, Hai Quang Pham, Wayne E. Werner, Ronald James Wozniak
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Patent number: 7391634Abstract: A semiconductor memory device may include a semiconductor substrate, a first unit memory device on the substrate, and a second unit memory device on the substrate. The first unit memory device may be configured to receive first through Nth data bits and/or to provide first through Nth data bits to an external device in response to a command signal, an address signal, and a clock signal, and in response to a first chip selection signal. The second unit memory device may be configured to receive (N+1)th through 2Nth data bits and/or to provide (N+1)th through 2Nth data bits to an external device in response to the command signal, the address signal, and the clock signal, and in response to a second chip selection signal. Related methods are also discussed.Type: GrantFiled: February 21, 2006Date of Patent: June 24, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Hoon Kim, Seong-Jin Jang, Su-Jin Park
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Patent number: 7391635Abstract: An apparatus and method for storage and retrieval of memory content including a storage structure containing a plurality of memory elements addressable as a two-dimensional array of memory content values, a reading circuit capable of retrieving the memory content values from a region of the two-dimensional array varying in size according to the desired memory readout resolution, an aggregating circuit capable of totaling the memory content values of the memory elements addressed by the reading circuit to produce an aggregate memory content value and a normalizing circuit capable of scaling the aggregate memory content value according to the number of memory elements in the contiguous region to produce an average memory content value of the desired memory readout resolution.Type: GrantFiled: November 1, 2005Date of Patent: June 24, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventor: Warren Bruce Jackson
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Patent number: 7391636Abstract: A semiconductor memory device and an arrangement method thereof are included. The semiconductor memory device includes column selecting signal lines and global data IO signal lines arranged on the same layer in the same direction above a memory cell array; word lines and first local data IO signal lines arranged on a different layer from the column selecting signal lines above the memory cell array, in a perpendicular direction to the column selecting signal lines; and second local data IO signal lines arranged on a different layer from the column selecting signal lines and the word lines above the memory cell array, in the same direction as the first local data IO signal lines.Type: GrantFiled: September 27, 2007Date of Patent: June 24, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Chul-Woo Park, Sung-Hoon Kim, Hyuk-Joon Kwon, Jung-Bae Lee, Youn-Sik Park
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Patent number: 7391637Abstract: A memory device is provided with a structure for improved transmission line operation on integrated circuits. The structure for transmission line operation includes a first layer of electrically conductive material on a substrate. A first layer of insulating material is formed on the first layer of the electrically conductive material. A number of high permeability metal lines are formed on the first layer of insulating material. The number of high permeability metal lines includes composite hexaferrite films. A number of transmission lines is formed on the first layer of insulating material and between and parallel with the number of high permeability metal lines. A second layer of insulating material is formed on the transmission lines and the high permeability metal lines. The structure for transmission line operation includes a second layer of electrically conductive material on the second layer of insulating material.Type: GrantFiled: August 3, 2004Date of Patent: June 24, 2008Assignee: Micron Technology, Inc.Inventors: Leonard Forbes, Kie Y. Ahn, Salman Akram
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Patent number: 7391638Abstract: Improved circuitry and methods for programming memory cells of a memory device are disclosed. The improved circuitry and methods operate to protect the memory cells from potentially damaging electrical energy that can be imposed during programming of the memory cells. Additionally, the improved circuitry and methods operate to detect when programming of the memory cells has been achieved. The improved circuitry and methods are particularly useful for programming non-volatile memory cells. In one embodiment, the memory device pertains to a semiconductor memory product, such as a semiconductor memory chip or a portable memory card.Type: GrantFiled: October 24, 2006Date of Patent: June 24, 2008Assignee: SanDisk 3D LLCInventors: Luca G. Fasoli, Tyler Thorp
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Patent number: 7391639Abstract: A memory with memory cells, wherein a memory cell includes a resistive element and a switch, wherein the memory cells are connected with a common plate line and with respective bit lines, wherein the common plate line supplies a plate voltage, wherein the switches include control inputs that are connected with word lines for controlling the switching states, wherein the word lines are connected with a word line driver that supplies selected word lines with a voltage, wherein the bit lines are connected with second switches, wherein the first bit lines are connectable by respective second switches with a first voltage level and the second bit lines are connectable by respective second switches with a second voltage level, wherein a first and a second bit line are connectable as a bit line pair with a sense amplifier, wherein the sense amplifier amplifies a voltage difference between the first and the second bit line of the bit line pair, wherein the resistive element is able to change the resistance dependingType: GrantFiled: February 14, 2006Date of Patent: June 24, 2008Assignee: Infineon Technologies AGInventor: Dietmar Gogl
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Patent number: 7391640Abstract: A dynamic random access memory includes a cell having a circuit between a floating-body transistor and a bit line. Activation of the circuit is controlled to provide isolation between the floating body and bit-line voltage both during write operations and during times when the cell is unselected. The added isolation improves performance, for example, by reducing the need for gate-to-body coupling and the magnitude of voltage swings between the bit lines.Type: GrantFiled: December 10, 2004Date of Patent: June 24, 2008Assignee: Intel CorporationInventors: Stephen H. Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad M. Khellah, Yibin Ye, Shih-Lien L. Lu, Vivek K. De
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Patent number: 7391641Abstract: An exemplary memory array including a plurality of memory cells, each of the memory cells comprises a first ferromagnetic layer, a second ferromagnetic layer spaced apart from the first ferromagnetic layer by a non-magnetic separating layer and being magnetically coupled to the first ferromagnetic layer by demagnetizing fields from the first ferromagnetic layer, a spacer layer above the second ferromagnetic layer, and a reference layer above the spacer layer. The first ferromagnetic layer, non-magnetic separating layer, and second ferromagnetic layer in combination function as a data layer of the memory cell.Type: GrantFiled: November 23, 2005Date of Patent: June 24, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Manish Sharma, Lung Tran, Thomas C. Anthony
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Patent number: 7391642Abstract: A method for programming a phase change memory cell is discussed. A phase change memory cell includes a memory element of a phase change material having a first state, in which the phase change material is crystalline and has a minimum resistance level, a second state in which the phase change material is amorphous and has a maximum resistance level, and a plurality of intermediate states, in which the phase change material includes both crystalline regions and amorphous regions and has intermediate resistance levels. According to the method, a plurality of programming pulses are provided to the phase change memory cell; programming energies respectively associated to the programming pulses are lower than a threshold energy which is required to bring the phase change material to the second state.Type: GrantFiled: January 25, 2005Date of Patent: June 24, 2008Assignee: Intel CorporationInventors: George Gordon, Stephen Hudgens, Fabio Pellizzer, Agostino Pirovano
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Patent number: 7391643Abstract: To provide a semiconductor memory device comprising a phase-change memory and having high compatibility with DRAM interface. The memory cell array 18 comprises a memory cell that includes a phase-change element provided at the intersection of a bit line and word line. A write address and data accompanying a write request are temporarily held in a write address register 15 and a data register 14 respectively, and a write operation is not performed on the memory cell array 18 in this cycle of write request. And when a next write request occurs, the held data is written to the memory cell array 18. At this time, two write cycles—RESET cycle and SET cycle—are provided. Then the written contents of the memory cell and the rewrite data are compared, and after only SET cells are temporarily RESET (amorphization, increasing the resistance), it is operated so as to write only SET data (crystallization, lowering the resistance).Type: GrantFiled: January 27, 2006Date of Patent: June 24, 2008Assignee: Elpida Memory, Inc.Inventor: Yukio Fuji
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Patent number: 7391644Abstract: Disclosed is a phase-changeable memory device and a related method of reading data. The memory device is comprised of memory cells, a high voltage circuit, a precharging circuit, a bias circuit, and a sense amplifier. Each memory cell includes a phase-changeable material and a diode connected to a bitline. The high voltage circuit provides a high voltage from a power source. The precharging circuit raises the bitline up to the high voltage after charging the bitline up to the power source voltage. The bias circuit supplies a read current to the bitline by means of the high voltage. The sense amplifier compares a voltage of the bitline with a reference voltage by means of the high voltage, and reads data from the memory cell. The memory device is able to reduce the burden on the high voltage circuit during the precharging operation, thus assuring a sufficient sensing margin during the sensing operation.Type: GrantFiled: November 29, 2006Date of Patent: June 24, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Woo-Yeong Cho, Byung-Gil Choi, Du-Eung Kim, Hyung-Rok Oh, Beak-Hyung Cho, Yu-Hwan Ro
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Patent number: 7391645Abstract: Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop across the resistance and results in errors in the applied control gate and drain voltages. This error is minimized when the applied control gate and drain voltages have their reference point located as close as possible to the sources of the memory cells. In one preferred embodiment, the reference point is located at a node where the source control signal is applied. When a memory array is organized in pages of memory cells that are sensed in parallel, with the sources in each page coupled to a page source line, the reference point is selected to be at the page source line of a selected page via a multiplexor.Type: GrantFiled: January 18, 2007Date of Patent: June 24, 2008Assignee: Sandisk CorporationInventors: Raul-Adrian Cernea, Siu Lung Chan
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Patent number: 7391646Abstract: Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop across the resistance and results in errors in the applied control gate and drain voltages. This error is minimized when the applied control gate and drain voltages have their reference point located as close as possible to the sources of the memory cells. In one preferred embodiment, the reference point is located at a node where the source control signal is applied. When a memory array is organized in pages of memory cells that are sensed in parallel, with the sources in each page coupled to a page source line, the reference point is selected to be at the page source line of a selected page via a multiplexor.Type: GrantFiled: January 18, 2007Date of Patent: June 24, 2008Assignee: Sandisk CorporationInventors: Raul-Adrian Cernea, Siu Lung Chan
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Patent number: 7391647Abstract: A non-volatile memory (NVM) cell fabricated on a semiconductor substrate, and including a floating gate electrode (which extends at least partially over all active regions of the NVM cell). The NVM cell also includes a PMOS access transistor located in a first n-type region, a PMOS control capacitor located in a second n-type region (separate from the first n-type region), and an NMOS programming transistor located in a p-type region. The floating gate electrode is a continuous electrode which extends over the active regions of the PMOS access transistor, the PMOS control capacitor and the NMOS programming transistor. Various array connections are provided for implementing arrays using this NVM cell. The PMOS access transistor and NMOS programming transistor can be replaced with an NMOS access transistor and a PMOS erase transistor, respectively, in an alternate embodiment.Type: GrantFiled: April 11, 2006Date of Patent: June 24, 2008Assignee: Mosys, Inc.Inventors: Gang-feng Fang, Dennis Sinitsky, Wingyu Leung
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Patent number: 7391648Abstract: A regulated charge pump, regulated by a plurality of capacitor boost stages and separate from the memory device supply voltage (Vcc), generates a regulated voltage (VSA) over a range of supply voltages. The regulated charge pump powers sense amplifier and differential amplifier circuits of the memory device to permit a low bit line bias voltage. The differential amplifier circuit generates a logical output to indicate a memory cell programmed state that is detected by the sense amplifier circuit.Type: GrantFiled: October 27, 2005Date of Patent: June 24, 2008Assignee: Micron Technology, Inc.Inventor: Theodore T. Pekny
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Patent number: 7391649Abstract: In one aspect, a non-volatile memory device includes a non-volatile memory cell array and a page buffer. The page buffer includes a sense node selectively connected to a bit line of the memory cell array, a main latch circuit including first and second main latch nodes, where the first main latch node is selectively connected to the sense node, and a latch input node selectively connected to the first and second main latch nodes. The page buffer further includes a cache latch circuit including first and second cache latch nodes, a switching circuit which selectively connects the second cache latch node to the latch input node, and a shared sense circuit connected between to the latch input node and a reference potential. The shared sense circuit selectively connects the latch input node to the reference potential in response to a voltage of the sense node and a voltage of the first cache latch node.Type: GrantFiled: May 3, 2006Date of Patent: June 24, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Joo-Ah Kang, Jong-Hwa Kim, Moo-Sung Kim
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Patent number: 7391650Abstract: Reading and verify operations are performed on non-volatile storage elements using temperature-compensated read voltages for unselected word lines, and/or for select gates such as drain or source side select gates of a NAND string. In one approach, while a read or verify voltage is applied to a selected word line, temperature-compensated read voltages are applied to unselected word lines and select gates. Word lines which directly neighbor the selected word line can receive a voltage which is not temperature compensated, or which is temperature-compensated to a reduced degree. The read or verify voltage applied to the selected word line can also be temperature-compensated. The temperature compensation may also account for word line position.Type: GrantFiled: June 16, 2006Date of Patent: June 24, 2008Assignee: Sandisk CorporationInventors: Nima Mokhlesi, Dengtao Zhao
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Patent number: 7391651Abstract: A method for programming a multi-level-cell NAND flash memory device having plural memory cells is disclosed to reduce the programming time. The method comprises: programming each memory cell to a zero state, programming from the zero state to a first state by activating a first program signal and programming from the zero state to a quasi-second state and a semi-third state by activating a second program signal, programming from the quasi-second state to a second state and programming from the semi-third state to a quasi-third state by activating the second program signal, and programming from the quasi-third state to a third state by activating the first program signal. The present invention also discloses a page buffer to perform the method for programming a multi-level-cell NAND flash memory device, which comprises a bit line selection circuit, a first register, a second register, a first verify circuit, a second verify circuit and an exclusion circuit.Type: GrantFiled: May 12, 2006Date of Patent: June 24, 2008Assignee: Elite Semiconductor Memory Technology Inc.Inventor: Chung Zen Chen
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Patent number: 7391652Abstract: A programming method for a p-channel memory cell, the memory cell includes a source, a drain and a gate. The gate is applies with a first voltage, which results in Fowler-Nordheim (?FN) hole injection, thereby causing the memory cell to be in a programmed state.Type: GrantFiled: May 5, 2006Date of Patent: June 24, 2008Assignee: Macronix International Co., Ltd.Inventor: Hang-Ting Lue
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Patent number: 7391653Abstract: The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.Type: GrantFiled: April 21, 2006Date of Patent: June 24, 2008Assignee: Halo LSI, Inc.Inventors: Seiki Ogura, Kimihiro Satoh, Tomoya Saito
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Patent number: 7391654Abstract: The erase and verify method performs an erase operation and an erase verify read operation. If the erase verify read operation fails because unerased memory cells have been found, a normal memory read operation is performed in order to determine which memory cells are still programmed. A selective erase operation is then performed on the memory cells such that only the rows that comprise unerased memory cells undergo additional erase operations.Type: GrantFiled: May 11, 2005Date of Patent: June 24, 2008Assignee: Micron Technology, Inc.Inventor: Seiichi Aritome
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Patent number: 7391655Abstract: Erasing is performed with respect to a nonvolatile memory cell without causing depletion halfway therethrough. A control circuit for reversibly and variably controlling the threshold voltage of the nonvolatile memory cell by electrical erasing and writing controls an erase process of performing erasing to the plurality of nonvolatile memory cells assigned to one unit in an erase operation, a first write process of performing writing to the nonvolatile memory cell exceeding a pre-write-back level before a depletion level, and a second write process of performing writing to the nonvolatile memory cell exceeding a write-back level after the first write process. Since the occurrence of depletion is suppressed by successively performing the first write process with respect to the nonvolatile memory cells which may exceed the depletion level in the erase process, erasing can be performed to the nonvolatile memory cell without causing depletion halfway therethrough.Type: GrantFiled: January 24, 2007Date of Patent: June 24, 2008Assignee: Renesas Technology Corp.Inventors: Ken Matsubara, Yoshinori Takase, Tomoyuki Fujisawa
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Patent number: 7391656Abstract: A memory reading apparatus transfers digital data from a memory array that is independent of external clocking rate, where the data transmission time is not limited by the external clock period, and the internal timing of controls permits flexible column selection and no conflicts in the timing between external clock signals and internal bit line sensing ready signal. The memory read apparatus has a data read path circuit and a memory read control apparatus. The data read path circuit is in communication with the memory to acquire the selected data read from the memory, synchronize the selected data, and transfer the selected data from the memory. The memory read control apparatus is in communications with the data read path circuit for selecting the data to be read from the memory, for providing self-feedback signals for synchronizing the selected data for transfer from the memory.Type: GrantFiled: July 25, 2006Date of Patent: June 24, 2008Assignee: Etron Technology, Inc.Inventors: Ming Hung Wang, Jeng-Tzong Shih
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Patent number: 7391657Abstract: A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an intermediate data buffer for intermediately storing write data and, optionally, write data mask bits to be written to a memory cell array; a memory core having a bank organized memory cell array; a decoder section for decoding an address derived from a signal frame received from the reception interface section for writing/reading data in/from one or more memory banks of the memory cell array in accordance with a write/read command within one or more received signal frames; and a frame decoder provided as an interface between the reception interface section and the memory core for decoding one or more commands included in one or more frames and outputting data addresses, command, and read/write access indication signals to the memory core and to the intermediate data buffer.Type: GrantFiled: May 22, 2007Date of Patent: June 24, 2008Assignee: Infineon Technologies AGInventors: Paul Wallner, Martin Streibl, Manfred Menke, Yukio Fukuzo, Christian Sichert, Peter Gregorius
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Patent number: 7391658Abstract: An internal voltage generator maintains stable level of an internal voltage without increasing physical area. The internal voltage generator includes an active level detector for detecting a level of an internal voltage by comparing the level of the internal voltage and a level of a reference voltage to thereby output a first active driving signal, a first active driver for providing the internal voltage in response to the first active driving signal, a driving time controller for generating a time driving signal activated for a predetermined time, an active driving controller for activating a second active driving signal while the time driving signal is activated and for outputting the first active driving signal as the second active driving signal while the time driving signal is inactivated, and a second active driver for providing the internal voltage in response to the second active driving signal.Type: GrantFiled: October 4, 2007Date of Patent: June 24, 2008Assignee: Hynix Semiconductor Inc.Inventor: Chang-Ho Do
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Patent number: 7391659Abstract: A memory cell is programmed by injecting charge into a charge storage layer of the memory cell. A desired programmed charge results in the charge storage layer over an edge portion of a channel region of the memory cell. An undesired programmed charge results in the charge storage layer over an inner portion of the channel region. Charge tunneling is used to substantially remove the undesired programmed charge in the charge storage layer. In one form the memory cell has a substrate having a channel region, a first dielectric layer over the substrate and a charge storage layer over the first dielectric layer. A second dielectric layer over the charge storage layer has a first portion that is thicker than a second portion to selectively control the charge tunneling.Type: GrantFiled: January 27, 2006Date of Patent: June 24, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Craig T. Swift, Gowrishankar L. Chindalore
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Patent number: 7391660Abstract: An address path circuit with a row redundant scheme may include an address buffer for buffering an external address to output an internal address, a command buffer for buffering a plurality of external commands, a pre-latch unit for pre-latching the internal address from the address buffer using a specific one of the commands buffered by the command buffer to output a pre-latched internal address, a detector for detecting whether the pre-latched internal address from the pre-latch unit is a repaired address or normal address and outputting one or more detection signals as a result of the detection, an address latch unit for latching the internal address from the address buffer synchronously with a buffered clock to output a latched internal address, and a global address generator for receiving the detection signals from the detector and the latched internal address from the address latch unit and generating a global row address.Type: GrantFiled: July 18, 2006Date of Patent: June 24, 2008Assignee: Hynix Semiconductor Inc.Inventor: Cheul Hee Koo
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Patent number: 7391661Abstract: A memory is organized with many memory subspaces (db<i>) each including their own read-out circuit (SA<i>). At least one redundant column (Blred) is provided within each subspace in order to compensate for at least one defective column of said subspace. A memory controller is provided for interacting with the memory via a write bus (TD) and a read bus (Q). The memory controller generates a signal (TD<i>) for enabling the redundant column. This signal is provided so as to be conveyed to the read-out circuits of the memory to which the write bus (TD) is connected. Thus, one enables, via the read-out circuits, the redundant column of the memory subspaces which are associated with a defective column address.Type: GrantFiled: July 11, 2006Date of Patent: June 24, 2008Assignee: STMicroelectronics S.A.Inventor: Cyrille Dray
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Patent number: 7391662Abstract: A semiconductor device has a memory cell, decoders, a redundancy circuit and a mode setting circuit. The memory cell array has word lines including a redundant word line, bit lines and memory cells. A row decoder selects the word lines in response to a row address. Further, the row address decoder selects the redundant word line when a replacement signal is received. A column decoder selects the bit lines in response to a column address. A row address redundancy circuit stores a redundant row address. The row address redundancy circuit provides the replacement signal when the redundant row address corresponds to the received address. The mode setting circuit receives a mode signal having a normal mode and a test mode. The mode setting circuit outputs the replacement signal to the row decoder when the mode signal is in the normal mode, and prohibits an output of the replacement signal.Type: GrantFiled: April 23, 2007Date of Patent: June 24, 2008Assignee: Oki Electric Industry Co., Ltd.Inventor: Koji Kuroki