Patents Issued in July 10, 2008
  • Publication number: 20080164454
    Abstract: A phase change memory device is provided. The phase change memory device includes a substrate with a first electrode layer formed thereon. A first phase change memory structure is on the first electrode layer and electrically connected to the first electrode layer. A second phase change memory structure is on the first phase change memory structure and electrically connected to the first phase change memory structure, wherein the first or second phase change memory structure includes a cup-shaped heating electrode. A first insulating layer covers a portion of the cup-shaped heating electrode along a first direction. A first electrode structure covers a portion of the first insulating layer and the cup-shaped heating electrode along a second direction. The first electrode structure includes a pair of phase change material sidewalls on a pair of sidewalls of the first electrode structure and covering a portion of the cup-shaped heating electrode.
    Type: Application
    Filed: May 7, 2007
    Publication date: July 10, 2008
    Inventor: Wei-Su Chen
  • Publication number: 20080164455
    Abstract: A memory element comprises a first number of electrodes and a second number of electrically conducting channels between sub-groups of two of said electrodes, the channels exhibiting an electrical resistance that is reversibly switchable between different states, wherein the first number is larger than two and the second number is larger than the first number divided by two. The electrically conducting channels may be provided in transition metal oxide material, which exhibits a reversibly switchable resistance that is attributed to a switching phenomenon at the interfaces between the electrodes and the transition metal oxide material.
    Type: Application
    Filed: March 12, 2008
    Publication date: July 10, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Santos F. Alvarado, Johannes Georg Bednorz, Gerhard Ingmar Meijer
  • Publication number: 20080164456
    Abstract: Methods and apparatus for providing a resistance variable memory device with agglomeration prevention and thermal stability. According to one embodiment, a resistance variable memory device is provided having at least one tin-chalcogenide layer proximate at least one chalcogenide glass layer. The invention also relates to methods of forming such a memory device.
    Type: Application
    Filed: February 1, 2008
    Publication date: July 10, 2008
    Applicant: Micron Technology, Inc.
    Inventor: Kristy A. Campbell
  • Publication number: 20080164457
    Abstract: A semiconductor light emitting element comprising: a plurality of light-emitting-layer forming portions each of which includes a pn junction capable of emitting light of a certain wavelength, and which are separated from one another with a translucent resin formed on the side portions of the light-emitting-layer forming portions; a metal film disposed on first surfaces of the light-emitting-layer forming portions; a conductive substrate bonded to the metal film; a lower electrode formed on a surface of the conductive substrate, the surface being opposite to the surface to which the metal film is bonded; a transparent electrode which is connected to second surfaces, opposite to the first surfaces, of the light-emitting-layer forming portions, and which is substantially transparent to the certain wavelength; and an upper electrode formed above the second surfaces of the light-emitting-layer forming portions with the transparent electrode sandwiched in between.
    Type: Application
    Filed: December 20, 2007
    Publication date: July 10, 2008
    Inventors: Chisato Furukawa, Takafumi Nakamura
  • Publication number: 20080164458
    Abstract: A sapphire substrate includes a generally planar surface having a crystallographic orientation selected from the group consisting of a-plane, r-plane, m-plane, and c-plane orientations, and having a nTTV of not greater than about 0.037 ?m/cm2, wherein nTTV is total thickness variation normalized for surface area of the generally planar surface, the substrate having a diameter not less than about 9.0 cm.
    Type: Application
    Filed: December 21, 2007
    Publication date: July 10, 2008
    Applicant: SAINT-GOBAIN CERAMICS & PLASTICS, INC.
    Inventors: Brahmanandam V. Tanikella, Matthew A. Simpson, Palaniappan Chinnakaruppan, Robert A. Rizzuto, Ramanujam Vedantham
  • Publication number: 20080164459
    Abstract: A method and system for using a method of pre-equilibrium ballistic charge carrier refraction comprises fabricating one or more solid-state electric generators. The solid-state electric generators include one or more of a chemically energized solid-state electric generator and a thermionic solid-state electric generator. A first material having a first charge carrier effective mass is used in a solid-state junction. A second material having a second charge carrier effective mass greater than the first charge carrier effective mass is used in the solid-state junction. A charge carrier effective mass ratio between the second effective mass and the first effective mass is greater than or equal to two.
    Type: Application
    Filed: June 14, 2007
    Publication date: July 10, 2008
    Inventors: Anthony C. Zuppero, Jawahar M. Gidwani
  • Publication number: 20080164460
    Abstract: An organic semiconductor light-emitting device having the form of a field-effect transistor and a display using this device is provided. In the device, electrons and holes can be transported. The device comprises an organic semiconductor light-emitting layer capable of emitting light by recombination of holes and electrons, a hole injection electrode for injecting holes into the organic semiconductor light-emitting layer, an electron injection electrode for injecting electrons into the organic semiconductor light-emitting layer, and a gate electrode so disposed as to be opposed to the organic semiconductor light-emitting layer between the electrodes. When a control voltage is applied to the gate electrode, the carrier distribution in the organic semiconductor light-emitting layer is controlled. Thus, the light emission can be turned on/off and the emission intensity can be modulated.
    Type: Application
    Filed: August 26, 2005
    Publication date: July 10, 2008
    Applicants: Kyoto University, Pioneer Corporation, Hitachi, Ltd., Rohm Co., Ltd.
    Inventors: Takahito Oyamada, Hiroyuki Uchiuzo, Chinaya Adachi
  • Publication number: 20080164461
    Abstract: An organic transistor comprising source and drain electrodes; a gate electrode; an organic insulating layer between the gate electrode and the source and drain electrodes; and an organic semiconductive region between the insulating layer and the source and drain electrodes; wherein the organic semiconductive region comprises (a) a high mobility layer of an organic semiconductor and (b) a blocking layer of organic material positioned between the high mobility layer and the source and drain electrodes, in which the ionization potential of the organic material of the blocking layer exceeds the workfunction of the source and drain electrodes so as to inhibit charge injection from the source electrode into the blocking layer in the off-state.
    Type: Application
    Filed: October 12, 2005
    Publication date: July 10, 2008
    Applicant: CAMBRIDGE DISPLAY TECHNOLOGY LIMITED
    Inventor: Richard Wilson
  • Publication number: 20080164462
    Abstract: A light emitting device includes: a first substrate; a second substrate; a light emitting unit interposed between the first substrate and the second substrate; and a sealing material bonding the first substrate to the second substrate and sealing the light emitting unit. The sealing material comprises V+4. In addition, a glass frit, a composition for forming a sealing material, and a method of manufacturing a light emitting device using the composition for forming a sealing material are provided to obtain the light emitting device. The sealing material of the light emitting device can be easily formed by coating and irradiation of electro-magnetic waves, so that manufacturing costs are low and deterioration of the light emitting unit occurring when sealing material is formed can be substantially prevented. The sealing material has good sealing properties and thus a light emitting device including the sealing material has a long lifetime.
    Type: Application
    Filed: April 30, 2007
    Publication date: July 10, 2008
    Applicant: SAMSUNG SDI CO., LTD.
    Inventors: Seung-Han Lee, Jong-Seo Choi, Jin-Hwan Jeon, Sang-Wook Sin
  • Publication number: 20080164463
    Abstract: A manufacturing method of a thin film transistor made of a stack of an organic semiconductor layer, a gate insulating film and a gate electrode in this order on a substrate, which includes the steps of pattern coating a gate electrode material on the gate insulating film by printing; and carrying out a heat treatment to form the gate electrode resulting from drying for solidification of the pattern coated gate electrode material.
    Type: Application
    Filed: May 10, 2007
    Publication date: July 10, 2008
    Applicant: SONY CORPORATION
    Inventors: Noriyuki Kawashima, Kazumasa Nomoto, Akihiro Nomoto
  • Publication number: 20080164464
    Abstract: The invention provides a semiconductor device where data can be written after the production and forgery caused by rewriting of data can be prevented, and which can be manufactured at a low cost using a simple structure and an inexpensive material. Further, the invention provides a semiconductor device having the aforementioned functions, where wireless communication is not blocked by the internal structure. The semiconductor device of the invention has an organic memory provided with a memory cell array including a plurality of memory cells, a control circuit for controlling the organic memory, and a wire for connecting an antenna. Each of the plurality of memory cells has a transistor and a memory element. The memory element has a structure where an organic compound layer is provided between a first conductive layer and a second conductive layer. The second conductive layer is formed in a linear shape.
    Type: Application
    Filed: November 21, 2005
    Publication date: July 10, 2008
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Kiyoshi Kato
  • Publication number: 20080164465
    Abstract: The electronic device comprises an organic semiconductor material in a monodomain structure on a substrate. Said semiconductor material is preferably part of a transistor, wherein the monodomain extends on the channel, i.e. from a source to a drain electrode. The material comprises a mesogenic unit with spacer groups and end groups. The end groups are preferably reactive, i.e. dienes, acrylates, oxetanes or the like. The mesogenic unit contains a central oligothiophenyl-group, rigid spacer groups, particularly acetylenes, and additional groups, for instance thiophenyl or phenyl.
    Type: Application
    Filed: February 15, 2006
    Publication date: July 10, 2008
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS, N.V.
    Inventors: Albert Jose Jan Marie Van Breemen, Peter Tobias Herwig, Jorgen Sweelssen, Caecilia Hendrina Theodora Chlon, Harmannus Franciscus Maria Schoo, Dago De Leeuw, Sepas Setayesh, Wilhelmina Maria Hardeman
  • Publication number: 20080164466
    Abstract: The present invention relates to a sol-gel deposition/heat treatment process, which consistently produces polycrystalline direct bandgap semiconductor, e.g. ZnO, thin films exhibiting a photo luminescent (PL) spectrum at room temperature that is dominated by a single peak, e.g. in the ultraviolet part of the spectrum, in which the PL intensity of the bandgap emission is more than approximately 40 times greater than any deep-level defect emission peak or band. The present invention incorporates such direct bandgap semiconductor, e.g. ZnO, polycrystalline thin films produced by the method of the present invention into electro-luminescent devices that exhibit similarly high ratios of bandgap/deep-level defect emission intensity.
    Type: Application
    Filed: January 9, 2008
    Publication date: July 10, 2008
    Inventors: Brian Rioux, Jean-Paul Noel
  • Publication number: 20080164467
    Abstract: A semiconductor light emitting device manufacture method is provided which can manufacture a semiconductor light emitting device of high quality. A first substrate of an n-type ZnO substrate is prepared. A lamination structure including an optical emission layer made of ZnO based compound semiconductor is formed on the first substrate. A p-side conductive layer is formed on the lamination structure. A first eutectic material layer made of eutectic material is formed on the p-side conductive layer. A second eutectic material layer made of eutectic material is formed on a second substrate. The first and second eutectic material layers are eutectic-bonded to couple the first and second substrates. After the first substrate is optionally thinned, an n-side electrode is formed on a partial surface of the first substrate.
    Type: Application
    Filed: February 3, 2008
    Publication date: July 10, 2008
    Inventors: Michihiro Sano, Hiroyuki Kato, Naochika Horio
  • Publication number: 20080164468
    Abstract: Reinforced semiconductor structures are provided. An exemplary embodiment of a reinforced semiconductor structure comprises a semiconductor wafer comprising a plurality of dielectric layers formed thereon. At least one scribe line region is defined over the semiconductor wafer, separating the semiconductor wafer with at least two active regions thereover. A plurality of first non-dielectric pillars are formed in the topmost layer of the dielectric layers in the scribe line region and surround the test pad along a periphery. A plurality of second non-dielectric pillars and first vias are formed in a first low-k dielectric layer underlying the topmost low-k layer in the scribe line region, wherein the second non-dielectric pillars electrically connect the first non-dielectric pillars by the first vias, respectively.
    Type: Application
    Filed: January 4, 2007
    Publication date: July 10, 2008
    Inventors: Hsien-Wei Chen, Shih-Hsun Hsu
  • Publication number: 20080164469
    Abstract: A semiconductor device includes pads disposed in a chip region of a semiconductor substrate and line patterns disposed in a scribe region of the semiconductor substrate and extending toward the pads. The line patterns each have a line-width that is less than a predetermined distance between adjacent pads. Thus, respective interconnection lines connected to the pads are not short-circuited to each-other through the line patterns in the remaining scribe region after the chip region is sawed into a semiconductor chip.
    Type: Application
    Filed: December 26, 2007
    Publication date: July 10, 2008
    Inventors: Myoung-soo Kim, Yong-chan Kim
  • Publication number: 20080164470
    Abstract: A TFT array substrate and a manufacturing method thereof, where the TFT array substrate includes a substrate; a gate line and a gate electrode integrated therewith, which are covered by a gate insulating layer, a semiconductor layer, and a ohmic contact layer sequentially. An insulating layer is formed on the resulting substrate and on both sides of the gate line and the gate electrode, the gate insulating layer, the semiconductor layer, and the ohmic contact layer. A trench is then formed in the ohmic contact layer to divide the ohmic contact layer over the semiconductor layer. A data line and first and second source/drain electrodes are then formed on the insulating layer and the ohmic contact layer.
    Type: Application
    Filed: December 18, 2007
    Publication date: July 10, 2008
    Applicant: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zhangtao WANG, Haijun Qiu, Tae Yup Min, Seung Moo Rim
  • Publication number: 20080164471
    Abstract: A thin film transistor substrate that has reduced production cost and defect rate is presented. The thin film transistor substrate includes a gate wiring line formed on an insulating substrate and including a gate electrode, a data wiring line formed on the gate wiring line and including a source electrode and a drain electrode, a passivation layer pattern formed on parts of the data wiring line other than the drain electrode and a pixel region, and a pixel electrode electrically connected to the drain electrode. The pixel electrode includes zinc oxide.
    Type: Application
    Filed: November 13, 2007
    Publication date: July 10, 2008
    Inventors: Jong-hyun Choung, Byeong-Jin Lee, Hong-sick Park, Sun-young Hong, Bong-kyun Kim, Won-suk Shin
  • Publication number: 20080164472
    Abstract: A method of patterning a transparent conductive film adaptive for selectively etching a transparent conductive film without any mask processes, a thin film transistor for a display device using the same and a fabricating method thereof are disclosed. In the method of patterning the transparent conductive film, an inorganic material substrate is prepared. An organic material pattern is formed at a desired area of the inorganic material substrate. A thin film having a different crystallization rate depending upon said inorganic material and said organic material is formed. The thin film is selectively etched in accordance with said crystallization rate.
    Type: Application
    Filed: November 29, 2007
    Publication date: July 10, 2008
    Inventors: Byung Chul Ahn, Byoung Ho Lim, Byeong Dae Choi
  • Publication number: 20080164473
    Abstract: The present invention provides an image display unit integrated with a photo-sensor, comprising a photo-sensing element with high sensitivity and low noise and a polycrystalline silicon TFT prepared at the same time on an insulating substrate using planer process. After a first electrode 11 and a second electrode 12 of the photo-sensing element are made of polycrystalline silicon film, a light receiving layer (photoelectric conversion layer) 13 of the photo-sensing element is prepared by amorphous silicon film on upper layer. In this case, a polycrystalline silicon TFT is prepared at the same time.
    Type: Application
    Filed: December 12, 2007
    Publication date: July 10, 2008
    Inventors: Mitsuharu Tai, Toshio Miyazawa
  • Publication number: 20080164474
    Abstract: A display device in which variations in luminance due to variations in characteristics of transistors are reduced, and image quality degradation due to variations in resistance values is prevented. The invention comprises a transistor whose channel portion is formed of an amorphous semiconductor or an organic semiconductor, a connecting wiring connected to a source electrode or a drain electrode of the transistor, a light emitting element having a laminated structure which includes a pixel electrode, an electro luminescent layer, and a counter electrode, an insulating layer surrounding an end portion of the pixel electrode, and an auxiliary wiring formed in the same layer as a gate electrode of the transistor, a connecting wiring, or the pixel electrode. Further, the connecting wiring is connected to the pixel electrode, and the auxiliary wiring is connected to the counter electrode via an opening portion provided in the insulating layer.
    Type: Application
    Filed: March 7, 2008
    Publication date: July 10, 2008
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Publication number: 20080164475
    Abstract: A method of forming polysilicon, a thin film transistor (TFT) using the polysilicon, and a method of fabricating the TFT are disclosed. The method of forming the polysilicon comprises: forming an insulating layer on a substrate; forming a first electrode and a second electrode on the insulating layer; forming at least one heater layer on the insulating layer so as to connect the first electrode and the second electrode; forming an amorphous material layer containing silicon on the heater layer(s); forming a through-hole under the heater layer(s) by etching the insulating layer; and crystallizing the amorphous material layer into a polysilicon layer by applying a voltage between the first electrode and the second electrode so as to heat the heater layer(s).
    Type: Application
    Filed: August 3, 2007
    Publication date: July 10, 2008
    Inventors: Jun-Hee Choi, Andrei Zoulkarneev
  • Publication number: 20080164476
    Abstract: Provided are a method of manufacturing a transparent N-doped p-type ZnO semiconductor layer using a surface chemical reaction between precursors containing elements constituting thin layers, and a thin film transistor (TFT) including the p-type ZnO semiconductor layer. The method includes the steps of: preparing a substrate and loading the substrate into a chamber; injecting a Zn precursor and an oxygen precursor into the chamber, and causing a surface chemical reaction between the Zn precursor and the oxygen precursor using an atomic layer deposition (ALD) technique to form a ZnO thin layer on the substrate; and injecting a Zn precursor and an nitrogen precursor into the chamber, and causing a surface chemical reaction between the Zn precursor and the nitrogen precursor to form a doping layer on the ZnO thin layer.
    Type: Application
    Filed: January 8, 2008
    Publication date: July 10, 2008
    Inventors: Sang Hee PARK, Chi Sun HWANG, Hye Yong CHU, Jeong Ik LEE
  • Publication number: 20080164477
    Abstract: A thin film transistor, a method of fabricating the same, and a flat panel display device including the same, are provided. According to the method, low resistance regions and high resistance regions can be manufactured through one doping process. The thin film transistor includes: a substrate; a semiconductor layer disposed on the substrate and including source and drain regions, high resistance regions smaller than the source and drain regions, a channel region, and connection regions disposed between the high resistance regions and the channel region; a gate insulating layer disposed on the semiconductor layer; a gate electrode disposed on the gate insulating layer above the channel region; an interlayer insulating layer disposed on the gate electrode; and source and drain electrodes disposed on the interlayer insulating layer and electrically connected to the source and drain regions, respectively.
    Type: Application
    Filed: January 8, 2008
    Publication date: July 10, 2008
    Inventor: Jong-Hyun Choi
  • Publication number: 20080164478
    Abstract: In manufacturing a semiconductor device, static electricity is generated while contact holes are formed in an interlayer insulating film by dry etching. Damage to a pixel region or a driving circuit region due to travel of the static electricity generated is prevented. Gate signal lines are spaced apart from each other above a crystalline semiconductor film. Therefore a first protective circuit is not electrically connected when contact holes are opened in an interlayer insulating film. The static electricity generated during dry etching for opening the contact holes moves from the gate signal line, damages a gate insulating film, passes the crystalline semiconductor film, and again damages the gate insulating film before it reaches the gate signal line. As the static electricity generated during the dry etching damages the first protective circuit, the energy of the static electricity is reduced until it loses the capacity of damaging a driving circuit TFT.
    Type: Application
    Filed: December 17, 2007
    Publication date: July 10, 2008
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Satoshi Murakami, Yosuke Tsukamoto, Tomoaki Atsumi, Masayuki Sakakura
  • Publication number: 20080164479
    Abstract: A semiconductor device including polysilicon (poly-Si) and method of manufacturing the same are provided. The semiconductor device includes a TaNx material layer and a poly-Si layer formed on the TaNx material layer. The semiconductor device including poly-Si may be manufactured by forming a TaNx material layer and forming a poly-Si layer by depositing silicon formed on the TaNx material layer and annealing silicon.
    Type: Application
    Filed: December 11, 2007
    Publication date: July 10, 2008
    Inventors: Wenxu Xianyu, Jung-hyun Lee, Hyung-Jin Bae, Young-soo Park
  • Publication number: 20080164480
    Abstract: A method for fabrication of a semiconductor device on a substrate, the semiconductor having a wafer. The method includes the steps:(a) applying a seed layer of a thermally conductive metal to the wafer; (b) electroplating a relatively thick layer of the conductive metal on the seed layer, and(c) removing the substrate. A corresponding semiconductor device is also disclosed.
    Type: Application
    Filed: September 19, 2003
    Publication date: July 10, 2008
    Inventors: Xuejun Kang, Daike Wu, Edward Robert Perry, Shu Yuan
  • Publication number: 20080164481
    Abstract: An image display apparatus with an illuminance sensor, where the packaging cost, mechanical reliability due to packaging, and product yield are maintained. In the same semiconductor film as a thin-film-transistor (TFT) consisting of a pixel formed over an insulating substrate constituting a pixel, plural photo-sensors composed of a TFT for detecting light which has different detecting wavelength bands, and a signal processing circuit for generating a signal which controls the brightness of the pixel on the basis of the output of the photo-sensor are formed. The photo-sensor detects light energy of different wavelength bands by using a filter having a different film thickness of the semiconductor film or a different light transmission band. Ambient illuminance is detected by processing the output of each sensor in the signal processing circuit. The detected signal is fed back to the brightness control of the pixel.
    Type: Application
    Filed: December 5, 2007
    Publication date: July 10, 2008
    Inventors: Mitsuharu Tai, Hiroshi Kageyama
  • Publication number: 20080164482
    Abstract: In a light emitting apparatus that includes a plurality of semiconductor light emitting devices 2 each having a light emitting face covered with a phosphor layer 3, a semiconductor assembly obtained by assembling a submount and the semiconductor light emitting devices is mounted on the substrate. Accordingly, chromaticity characteristics of the semiconductor assembly can be measured before the semiconductor assembly is mounted on the substrate. Therefore, even if using a plurality of semiconductor light emitting devices, a semiconductor assembly can be prepared on which the semiconductor light emitting devices each having uniform chromaticity characteristics are mounted before the semiconductor assembly is mounted on the substrate. And, a light emitting apparatus having suppressed dispersion of chromaticity can be manufactured.
    Type: Application
    Filed: April 27, 2005
    Publication date: July 10, 2008
    Inventors: Kunihiko Obara, Toshihide Maeda, Tadashi Yano, Noriyasu Tanimoto
  • Publication number: 20080164483
    Abstract: An active matrix substrate includes a glass substrate, a driver portion formed on the glass substrate in a protruding state, a stepped portion formed along a surface of the driver portion and a surface of the glass substrate, an insulating reentrant-angle compensating film formed on a surface of the stepped portion, for compensating for at least a part of a reentrant-angle shape of the stepped portion, and a wiring layer formed along a surface of the reentrant-angle compensating film and connected to the driver portion.
    Type: Application
    Filed: March 9, 2006
    Publication date: July 10, 2008
    Inventors: Kazuhide Tomiyasu, Yutaka Takafuji, Masao Moriguchi
  • Publication number: 20080164484
    Abstract: The present invention provides a light emitting apparatus comprising a three-color light emitting device unit including at least three light emitting diode (LED) chips for respectively emitting red, green and blue light; a white light emitting device unit including at least one blue LED chip with a fluorescent substance formed thereon; and a substrate provided with a first electrode connected in common to ends of the LED chips and second electrodes formed to correspond respectively to the LED chips.
    Type: Application
    Filed: March 8, 2006
    Publication date: July 10, 2008
    Applicant: SEOUL SEMICONDUCTOR CO., LTD.
    Inventor: Jae Hong Lee
  • Publication number: 20080164485
    Abstract: Disclosed are a light emitting device having a plurality of light emitting cells connected in series and a method of fabricating the same. The light emitting device includes a buffer layer formed on a substrate. A plurality of rod-shaped light emitting cells are located on the buffer layer to be spaced apart from one another. Each of the light emitting cells has an n-layer, an active layer and a p-layer. Meanwhile, wires connect the spaced light emitting cells in series or parallel. Accordingly, arrays of the light emitting cells connected in series are connected to be driven by currents flowing in opposite directions. Thus, there is provided a light emitting device that can be directly driven by an AC power source.
    Type: Application
    Filed: July 4, 2005
    Publication date: July 10, 2008
    Applicant: SEOUL OPTO DEVICE CO., LTD.
    Inventor: Chung Hoon Lee
  • Publication number: 20080164486
    Abstract: A semiconductor light emitting device including: a substrate made of GaAs; and a semiconductor layer formed on the substrate, in which part of the substrate on a side opposite to the semiconductor layer is removed by etching so that the semiconductor light emitting device has a thickness of not more than 60 ?m.
    Type: Application
    Filed: January 4, 2008
    Publication date: July 10, 2008
    Applicant: ROHM CO., LTD.
    Inventors: Tadahiro Hosomi, Kentaro Mineshita
  • Publication number: 20080164487
    Abstract: A ceramic light emitted diode (LED) package has a pair of discrete reflection walls to reflect light emission from the LED. With two opposite reflection walls and two opposite openings around the LED, light emitted from the LED package can be fanned out.
    Type: Application
    Filed: February 15, 2007
    Publication date: July 10, 2008
    Applicant: LEDTECH ELECTRONICS CORP.
    Inventors: Hsin-Chun LIU, Yao-I WANG, Chih-Liang SU, Fang-Po WANG
  • Publication number: 20080164488
    Abstract: A second electrode (16) formed on a second main surface of a compound semiconductor layer (100) of a light emitting element (1) is arranged in contact with the second main surface of the compound semiconductor layer (100) and has a junction alloying layer (31) for reducing the resistance due to the junction with said compound semiconductor layer (100) and a solder layer (34) for connecting said junction metal layer to an electoconductive support (52).
    Type: Application
    Filed: January 26, 2006
    Publication date: July 10, 2008
    Applicant: Shin- Etsu Handotai Co., Ltd
    Inventors: Hitoshi Ikeda, Masayoshi Obara
  • Publication number: 20080164489
    Abstract: A method of device growth and p-contact processing that produces improved performance for non-polar III-nitride light emitting diodes and laser diodes. Key components using a low defect density substrate or template, thick quantum wells, a low temperature p-type III-nitride growth technique, and a transparent conducting oxide for the electrodes.
    Type: Application
    Filed: December 11, 2007
    Publication date: July 10, 2008
    Applicants: The Regents of the University of California, Japan Science and Technology Agency
    Inventors: Mathew C. Schmidt, Kwang Choong Kim, Hitoshi Sato, Steven P. DenBaars, James S. Speck, Shuji Nakamura
  • Publication number: 20080164490
    Abstract: The power semiconductor device with a four-layer npnp structure can be turned-off via a gate electrode. The first base layer comprises a cathode base region adjacent to the cathode region and a gate base region adjacent to the gate electrode, but disposed at a distance from the cathode region. The gate base region has the same nominal doping density as the cathode base region in at least one first depth, the first depth being given as a perpendicular distance from the side of the cathode region, which is opposite the cathode metallization. The gate base region has a higher doping density than the cathode base region and/or the gate base region has a greater depth than the cathode base region in order to modulate the field in blocking state and to defocus generated holes from the cathode when driven into dynamic avalanche.
    Type: Application
    Filed: January 16, 2008
    Publication date: July 10, 2008
    Applicant: ABB Technology AG
    Inventors: Munaf Rahimo, Peter Streit
  • Publication number: 20080164491
    Abstract: While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.
    Type: Application
    Filed: January 4, 2007
    Publication date: July 10, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yaocheng Liu, Dureseti Chidambarrao, Oleg Gluschenkov, Judson R. Holt, Renee T. Mo, Kern Rim
  • Publication number: 20080164492
    Abstract: A process for preparing a semiconductor wafer with a strained layer having an elevated critical thickness.
    Type: Application
    Filed: February 29, 2008
    Publication date: July 10, 2008
    Inventors: Bruno Ghyselen, Daniel Bensahel, Thomas Skotnicki
  • Publication number: 20080164493
    Abstract: Methods for electrodepositing germanium on various semiconductor substrates such as Si, Ge, SiGe, and GaAs are provided. The electrodeposited germanium can be formed as a blanket or patterned film, and may be crystallized by solid phase epitaxy to the orientation of the underlying semiconductor substrate by subsequent annealing. These plated germanium layers may be used as the channel regions of high-mobility channel field effect transistors (FETs) in complementary metal oxide semiconductor (CMOS) circuits.
    Type: Application
    Filed: January 5, 2007
    Publication date: July 10, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Hariklia Deligianni, Qiang Huang, Lubomyr T. Romankiw, Devendra K. Sadana, Katherine L. Saenger
  • Publication number: 20080164494
    Abstract: Embodiments of the invention provide a semiconductor device including a collector in an active region; a first and a second sub-collector, the first sub-collector being a heavily doped semiconductor material adjacent to the collector and the second sub-collector being a silicided sub-collector next to the first sub-collector; and a silicided reach-through in contact with the second sub-collector, wherein the first and second sub-collectors and the silicided reach-through provide a continuous conductive pathway for electrical charges collected by the collector from the active region. Embodiments of the invention also provide methods of fabricating the same.
    Type: Application
    Filed: January 5, 2007
    Publication date: July 10, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Francois Pagette, Christian Lavoie, Anna Topol
  • Publication number: 20080164495
    Abstract: A heterojunction bipolar transistor structure with self-aligned sub-lithographic extrinsic base region including a self-aligned metal-semiconductor alloy and self-aligned metal contacts made to the base is disclosed. The lateral dimension of the extrinsic base region is defined by the footprint of a sacrificial spacer, and its thickness is controlled by selective epitaxy. A self-aligned semiconductor-metal alloy and self-aligned metal contacts are made to the extrinsic base using a method compatible with conventional silicon processing.
    Type: Application
    Filed: January 10, 2007
    Publication date: July 10, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Guy M. Cohen, Francois Pagette
  • Publication number: 20080164496
    Abstract: When dummy patterns are arranged to planarize LSI layout patterns, a plurality of dummy patterns 1 are arranged in a wiring layer in which signal wiring patterns 2 are formed, so as to be inclined at an angle of generally 45 degrees toward the associated signal wiring patterns 2. These dummy patterns 1 cross signal wiring patterns 3 formed in another vertically adjacent wiring layer to have an inclination angle of generally 45 degrees. A plurality of dummy patterns 13 are located in the wiring layer in which the signal wiring patterns 3 are formed, so as to be inclined at an angle of generally 45 degrees toward the associated signal wiring patterns 3. The dummy patterns 1 formed in one of the adjacent wiring layers cross the dummy patterns 13 formed in the other wiring layer at an angle of generally 90 degrees. This reduces fluctuations in wiring capacitance and equalizes fluctuations in the wiring capacitance to the maximum extent.
    Type: Application
    Filed: March 3, 2006
    Publication date: July 10, 2008
    Inventor: Yoshiyuki Kawakami
  • Publication number: 20080164497
    Abstract: A circuit having a power transistor and drive circuit is disclosed. One embodiment provides a drive terminal and a load path. The power transistor is integrated in a first semiconductor body. A first sensor arrangement having a sensor transistor is integrated in the first semiconductor body. The sensor arrangement provides a first sensor signal dependent on a threshold voltage of the sensor transistor. A drive circuit to which the first sensor signal is supplied and designed to drive the power transistor via its drive terminal as a function of the first sensor signal.
    Type: Application
    Filed: January 3, 2008
    Publication date: July 10, 2008
    Applicant: INFINEON TECHNOLOGIES AG
    Inventor: Mathias von Borcke
  • Publication number: 20080164498
    Abstract: A method for forming a semiconductor device includes forming a gate dielectric over a substrate, forming a metal electrode over the gate dielectric, forming a first sacrificial layer which includes polysilicon or a metal over the metal electrode, removing the first sacrificial layer, and forming a gate electrode contact over and coupled to the metal electrode.
    Type: Application
    Filed: January 4, 2007
    Publication date: July 10, 2008
    Inventor: William J. Taylor
  • Publication number: 20080164499
    Abstract: A method of a CMOS image sensor is disclosed. A method of manufacturing a CMOS image sensor includes forming an epi layer formed over a semiconductor substrate including a pixel region and a peripheral region. At least one oxide film may be formed over the epi layer, including the peripheral region and an upper pad formed therein. A nitride film may be formed over the oxide film. A primary array etching process may be performed with respect to the nitride film using a first photoresist pattern for opening a main pixel region in the pixel region. A secondary array etching process may be performed with respect to the nitride film and the oxide film using a second photoresist pattern for opening the upper pad. The oxide film of the pixel region may be obliquely removed to a predetermined depth. A plurality of color filters and a plurality of micro lenses may be formed over the pixel region after the secondary array etching process.
    Type: Application
    Filed: December 21, 2007
    Publication date: July 10, 2008
    Inventors: Ki-Sik Im, Woo Seok Hyun
  • Publication number: 20080164500
    Abstract: A solid-state image sensing device includes a plurality of pixels. Each pixel has a photodiode, a first transistor, and a second transistor. The photodiode is constituted by a first-conductivity-type semiconductor region and a second-conductivity-type semiconductor region. The first and second conductivity types are opposite to each other. The first transistor has a first-conductivity-type drain region formed in the second-conductivity-type semiconductor region to transfer signal charge to the drain region. The second transistor has a source region and a drain region which are formed in the second-conductivity-type semiconductor region and which have the first conductivity type. At least one second-conductivity-type potential barrier is provided under the drain region of the first transistor and the source region and/or the drain region of the second transistor.
    Type: Application
    Filed: March 14, 2008
    Publication date: July 10, 2008
    Applicant: Canon Kabushiki Kaisha
    Inventors: Mahito Shinohara, Shunsuke Inoue
  • Publication number: 20080164501
    Abstract: An active pixel using a photodiode with multiple species of N type dopants is disclosed. The pixel comprises a photodiode formed in a semiconductor substrate. The photodiode is an N? region formed within a P-type region. The N? region is formed from an implant of arsenic and an implant of phosphorus. Further, the pixel includes a transfer transistor formed between the photodiode and a floating node and selectively operative to transfer a signal from the photodiode to the floating node. Finally, the pixel includes an amplification transistor controlled by the floating node.
    Type: Application
    Filed: March 18, 2008
    Publication date: July 10, 2008
    Applicant: OmniVision Technologies, Inc.
    Inventor: Howard E. Rhodes
  • Publication number: 20080164502
    Abstract: The present invention to provide a new technique to reduce a variation in switching field of a magnetization free layer in a magnetic memory. The magnetic memory according to the present invention includes a magnetization free layer including a ferromagnetic layer having a shape magnetic anisotropy in a first direction and a magnetic strain constant is positive; and a stress inducing structure configured to apply a tensile stress to said magnetization free layer in a same direction as the first direction.
    Type: Application
    Filed: November 16, 2005
    Publication date: July 10, 2008
    Applicant: NEC CORPORATION
    Inventors: Yoshiyuki Fukumoto, Tetsuhiro Suzuki, Katsumi Suemitsu
  • Publication number: 20080164503
    Abstract: A ferroelectric memory device and methods of forming the same are provided. Forming a ferroelectric device includes forming an insulation layer over a substrate having a conductive region, forming a bottom electrode electrically connected to the conductive region in the insulation layer, recessing the insulation layer, and forming a ferroelectric layer and an upper electrode layer covering the bottom electrode over the recessed insulation layer, The bottom electrode protrudes over an upper surface of the recessed insulation layer.
    Type: Application
    Filed: January 8, 2008
    Publication date: July 10, 2008
    Inventors: Suk-Hun Choi, Chang-Ki Hong, Jung-Hyeon Kim, Jun-Young Lee, Jong-Heun Lim, Seong-Kyu Yun