Abstract: A phase change memory device is provided. The phase change memory device comprises a substrate. An electrode layer is on the substrate. A phase change memory structure is on the electrode layer and electrically connected to the electrode layer, wherein the phase change memory structure comprises a cup-shaped heating electrode on the electrode layer. An insulating layer is on the cup-shaped heating electrode along a first direction covering a portion of the cup-shaped heating electrode. An electrode structure is on the cup-shaped heating electrode along a second direction covering a portion of the insulating layer and the cup-shaped heating electrode. A pair of double spacers is on a pair of sidewalls of the electrode structure covering a portion of the cup-shaped heating electrode, wherein the double spacer comprises a phase change material spacer and an insulating material spacer on a sidewall of the phase change material spacer.

Abstract: The present invention relates to a metal-oxide-semiconductor field-effect transistor (MOSFET) with electrostatic-discharge (ESD) protection and a voltage-stabilizing capacitor, and a method for manufacturing the same and is applied to a chip, including a P-type substrate, a conductor layer, a first N-type doping region, a second N-type doping region, and an N-type well. The conductor layer is coupled to the ground; the first N-type doping region is coupled to the power supply; the second N-type doping region is coupled to a VDD pad (power-supply pad). Thereby, when the chip is not installed or not operating, the MOSFET can be used for ESD protection. When the chip is operating, the conductor layer, the first N-type doping region, the second N-type doing region, and the N-type well form a gate capacitor as a voltage-stabilizing capacitor between the power supply and the ground. Hence, the objective of fully utilization is achieved. In addition, the chip size is saved and thus the cost thereof is reduced.

Abstract: A high voltage semiconductor device, such as a RESURF transistor, having improved properties, including reduced on state resistance. The device includes a semiconductor substrate; a source region and a drain region provided in the substrate; wherein the source region and the drain region are laterally spaced from each other; and a drift region in the substrate between the source region and the drain region. The drift region includes a structure having at least two spaced trench capacitors extending between the source region and the drain region; and further includes a stack having at least a first region of a first conductivity type, a second region of a second conductivity type, and a third region of the first conductivity type, wherein the stack extends between the source region and the drain region and between the at least first and second trench capacitors and in electrical connection to the first and second trench capacitors.

Abstract: An area-efficient gated diode includes a semiconductor layer of a first conductivity type, an active region of a second conductivity type formed in the semiconductor layer proximate an upper surface thereof, and at least one trench electrode extending vertically through the active region and at least partially into the semiconductor layer. A first terminal of the gated diode is connected to the trench electrode, and a second terminal is connected to the active region. The gated diode is operative in one of at least first an second modes as a function of a voltage potential applied between the first and second terminals. The first mode is characterized by the creation of an inversion layer in the semiconductor layer surrounding the trench electrode. The gated diode has a first capacitance in the first mode and a second capacitance in the second mode, the first capacitance being greater than the second capacitance.

Abstract: The memory device includes a first tunnel insulation layer pattern on a semiconductor substrate, a second tunnel insulation layer pattern having an energy band gap lower than that of the first tunnel insulation layer pattern on the first tunnel insulation layer pattern, a charge trapping layer pattern on the second tunnel insulation layer pattern, a blocking layer pattern on the charge trapping layer pattern, and a gate electrode on the blocking layer pattern. The memory device further includes a source/drain region at an upper portion of the semiconductor substrate, The upper portion of the semiconductor substrate is adjacent to the first tunnel insulation layer pattern.

Abstract: A nonvolatile memory device includes a semiconductor substrate of a first conductivity type, a plurality of word lines on the semiconductor substrate, each the plurality of word lines including a floating gate of a second conductivity type. A ground select line and a string select line are disposed on respective sides of word lines. An impurity region of the second conductivity type underlies a first word line adjacent the ground select line. The device may further include a second impurity region of the second conductivity type underlying a second word line adjacent the string select line. In still further embodiments, the device may further include third impurity regions of the second conductivity type underlying respective third word lines between the first word line and the second word line. Methods of forming such devices are also provided.

Abstract: A semiconductor memory device performing an erase operation using an erase gate and a method of manufacturing the same are provided. The memory device may include a charge trap layer storing a first charge transfer medium having a first polarity and at least one erase gate. The at least one erase gate may be formed below the charge trap layer. A second charge transfer medium, which has a second polarity opposite to the first polarity, may be stored in the at least one erase gate. During the erase operation, the second charge transfer medium migrates to the charge trap layer causing the first charge transfer medium to combine with the second charge transfer medium.

Abstract: A semiconductor device having spacer patterns formed at the sidewalls of gate electrodes and a method of fabricating the same are disclosed. The semiconductor device includes a gate pattern, including a plurality of gate electrodes, formed on a semiconductor substrate, a barrier insulation layer formed on the entire surface of the substrate including the gate pattern, and spacer patterns formed at opposite sidewall regions of the respective gate electrodes surrounded by the barrier insulation layer such that the spacer patterns have a height less than that of the respective gate electrodes.

Abstract: A semiconductor device has a semiconductor substrate that in turn has a top semiconductor layer portion and a major supporting portion under the top semiconductor layer portion. An interconnect layer is over the semiconductor layer. A memory array is in a portion of the top semiconductor layer portion and a portion of the interconnect layer. The memory is erased by removing at least a portion of the major supporting portion and, after the step of removing, applying light to the memory array from a side opposite the interconnect layer. The result is that the memory array receives light from the backside and is erased.

Abstract: The present invention relates to a memory device and a method of fabricating the same. The memory device comprises a substrate, a tunnel dielectric film on the substrate, pairs of source and drain regions formed in the substrate, and a number of separate storage blocks between each pair of the source and drain regions. Each storage wire block includes a storage medium and a silicon dioxide layer. Two storage blocks are separated by an interval of at least 100 angstroms.

Abstract: A semiconductor device includes an active region surrounded by an element isolation region; a gate electrode crossing the active region; and at least one slit provided at a boundary portion between the element isolation region and the active region and having a first region covered with the gate electrode and second region not covered with the gate electrode; wherein the first region of the slit is embedded with a conductive material which is the same as that of the gate electrode, and at least an upper part of a second region of the slit is embedded with an insulation material.

Abstract: A method for producing a power MOSFET. The method includes fabricating a plurality of layers of a power MOSFET to produce an upper surface active area and performing a chemical mechanical polishing process on the active area to produce a substantially planar surface. A metalization deposition process is then performed on the substantially planar surface and the fabrication of the power MOSFET is subsequently completed.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor device also includes a body layer extending a first predetermined distance into the semiconductor layer of the second conductivity type and a pair of trenches extending a second predetermined distance into the semiconductor layer of the second conductivity type. Each of the pair of trenches consists essentially of a dielectric material disposed therein and a concentration of doping impurities present in the semiconductor layer of the second conductivity type and a distance between the pair of trenches define an electrical characteristic of the semiconductor device. The semiconductor device further includes a control gate coupled to the semiconductor layer of the second conductivity type and a source region coupled to the semiconductor layer of the second conductivity type.

Abstract: A semiconductor device according to the present invention includes: a first trench that is formed in a semiconductor substrate; a gate oxide film that is formed on a surface of the first trench; and a trench gate electrode that is formed so as to bury the first trench via the gate oxide film. The semiconductor device also includes: a second trench that is formed in the semiconductor substrate with a width wider than the width of the first trench; and a terminal-embedded insulation layer that is formed so as to bury the second trench. The semiconductor device further includes: a third trench that is formed in the semiconductor substrate with a width wider than the width of the second trench; and a trench contact electrode that is formed so as to bury the third trench.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor layer of the second conductivity type is characterized by a first thickness. The semiconductor device includes a set of trenches having a predetermined depth and extending into the semiconductor layer of the second conductivity type, thereby defining interfacial regions disposed between the semiconductor layer of the second conductivity type and each of the trenches. The trenches comprises a distal portion consisting essentially of a dielectric material disposed therein and a proximal portion comprising the dielectric material and a gate material disposed interior to the dielectric material in the proximal portion of the trench. The semiconductor device further includes a source region coupled to the semiconductor layer of the second conductivity type.

Abstract: In accordance with an embodiment of the present invention, a FET is formed as follows. An exposed surface area of a silicon layer where silicon can be removed is defined. A portion of the silicon layer is removed to form a middle section of a trench extending into the silicon layer from the exposed surface area of the silicon layer. Additional exposed surface areas of the silicon layer where silicon can be removed are defined. Additional portions of the silicon layer are removed to form outer sections of the trench such that the outer sections of the trench extend into the silicon layer from the additional exposed surface areas of the silicon layer. The middle section of the trench extends deeper into the silicon layer than the outer sections of the trench.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a first surface and a second surface, a source region disposed on the first surface, a gate region disposed on the first surface adjacent the source region, and a drain region disposed on the first surface. The semiconductor device also includes a pair of charge control trenches disposed between the gate region and the drain region. Each of the pair of charge control trenches is characterized by a width and includes a first dielectric material disposed therein and a second material disposed internal to the first dielectric material. Additionally, a concentration of doping impurities present in the semiconductor layer of the first conductivity type and a distance between the pair of charge control trenches define an electrical characteristic of the semiconductor device that is independent of the width of each of the pair of charge control trenches.

Abstract: A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches in the termination region. The second plurality of trenches are with the dielectric material.

Abstract: To provide a semiconductor device that has a three dimensional gate dielectric film, is easily manufactured, and a gate structure thereof can be easily miniaturize. A semiconductor device comprises: a three-dimensional gate dielectric film formed on a semiconductor substrate; a gate electrode that contacts the gate dielectric film and protrudes from the semiconductor substrate; a source electrode and a drain electrode that are formed in a diffusion layer region of the semiconductor substrate around the gate dielectric film; a protective dielectric film that covers a top face of the semiconductor substrate around the gate electrode and a side face of the gate electrode protruding from the semiconductor substrate; and an inter-layer dielectric film that is laminated over the protective dielectric film.

Abstract: A dynamic random access memory cell and a manufacturing method thereof are provided. First, a substrate on which a bottom oxide layer and a semiconductor layer are formed is provided. The semiconductor layer is formed on the bottom oxide layer. Next, a gate is formed on the semiconductor layer. Then, the semiconductor layer is patterned to expose a portion of the bottom oxide layer. Afterwards, an insulation layer is formed at the side walls of the semiconductor layer, wherein the height of the insulation layer is shorter than that of the semiconductor layer, so that a gap is formed between the tops of the insulation layer and the semiconductor layer. Further, a doping layer covering the insulation layer and having the same height with the semiconductor layer is formed on the bottom oxide layer. The doping layer contacts the side walls of the semiconductor layer via the gap.

Abstract: The invention provides wiring, which can form or disconnect freely the adjacent exposure regions by employing the same optical mask under a condition that a plurality of array substrates are produced on one mother glass substrate; and an optical mask, which can be inspected by utilizing the same probe device for inspecting even though under a condition that the same mother glass substrate is used to produce the array substrates with different sizes; array substrates; and the manufacture method of the same.

Abstract: A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the structure of the second gate electrode is discontinuous with the structure of the landing pad.

Abstract: A method of trimming hard mask is provided. The method includes providing a substrate, a hard mask layer, and a tri-layer stack on the substrate. The tri-layer stack includes a top photo resist layer, a silicon photo resist layer, and a bottom photo resist layer. The top photo resist layer, the silicon photo resist layer, the bottom photo resist layer, and the hard mask layer are patterned sequentially. A trimming process is performed on the hard mask layer. The bottom photo resist layer of the present invention is thinner and loses some height in the etching process, so the bottom photo resist layer will not collapse.

Abstract: The semiconductor comprises a channel layer including GaN, a barrier layer formed by laminating a first layer including AlXGa1-XN (0.05?X?0.25) and a second layer including AlYGa1-YN (0.20?Y?0.28, X<Y), source and drain electrodes provided spaced apart from each other on the barrier layer, and a gate electrode provided on the bottom of a ditch extending between the source and drain electrodes and formed with a depth starting from the top surface of the barrier layer reaching the first layer adjacent to the channel layer.

Abstract: A lateral double-gate FET structure with sub-lithographic source and drain regions is disclosed. The sub-lithographic source and drain regions are defined by a sacrificial spacer. Self-aligned metal-semiconductor alloy and metal contacts are made to the sub-lithographic source and drain using conventional silicon processing.

Abstract: A semiconductor device having dual fully-silicided gate is provided, which includes a first transistor, a second transistor, a dielectric layer, and an interlayer insulating layer. The first transistor is disposed on the substrate, which includes a first silicided gate and a first source/drain. The second transistor is disposed on the substrate, which includes a second silicided gate and a second source/drain. The material of the first silicided gate is different from the material of the second silicided gate. The first silicided gate and the second silicided gate are formed in one silicidation process. The dielectric layer completely covers the first transistor and the second transistor. The interlayer insulating layer is disposed on the dielectric layer.

Abstract: Semiconductor devices with selective stress memory effect and fabrication methods thereof. The semiconductor device comprises a semiconductor substrate with a first region and a second region. Both the first region and the second region have a first doped region and a second doped region separated by an insulation layer. A PMOS transistor is disposed on the first doped region layer. An NMOS transistor is disposed on the second doped region. A first capping layer is disposed covering the NMOS transistor over the first region. A second capping layer is disposed covering the PMOS transistor over the first region. The thickness of the first capping layer is different from the thickness of the second capping layer, thereby different stress is induced on the PMOS transistor and the NMOS transistor respectively. The PMOS transistor and the NMOS transistor over the second region are silicided.

Abstract: A method for making a semiconductor device is provided by (a) providing a substrate (203) having first (205) and second (207) gate structures thereon; (b) forming an underlayer (231) over the first and second gate structures; (c) removing the underlayer from the first gate structure; (d) forming a first stressor layer (216) over the first and second gate structures; and (e) selectively removing the first stressor layer from the second gate structure through the use of a first etch which is selective to the underlayer.

Abstract: The present invention provides a semiconducting device including a gate region positioned on a mesa portion of a substrate; and a nitride liner positioned on the gate region and recessed surfaces of the substrate adjacent to the gate region, the nitride liner providing a stress to a device channel underlying the gate region. The stress produced on the device channel is a longitudinal stress on the order of about 275 MPa to about 450 MPa.

Abstract: Example embodiments relate to a method of manufacturing a germanosilicide and a semiconductor device having the germanosilicide. A method according to example embodiments may include providing a substrate having at least a portion formed of silicon germanium. A metal layer may be formed on the silicon germanium. A thermal process may be performed on the substrate at a relatively high pressure to form the germanosilicide.

Abstract: In some embodiments, when etching a dielectric to form a self-aligned contact opening to a source/drain region (160) of a transistor, the gate structure (220) is protected on top with a non-conformal layer (M3), possibly silicon, deposited so that it is thicker over the gate than over the source/drain region. The silicon may be insulated from the gates by another dielectric layer (M2). When the non-conformal layer is etched over the source/drain region, it may also be etched on top of the gate structure, but the gate structure remains protected due to the greater thickness of the non-conformal layer.

Abstract: A method of forming a transistor patterns a semiconductor fin on a substrate, such that the fin extends from the substrate. Then, the method forms a gate conductor over a central portion of the fin, leaving end portions of the fin exposed. Next, the end portions of the fin are doped with at least one impurity to leave the central portion of the fin as a semiconductor and form the end portions of the fin as conductors. The end portions of the fin are undercut to disconnect the end portions of the fin from the substrate, such that the fin is connected to the substrate along a central portion and is disconnected from the substrate along the end portions and that the end portions are free to move and the central portion is not free to move. A straining layer is formed on a first side of the fin and the straining layer imparts physical pressure on the fin such that the end portions are permanently moved away from a straight-line orientation with the central portion after the forming of the straining layer.

Abstract: Transistors and methods of manufacture thereof are disclosed. A workpiece is provided, a gate dielectric is formed over the workpiece, and a gate is formed over the gate dielectric by exposing the workpiece to a precursor of hafnium (Hf) and a precursor of silicon (Si). The gate may comprise a layer of a combination of Hf and Si. The layer of the combination of Hf and Si of the gate establishes the threshold voltage Vt of the transistor. The transistor may comprise a single NMOS transistor or an NMOS transistor of a CMOS device.

Abstract: Complementary RF LDMOS transistors have gate electrodes over split gate oxides. A source spacer of a second conductivity type extends laterally from the source tap of a first conductivity type to approximately the edge of the gate electrode above the thinnest gate oxide. A body of a first conductivity type extends from approximately the bottom center of the source tap to the substrate surface and lies under most of the thin section of the split gate oxide. The source spacer is approximately the length of the gate sidewall oxide and is self aligned with gate electrode. The body is also self aligned with gate electrode. The drain is surrounded by at least one buffer region which is self aligned to the other edge of the gate electrode above the thickest gate oxide and extends to the below the drain and extends laterally under the thickest gate oxide. Both the source tap and drain are self aligned with the gate side wall oxides and are thereby spaced apart laterally from the gate electrode.

Abstract: A nitride read-only memory cell and a method of manufacturing the same are provided. First, a substrate is provided, and a first oxide layer is formed on the substrate. Next, a nitride layer is deposited on the first oxide layer via a first gas and a second gas. The flow ratio of the first gas to the second gas is 2:1. After that, a second oxide layer is formed on the nitride layer. Then, a bit-line region is formed at the substrate. Afterward, a gate is formed on the second oxide layer. The first oxide layer, nitride layer, the second oxide layer and the gate compose a stack structure of the cell. Further, a spacer is formed on the side-wall of the stack structure.

Abstract: A new, effective and cost-efficient method of introducing Fluorine into Hf-based dielectric gate stacks of planar or multi-gate devices (MuGFET), resulting in a significant improvement in both Negative and Positive Bias Temperature Instabilities (NBTI and PBTI) is provided. The new method uses an SF6 based metal gate etch chemistry for the introduction of Fluorine, which after a thermal budget within the standard process flow, results in excellent F passivation of the interfaces. A key advantage of the method is that it uses the metal gate etch for F introduction, requiring no extra implantations or treatments. In addition to the significant BTI improvement with the novel method, a better Vth control and increased drive current on MuGFET devices is achieved.

Abstract: A method and an apparatus are provided in which non-directional and directional metal (e.g. Ni) deposition steps are performed in the same process chamber. A first plasma is formed for removing material from a target; a secondary plasma for increasing ion density in the material is formed in the interior of an annular electrode (e.g. a Ni ring) connected to an RF generator. Material is deposited non-directionally on the substrate in the absence of the secondary plasma and electrical biasing of the substrate, and deposited directionally when the secondary plasma is present and the substrate is electrically biased. Nickel silicide formed from the deposited metal has a lower gate polysilicon sheet resistance and may have a lower density of pipe defects than NiSi formed from metal deposited in a solely directional process, and has a lower source/drain contact resistance than NiSi formed from metal deposited in a solely non-directional process.

Abstract: Sensor platforms and methods of making them are described. A platform having a non-horizontally oriented sensor element comprising one or more nanostructures such as nanotubes is described. Under certain embodiments, a sensor element has or is made to have an affinity for an analyte. Under certain embodiments, such a sensor element comprises one or more pristine nanotubes. Under certain embodiments, the sensor element comprises derivatized or functionalized nanotubes. Under certain embodiments, a sensor is made by providing a support structure; providing one or more nanotubes on the structure to provide material for a sensor element; and providing circuitry to electrically sense the sensor element's electrical characterization. Under certain embodiments, the sensor element comprises pre-derivatized or pre-functionalized nanotubes. Under other embodiments, sensor material is derivatized or functionalized after provision on the structure or after patterning.

Abstract: A method of forming a package for a MEMS structure coupled to a substrate includes depositing an encapsulant material on the substrate and patterning the encapsulant material to form a plurality of encapsulated structures. The method also includes depositing a first capping layer on the substrate and forming one or more release hole patterns in the first capping layer. The method further includes removing the encapsulant material and depositing a second capping layer.

Abstract: A package includes a substrate provided with a passing opening and a MEMS device. The MEMS device includes an active surface wherein a portion of the MEMS device is integrated sensitive to the chemical/physical variations of a fluid. The active surface of the MEMS device faces the substrate and is spaced therefrom, the sensitive portion being aligned to the passing opening. A protective package incorporates the MEMS device and the substrate, leaving at least the sensitive portion of the MEMS device exposed through the passing opening of the substrate.

Abstract: A package is made of a transparent substrate having an interferometric modulator and a back plate. A non-hermetic seal joins the back plate to the substrate to form a package, and a desiccant resides inside the package. A method of packaging an interferometric modulator includes providing a transparent substrate and manufacturing an interferometric modulator array on a backside of the substrate. A back plate includes a curved portion relative to the substrate. The curved portion is substantially throughout the back plate. The back plate is sealed to the backside of the substrate with a back seal in ambient conditions, thereby forming a package.

Abstract: A MEMS microphone package includes a carrier, an application specific IC, an encapsulant and a microphone chip. The application specific IC and the microphone chip are respectively disposed on first and second surfaces of the carrier, and the application specific IC and the microphone chip are electrically connected to the carrier. The encapsulant includes first and second encapsulants, the first encapsulant is formed on the first surface to seal the application specific IC, the second encapsulant is formed on the second surface to become a cavity and the microphone chip is located at the cavity. Because the application specific IC and the microphone chip are disposed on the first and second surfaces of the carrier, respectively, the second encapsulant surrounds the microphone chip, and the first and second encapsulants are formed at the same time, it can increase the structural strength of package and reduce the process.

Abstract: A micro-electromechanical device comprises a micro-electromechanical die, a package, and three pillars attaching the micro-electromechanical die to the package, at least one of the shape, position and orientation of the pillars is configured such that any strain transferred from the package to the die by deformation of the package is minimized.

Abstract: A storage element includes a storage layer configured to hold information by use of a magnetization state of a magnetic material, with a pinned magnetization layer being provided on one side of the storage layer, with a tunnel insulation layer, and with the direction of magnetization of the storage layer being changed through injection of spin polarized electrons by passing a current in the lamination direction, so as to record information in the storage layer, wherein a spin barrier layer configured to restrain diffusion of the spin polarized electrons is provided on the side, opposite to the pinned magnetization layer, of the storage layer; and the spin barrier layer includes at least one material selected from the group composing of oxides, nitrides, and fluorides.

Abstract: One embodiment of the present invention includes a non-volatile magnetic memory element including a fixed layer, a barrier layer formed on top of the fixed layer, and a free layer formed on top of the barrier layer, wherein the electrical resistivity of the barrier layer is reduced by placing said barrier layer under compressive stress. Compressive stress is induced by either using a compressive stress inducing layer, or by using inert gases at low pressure during the sputtering process as the barrier layer is deposited, or by introducing compressive stress inducing molecules into the molecular lattice of the barrier layer.

Abstract: A method and apparatus for reducing thermally generated dark current in a CMOS imaging device is disclosed. A photodiode within the imaging device is kept zero-biased, so that the voltage is equal at both ends of the photodiode. This zero-biasing is accomplished using several different techniques, including, alternatively: a transistor operating at its sub-threshold level; a leaky diode; a short-channel MOSFET; or ramping charge injection.

Abstract: A package module for an image sensor device is disclosed. The package module comprises a device chip disposed between lower and upper substrates. A first conductive layer is over a first sidewall of the lower substrate and insulated from the device chip. A first protective layer is on the first conductive layer and exposes a portion of the first conductive layer over the first sidewall of the lower substrate. A first pad is on the bottom surface of the lower substrate and is electrically connected to the first conductive layer. The invention also discloses an electronic assembly for an image sensor device and a fabrication method thereof.

Abstract: Embodiments relate to an image sensor, and for directly manufacturing microlenses on color filter layers without forming a separate planarization layer, by forming the color filter layers having a relatively even step. According to embodiments, a method may include forming an interlayer dielectric layer on a semiconductor substrate formed with a plurality of photo diodes, forming color filter layers on the interlayer dielectric layer, forming a sacrifice layer on the whole surface including the color filter layers, making the steps of the color filter layers even by etching the upper surfaces of the color filter layers and the sacrifice layer, and forming microlenses on the color filter layers.

Abstract: Embodiments relate to a CMOS image sensor and to a method for manufacturing a CMOS image sensor that may disperse stray beam between microlenses. According to embodiments, the method for manufacturing the CMOS image may include forming an interlayer dielectric layer on a semiconductor substrate including a plurality of photo diodes, forming a color filter layer corresponding to the photo diodes on the interlayer dielectric layer, forming a planarization layer on the color filter layer, forming microlenses on the planarization layer after depositing an insulating layer over the microlenses, forming a trench in a concave lens shape in the insulating layer between the microlenses, and forming a concave lens gap-filling insulating materials inside the trench. In embodiments, concave lenses may be formed between microlenses in a CMOS image sensor and stray beams between the microlenses may be dispersed and recondensed into the microlenses.

Abstract: Isolation structure for CMOS image sensor device chip scale packages and fabrication methods thereof. A CMOS image sensor chip scale package includes a transparent substrate configured as a support structure for the package. The transparent substrate includes a first cutting edge and a second cutting edge. A CMOS image sensor die with a die circuitry is mounted on the transparent substrate. An encapsulant is disposed on the substrate encapsulating the CMOS image sensor die. A connection extends from the die circuitry to a plurality of terminal contacts for the package on the encapsulant, wherein the connection is exposed by the first cutting edge. An isolation structure is disposed on the first cutting edge passivating the exposed connection and co-planed with the second cutting edge.