Patents Issued in July 17, 2008
  • Publication number: 20080169439
    Abstract: The present invention is an integrated two-stage low-leak control valve which is used to control pressure or flow in a hydraulic system such as an automatic transmission valve body. The control valve formed of a single assembly. A valve portion and a solenoid portion are located in the single assembly. The solenoid portion is operably connected to the valve portion with two variable orifices contained in the single assembly. A first variable orifice controls the flow of a fluid medium from a supply port in the integrated control valve to a pressure control region of the integrated control valve, and a second variable orifice controls the flow of the fluid medium to an exhaust port in the integrated control valve.
    Type: Application
    Filed: December 18, 2007
    Publication date: July 17, 2008
    Applicant: BorgWarner Inc.
    Inventors: Jeffrey J. Waterstredt, Garrett R. Holmes, Steven L. Ambrose, Daniel L. DeLand
  • Publication number: 20080169440
    Abstract: A faucet for controlling the dispensing of liquids includes a valve body having a valve chamber with an inlet and an outlet. A valve element is located in the valve chamber and is movable from a first position for blocking flow between the inlet and outlet to a second position for permitting flow between the inlet and the outlet. An operating stem has an inner end operatively connected to the valve element and an outer end located external to the body. A bonnet is included, and an insert member is rotatably connected to the bonnet and defines an opening through which the stem extends. The bonnet and insert member are secured to the body and enclose the valve element in the valve chamber. The insert is located such that no portion of the insert member is clamped between the bonnet and the body. Spaced-apart guide walls project outwardly from the insert member external to the valve chamber. An actuator handle assembly is operatively coupled to the outer end of the stem.
    Type: Application
    Filed: January 16, 2008
    Publication date: July 17, 2008
    Inventors: Michael H. Meyer, Michael A. Kolar, Eric J. McCarty
  • Publication number: 20080169441
    Abstract: A quarter turn valve includes a tubular body having a bore flow passage, a valve element having a through flow passage, the valve element being supported in the through flow passage for rotation about an axis transverse to the through flow passage. The through flow passage is aligned with the bore flow passage to permit flow when the valve element is positioned at a first end of the quarter turn and is misaligned with the bore flow passage to prevent flow when the valve element is at a second end of the quarter turn. A motion multiplication device is included for facilitating a slow operation of the valve element. A tool engaging configuration is provided on the handle for facilitating a remote operation of the handle.
    Type: Application
    Filed: January 11, 2007
    Publication date: July 17, 2008
    Inventor: Patrick Allen Beebe
  • Publication number: 20080169442
    Abstract: A plug valve includes a valve body, an actuator, and an adapter. The valve body has an actuator end, a valve body end, and a stem chamber extending through said adapter. The valve body end of the adapter provides a valve body cover that can be attached to the valve body. The actuator end of the adapter is attached to the actuator by a threaded member extending through a set of holes of the adapter and the actuator. The adapter can have a bleedway in communication with the stem chamber for showing leakage. The holes of the adapter can be conforming to ISO standards for actuators.
    Type: Application
    Filed: January 11, 2008
    Publication date: July 17, 2008
    Applicant: GA INDUSTRIES INC.
    Inventor: Grant A. Colton
  • Publication number: 20080169443
    Abstract: A ball valve employing a flush inlet in the ball and a flush exhaust port in the valve body for communication with the ball valve port when the ball is oriented to allow source fluid to enter the ball valve port through the flush inlet is disclosed. The ball valve allows for convenient back flushing of an optional filter or located in the ball valve port and subsequent expulsion of debris flushed from the optional filter from the valve body through the flush exhaust port. The disclosed ball valve also allows for a simple method of collected fluid samples when a sample collector is connected to the flush exhaust port. The disclosed valve also operates to completely arrest fluid flow from the first end of the valve body to the second end in a manner similar to valve known in the prior art.
    Type: Application
    Filed: January 17, 2008
    Publication date: July 17, 2008
    Inventor: Donald Loloff
  • Publication number: 20080169444
    Abstract: A check valve for medical infusion lines and the like, includes a diaphragm made of elastic material set between a first tubular connector and a second tubular connector. The diaphram includes an end wall of a cup-shaped element, having an outer peripheral edge of which is normally pressed in seal contact against an annular valve seat with a conical surface of the first tubular connector under an axial thrust exerted by a side wall of the cup-shaped element. A free edge of the side wall of the cup-shaped element is set resting against a transverse surface of the second tubular connector only in regions corresponding to angular portions of the latter separated by non-resting angular portions.
    Type: Application
    Filed: January 16, 2008
    Publication date: July 17, 2008
    Applicant: INDUSTRIE BORLA S.p.A
    Inventor: Gianni GUALA
  • Publication number: 20080169445
    Abstract: A piezoelectric ceramic composition includes a bismuth layer compound containing at least Sr, Bi and Nb, e.g., (Sr0.9Nd0.1)Bi2Nb2O9, as a main component and 2 parts by weight or less (excluding 0 part by weight), preferably 0.04 part by weight to 0.5 part by weight, of Cu in terms of CuO relative to 100 parts by weight of the main component. From the viewpoint of improvement in sinterability, 0.1 part by weight to 2 parts by weight of Mn in terms of MnCO3 relative to 100 parts by weight of the main component is preferably contained. As a result, it is possible to obtain a piezoelectric ceramic composition resisting no deterioration in piezoelectricity even when a rapid temperature change occurs, and an advantageous piezoelectric component, such as a piezoelectric actuator or a piezoelectric resonator, manufactured using the piezoelectric ceramic composition.
    Type: Application
    Filed: March 24, 2008
    Publication date: July 17, 2008
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Hirozumi Ogawa, Masahiko Kimura, Kosuke Shiratsuyu
  • Publication number: 20080169446
    Abstract: The present invention relates to compositions for use in refrigeration and air-conditioning systems comprising 1,1,1,2,2,3,3,4,4-nonafluoro-4-methoxybutane and at least one chlorocarbon, alcohol, ether, ester, N-(difluoromethyl)-N,N-dimethylamine, or mixtures thereof. Further, the present invention relates to compositions for use in refrigeration and air-conditioning systems employing a centrifugal compressor comprising 1,1,1,2,2,3,3,4,4-nonafluoro-4-methoxybutane and at least one chlorocarbon, alcohol, ether, ester, N-(difluoromethyl)-N,N-dimethylamine, or mixtures thereof. The compositions of the present invention may be azeotropic or near-azeotropic and are useful in processes for producing cooling or heat or as heat transfer fluids.
    Type: Application
    Filed: February 6, 2008
    Publication date: July 17, 2008
    Applicant: E.I. du Pont de Nemours and Company
    Inventor: BARBARA HAVILAND MINOR
  • Publication number: 20080169447
    Abstract: There is provided an allergen inactivating agent having less lowering in performance due to fluctuation in pH, and being capable of not only adsorbing and removing an allergen, but also inactivating and removing the allergen itself. In addition, there is provided a house dust treatment agent, spray, and sheet, capable of effectively removing house dust, without any disadvantages upon use such as generation of stains.
    Type: Application
    Filed: March 17, 2006
    Publication date: July 17, 2008
    Inventors: Shinichi Nagai, Takashi Sugiyama
  • Publication number: 20080169448
    Abstract: To provide a liquid crystalline composition, which can be obtained by mixing a plurality of liquid crystalline composition search of which can exhibit different liquid crystal phases from one another, being capable of exhibiting a biaxial liquid crystal phase, a liquid crystalline composition contains a liquid crystalline composition R which exhibits a liquid crystal phase having a positive birefringence; and a liquid crystalline composition D which exhibits a liquid crystal phase having a negative birefringence, in which the liquid crystalline composition R comprises a compound having a rectangular plate-like shape.
    Type: Application
    Filed: March 12, 2008
    Publication date: July 17, 2008
    Applicant: FujiFilm Corporation
    Inventors: Hideyuki Nishikawa, Atsuhiro Ohkawa
  • Publication number: 20080169449
    Abstract: A solid state membrane for a reforming reactor is disclosed which comprises at least one oxygen anion-conducting oxide selected from the group consisting of hexaaluminates, cerates, perovskites, and other mixed metal oxides that are able to adsorb and dissociate molecular oxygen. The membrane adsorbs and dissociates molecular oxygen into highly active atomic oxygen and allows oxygen anions to diffuse through the membrane, to provide high local concentration of oxygen to deter formation and deposition of carbon on reformer walls. Embodiments of the membrane also have catalytic activity for reforming a hydrocarbon fuel to synthesis gas. Also disclosed are a reformer having an inner wall containing the new membrane, and a process of reforming a hydrocarbon feed, such as a high sulfur-containing diesel fuel, to produce synthesis gas, suitable for use in fuel cells.
    Type: Application
    Filed: September 6, 2007
    Publication date: July 17, 2008
    Applicant: ELTRON RESEARCH INC.
    Inventor: Michael V. MUNDSCHAU
  • Publication number: 20080169450
    Abstract: Composition and method for enhancing the dielectric strength of an in-service solid dielectric shielded electrical cable and preventing corrosion of a central aluminum conductor of the cable by supplying the cable with an alkoxysilane composition. In one embodiment, the alkoxysilane composition includes dimethyldi(n-butoxy)silane.
    Type: Application
    Filed: December 27, 2007
    Publication date: July 17, 2008
    Applicant: UTILX CORPORATION
    Inventors: Wayne J. Chatterton, James Steele, William R. Stagi
  • Publication number: 20080169451
    Abstract: The invention relates to the synthesis of polythiophene (PAT) copolymers, and their use as conductive polymers in final applications. Specifically, copolymers of PAT with (meth)acrylates, or amides are useful as additives in blends of different polymer matrices in many commercial applications.
    Type: Application
    Filed: March 3, 2006
    Publication date: July 17, 2008
    Applicant: Arkema Inc.
    Inventors: Gary S. Silverman, Thomas P. Mc Andrew, Scott C. Schmidt, David A. Mountz, Mark A. Aubart, Nicholas J. Rodak
  • Publication number: 20080169452
    Abstract: The invention relates to a mixture and a method for imprinting textiles. The mixture used for the imprinting of textiles, includes: A) at least one pigment, B) at least one dispersing agent on the basis of oxalkylated linear or branched alkanes, fatty acids or fatty alcohols, and/or alkyl sulfates or alkyl sulfonates, and/or polyelectrolytes, and/or alkylated, and/or arylated glycosides; C) at least one water-soluble or water-dilutable, radiation-hardenable binding agent with a molecular weight above 2000 g/mol and at least two polymerizable groups for each binding agent molecule, which are cross-linked to the binding agent molecule by at least one urethane group or urea group; D) water.
    Type: Application
    Filed: December 27, 2005
    Publication date: July 17, 2008
    Applicant: ITCF Institut fur Textilchemie Und Chemiefasern
    Inventors: Reinhold Schneider, Marion Funkler
  • Publication number: 20080169453
    Abstract: According to the present invention, there is provided a near infrared ray absorbing material comprising at least a first compound having a spectral absorption maximum wavelength of 470 nm or less in a range of 270 to 1600 nm in solution, and a second compound represented by the following formula (II-1) or (II-2). where in the formulas, R201, R202, R211, R212, R221, and R222 each represent, independently, a hydrogen atom, an aliphatic group, an aromatic group, or a heterocyclic group linked via a carbon atom; Z201 and Z202 represent a nonmetal atomic group necessary for forming a nitrogen-containing heterocycle; R213 to R216 and R223 to R226 represent a hydrogen atom or a substituent.
    Type: Application
    Filed: August 16, 2007
    Publication date: July 17, 2008
    Applicant: FUJIFILM CORPORATION
    Inventors: Keizo Kimura, Katsuyoshi Yamakawa, Osamu Uchida
  • Publication number: 20080169454
    Abstract: A range of mixed support and compression sheave assemblies is formed from standard 2S2C modules each comprising: two compression sheaves (11) and two support sheaves (12) respectively mounted rotating freely on the ends of two pairs of holding arms (15,16; 18,19) articulated on one another by a first upper joint pin (17) and a second lower joint pin (20), a first damping element (24) inserted between two bearing edges (22,23) securedly fixed to the two holding arms (15,16) of the compression sheaves (11), a second damping element (27) inserted between two bearing edges (25,26) of the two holding arms (18,19) of the support sheaves (12), and a frame (28) connecting the first and second joint pins (17,20), said frame being arranged to be connected to the end of a beam (14) with a swivel-pin (21). Application: aerial ropeway transport installations.
    Type: Application
    Filed: November 16, 2007
    Publication date: July 17, 2008
    Applicant: POMAGALSKI SA.
    Inventors: Daniel Michel, Laurent Bonifat, Thierry Triolier
  • Publication number: 20080169455
    Abstract: A fence attachment system includes a fence post clamp, a first anchoring device and an adapter with a second anchoring device for standardized attachment of any type fence panels to any type fence posts, wherein the fence post clamp has for example a ring-shaped configuration and contractible via a straining screw such that the clamp fits a variety of different fence posts, wherein the first anchoring device are preferably elongated holes distributed across the circumference of the ring-shaped clamp for fastening the adapters; with specialized fence post clamps for gate joints or disposition of a gate lock stop integration of a fence gate is also realized.
    Type: Application
    Filed: January 11, 2008
    Publication date: July 17, 2008
    Applicant: Gust. Alberts GmbH & Co. KG
    Inventor: DIETRICH ALBERTS
  • Publication number: 20080169456
    Abstract: Stairway and balcony railing assemblies are provided with balusters having elongated rod-like leg parts interconnecting baluster ends which may include support trunnions for connecting the balusters to a base and to a railing cap. The baluster legs are interconnected by two part collars which may be assembled to interconnect adjacent balusters and to support ornamental barrier parts. The ornamental barrier parts may comprise multipart members which may be assembled and disassembled by threaded connections to facilitate modular onsite erection of the railing assemblies.
    Type: Application
    Filed: January 16, 2007
    Publication date: July 17, 2008
    Inventor: Nancy A. Ross
  • Publication number: 20080169457
    Abstract: Phase-changeable memory devices and method of fabricating phase-changeable memory devices are provided that include a phase-changeable material pattern of a phase-changeable material that may include nitrogen atoms and/or silicon atoms. First and second electrodes are electrically connected to the phase-changeable material pattern and provide an electrical signal thereto. The phase-changeable material pattern may have a polycrystal line structure.
    Type: Application
    Filed: February 28, 2008
    Publication date: July 17, 2008
    Inventors: Horii Hideki, Bong-Jin Kuh, Yong-Ho Ha, Jeong-hee Park, Ji-Hye Yi
  • Publication number: 20080169458
    Abstract: Non-volatile memories formed on a substrate and fabrication methods are disclosed. A bottom electrode comprising a metal layer is disposed on the substrate. A buffer layer comprising a LaNiO3 film is disposed over the metal layer. A resistor layer comprising a SrZrO3 film is disposed on the buffer layer. A top electrode is disposed on the resistor layer.
    Type: Application
    Filed: March 20, 2007
    Publication date: July 17, 2008
    Inventors: Tseung-Yeun Tseng, Chun-chieh Lin, Chao-Cheng Lin
  • Publication number: 20080169459
    Abstract: Provided are a resistive random access memory device and a method of manufacturing the same. The resistive random access memory device includes a switching device and a storage node connected to the switching device, and the storage node includes a first electrode and a second electrode and a resistance change layer formed of Cu2-XO between the first electrode and the second electrode.
    Type: Application
    Filed: December 20, 2007
    Publication date: July 17, 2008
    Inventors: Sang-jun Choi, Jung-hyun Lee, Hyung-jin Bae, Chang-soo Lee
  • Publication number: 20080169460
    Abstract: An organic light emitting diode display and an aging method thereof are presented. The method provides the organic light emitting diode display with improved reliability as a progressive dark defect is removed, and the lifetime and the white balance of the organic light emitting diode display is secured by executing an aging treatment of high luminance using a pixel circuit including an aging circuit for supplying the organic light emitting diode with an aging pulse.
    Type: Application
    Filed: April 17, 2007
    Publication date: July 17, 2008
    Inventor: Jaeho Yoo
  • Publication number: 20080169461
    Abstract: A display device includes; an insulation substrate, a thin film transistor disposed on the insulation substrate and which includes a drain electrode, an insulation layer disposed on the thin film transistor and which includes a contact hole which exposes the drain electrode, a first electrode disposed on the insulation layer and which electrically connects with the drain electrode through the contact hole, a wall disposed on the insulation layer, the wall including an opening and a groove, wherein the opening at least partially exposes the first electrode and the groove at least partially encloses the opening, an organic layer disposed on the first electrode exposed through the opening in the wall; and a second electrode disposed on the organic layer and the wall, at least a portion of the second electrode being disposed on the groove.
    Type: Application
    Filed: August 28, 2007
    Publication date: July 17, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Seung-kyu PARK
  • Publication number: 20080169462
    Abstract: A thin film transistor includes a source electrode and a drain electrode which are disposed to face each other, an organic semiconductor layer provided at least between the source electrode and the drain electrode, a plurality of gate lines extending over the source electrode, the organic semiconductor layer, and the drain electrode, and a gate insulating layer interposed between the source electrode, the drain electrode, and the organic semiconductor layer and the plurality of gate lines.
    Type: Application
    Filed: September 18, 2007
    Publication date: July 17, 2008
    Applicant: Seiko Epson Corporation
    Inventors: Kiyoshi Nakamura, Hirofumi Hokari, Kazuya Nakamura
  • Publication number: 20080169463
    Abstract: An organic light emitting device includes a substrate, first and second ohmic contacts formed on the substrate, a driving semiconductor formed on the substrate and the first and second ohmic contacts and including polysilicon, a driving input electrode electrically connected to the first ohmic contact, a driving output electrode electrically connected to the second ohmic contact, a first gate insulating layer formed on the driving semiconductor, the driving input electrode, and the driving output electrode, and a driving control electrode formed on the first gate insulating layer and overlapping the driving semiconductor.
    Type: Application
    Filed: October 31, 2007
    Publication date: July 17, 2008
    Inventors: Byoung-Seong Jeong, Kyu-Sik Cho, Joon-Hoo Choi, Yong-Hwan Park
  • Publication number: 20080169464
    Abstract: Two-terminal switching devices of MIM type having at least one electrode formed by a liquid phase processing method are provided for use in active matrix backplane applications; more specifically, MIM devices with symmetric current-voltage characteristics are applied for LCD active matrix backplane applications, and MIM devices with asymmetric current-voltage characteristics are applied for active matrix backplane implementation for electrophoretic displays (EPD) and rotating element displays. In particular, the combination of the bottom metal, metal-oxide insulator and solution-processible top conducting layer enables high throughput, roll-to-roll process for flexible displays.
    Type: Application
    Filed: November 6, 2007
    Publication date: July 17, 2008
    Inventors: Xiong Gong, Kaixia Yang, Gang Yu, Boo Jorgen Lars Nilsson, Chan-Long Shieh, Hsing-Chung Lee, Fatt Foong
  • Publication number: 20080169465
    Abstract: A method of manufacturing a probe includes: forming a first slant face of the probe through an anisotropic etching process using a first etching mask pattern formed on a silicon substrate; forming a first semiconductor electrode region; forming a second etching mask pattern in an opposite direction of the first etching mask pattern on the silicon substrate; forming a spacer layer on a side wall of the second etching mask pattern; forming a second slant face of the probe; forming a second semiconductor electrode region; forming a silicon oxide layer pattern on the resulting silicon substrate; forming spacer layers on both side walls of the silicon oxide layer pattern; and etching the silicon substrate to a predetermined depth.
    Type: Application
    Filed: December 17, 2007
    Publication date: July 17, 2008
    Applicants: SAMSUNG ELECTRONICS CO., LTD., SEOUL NATIONAL UNIVERSITY INDUSTRY FOUNDATION
    Inventors: Hyoung Soo KO, Byung Gook PARK, Seung Bum HONG, Chul Min PARK, Woo Young CHOI, Jong Pil KIM, Jae Young SONG, Sang Wan KIM
  • Publication number: 20080169466
    Abstract: A test cell for localizing defects includes a first active region, a second active region formed substantially parallel to the first active region, a third active region formed substantially parallel to the first and second active regions, a fourth active region formed between the first and second active regions, and a fifth active region formed between the second and third active regions. The fourth and fifth active regions are formed adjacent to opposite end portions of the second active region. The fourth and fifth active regions are also formed substantially perpendicular to the second active region.
    Type: Application
    Filed: December 14, 2007
    Publication date: July 17, 2008
    Applicant: PDF Solutions, Inc.
    Inventors: Brian Stine, Victor Kitch, Mark Zwald, Stefano Tonello
  • Publication number: 20080169467
    Abstract: A transistor of a characteristic checking element has a gate electrode connected to a measurement pad disposed in a dicing line and to an internal measurement pad disposed inside a semiconductor device. In a P/W process, a gate insulating film of the transistor is broken by an electric voltage applied via the internal measurement pad. Since the gate insulating film of the transistor is broken, a new current path is formed. Thus, measurement of accurate characteristics of the characteristic checking element is inhibited.
    Type: Application
    Filed: January 8, 2008
    Publication date: July 17, 2008
    Inventors: Minoru Yamagami, Hisayuki Nagamine
  • Publication number: 20080169468
    Abstract: Provided is a method and apparatus for fabricating a polycrystalline silicon film using a transparent substrate. The method includes forming a light absorption layer on a surface of the transparent substrate; and heating the light absorption layer using irradiation of Rapid Thermal Process (RTP) light source, while depositing the polycrystalline silicon film on the light absorption layer.
    Type: Application
    Filed: November 14, 2006
    Publication date: July 17, 2008
    Applicant: POINT ENGINEERING CO., LTD
    Inventor: Bum Mo Ahn
  • Publication number: 20080169469
    Abstract: A display device for improving an aperture ratio of the pixel is provided. In the display device, a transparent oxide layer, an insulating film, and a conductive layer are sequentially stacked on a pixel region on a substrate, the conductive layer has a gate electrode of a thin film transistor connected to a gate signal line, and a region of the transparent oxide layer other than at least a channel region portion directly below the gate electrode is converted into an electrically conductive region, and a source signal line, a source region portion of the thin film transistor connected to the source signal line, a pixel electrode, and a drain region portion of the thin film transistor connected to the pixel electrode are formed from the conductive region.
    Type: Application
    Filed: December 26, 2007
    Publication date: July 17, 2008
    Inventors: Tetsufumi Kawamura, Takeshi Sato, Mutsuko Hatano, Yoshiaki Toyota
  • Publication number: 20080169470
    Abstract: A thin film transistor (TFT) array substrate and a method of manufacturing the same that is capable of decreasing the number of usage of exposure masks to reduce the process time and the process costs and excessively etching a passivation film below a photoresist pattern to easily perform a lift-off process of the photoresist pattern are disclosed.
    Type: Application
    Filed: December 28, 2007
    Publication date: July 17, 2008
    Applicant: LG.PHILIPS LCD CO., LTD
    Inventors: Joo Soo Lim, Hyun Seok Hong, Chang Bin Lee
  • Publication number: 20080169471
    Abstract: A display substrate includes a gate line, a data line, a pixel electrode and a source pad part. The gate line is formed on a base substrate. The data line crosses the gate line to define a pixel area. The pixel electrode makes contact with the base substrate. The source pad part is formed on an end portion of the data line, the source pad part including a source metal layer, a conductive etch stop layer formed on the source metal layer and a source pad electrode formed on the conductive etch stop layer. Thus, the conductive etch stop layer of the source pad part prevents the source metal layer of the source pad part from being damaged and the conductive etch stop layer of the source pad part may fully make contact with the source pad electrode.
    Type: Application
    Filed: January 8, 2008
    Publication date: July 17, 2008
    Inventors: Won-Suk Shin, Hong-Sick Park, Jong-Hyun Choung, Sun-Young Hong, Bong-Kyun Kim, Byeong-Jin Lee
  • Publication number: 20080169472
    Abstract: Disclosed are embodiments of a field effect transistor that incorporates an elongated semiconductor body with a spiral-shaped center channel region wrapped one or more times around a gate and with ends that extend outward from the center region in opposite directions away from the gate. Source/drain regions are formed in the end regions by either doping the end regions or by biasing a back gate to impart a preselected Fermi potential on the end regions. This disclosed structure allows the transistor size to be scaled without decreasing the effective channel length to the point where deleterious short-channel effects are exhibited. It further allows the transistor size to be scaled while also allowing the effective channel length to be selectively increased (e.g., by increasing the number of times the channel wraps around the gate). Also, disclosed are embodiments of an associated method of forming the transistor.
    Type: Application
    Filed: January 17, 2007
    Publication date: July 17, 2008
    Inventors: Andres Bryant, Jia Chen, Edward J. Nowak
  • Publication number: 20080169473
    Abstract: A thin film transistor array panel includes an insulating substrate, a plurality of gate lines formed on the substrate, a plurality of data lines, and an insulating layer. Each of the gate lines include a plurality of gate electrodes. The data lines cross the gate lines with insulation therebetween. Each of the data lines include a plurality of source electrodes. A plurality of drain electrodes face the source electrodes. The insulating layer is formed on the gate lines, the data lines, and the drain electrodes. A plurality of pixel electrodes are formed on the insulating layer and connected to the drain electrodes. The insulating layer has an opening or a trench and the opening or the trench is disposed in a part of the insulating layer that is not covered by the pixel electrodes.
    Type: Application
    Filed: May 30, 2007
    Publication date: July 17, 2008
    Inventor: Yong-Seok CHO
  • Publication number: 20080169474
    Abstract: Monolithic electronic devices including a common nitride epitaxial layer are provided. A first type of nitride device is provided on the common nitride epitaxial layer including a first at least one implanted n-type region on the common nitride epitaxial layer. The first at least one implanted n-type region has a first doping concentration greater than a doping concentration of the common nitride epitaxial layer. A second type of nitride device, different from the first type of nitride device, including a second at least one implanted n-type region is provided on the common nitride epitaxial layer. The second at least one implanted n-type region is different from the first at least one implanted n-type region and has a second doping concentration that is greater than the doping concentration of the common nitride epitaxial layer. A first plurality of electrical contacts are provided on the first at least one implanted n-type region.
    Type: Application
    Filed: March 19, 2008
    Publication date: July 17, 2008
    Inventor: Scott T. Sheppard
  • Publication number: 20080169475
    Abstract: A semiconductor device includes a first-conductivity-type SiC substrate, a first-conductivity-type SiC semiconductor layer formed on the substrate, whose impurity concentration is lower than that of the substrate, a first electrode formed on the semiconductor layer and forming a Schottky junction with the semiconductor layer, a barrier height of the Schottky junction being 1 eV or less, plural second-conductivity-type junction barriers formed to contact the first electrode and each having a depth d1 from an upper surface of the semiconductor layer, a width w, and a space s between adjacent ones of the junction barriers, a second-conductivity-type edge termination region formed outside the junction barriers to contact the first electrode and having a depth d2 from the upper surface of the semiconductor layer, and a second electrode formed on the second surface of the substrate, wherein following relations are satisfied d1/d2?1, s/d1?0.6, and s/(w+s)?0.33.
    Type: Application
    Filed: July 12, 2007
    Publication date: July 17, 2008
    Inventors: Johji Nishio, Takuma Suzuki, Chiharu Ota, Takashi Shinohe
  • Publication number: 20080169476
    Abstract: A high quality single crystal wafer of SiC is disclosed having a diameter of at least about 3 inches and a 1c screw dislocation density of less than about 2000 cm 2.
    Type: Application
    Filed: November 15, 2007
    Publication date: July 17, 2008
    Applicant: CREE, INC.
    Inventors: Adrian Powell, Mark Brady, Stephan G. Mueller, Valeri F. Tsvetkov, Robert T. Leonard
  • Publication number: 20080169477
    Abstract: A package structure for an optoelectronic device. The package structure comprises a device chip reversely disposed on a first substrate, which comprises a second substrate and a first dielectric layer between the first and second substrates. The first dielectric layer comprises a pad formed in a corner of the first dielectric layer non-overlapping the second substrate, such that the surface and sidewall of the pad are exposed. A metal layer is formed directly on the exposed surface of the pad and covers the second substrate. A protective layer covers the metal layer, having an opening to expose a portion of the metal layer on the second substrate. A solder ball is disposed in the opening, electrically connecting to the metal layer. The invention also discloses a method for fabricating the same.
    Type: Application
    Filed: January 11, 2007
    Publication date: July 17, 2008
    Inventors: Kai-Chih Wang, Fang-Chang Liu
  • Publication number: 20080169478
    Abstract: A photocoupler includes a silicon substrate, a light receiving element embedded in the substrate, a transparent insulating film formed on the substrate to cover the light receiving element, and a light emitting element facing the light receiving element via the transparent insulating film. The light emitting element is an organic electroluminescent light source made up of a metal electrode, a transparent electrode, and a light emitting layer disposed between the metal electrode and the transparent electrode.
    Type: Application
    Filed: January 10, 2008
    Publication date: July 17, 2008
    Applicant: ROHM CO., LTD.
    Inventor: Masahiro Muranaka
  • Publication number: 20080169479
    Abstract: A light-emitting diode includes a substrate (110), a reflective layer (120), a second diffraction grating (130), a first semiconductor layer (142), an active layer (144), a second semiconductor layer (146), a transparent electrode layer (148), and a first diffraction grating (150), arranged in that order. The first diffraction grating and the second diffraction grating is composed of an array of parallel and equidistant grooves, and a inclined angle between the grooves of the first diffraction grating and the grooves of the second diffraction grating is equal to or more than 0° and equal to or less than 90°. One of the first semiconductor layer and the second semiconductor layer is an N-type semiconductor and the other thereof is a P-type semiconductor. The light-emitting diode has high light extraction efficiency and is easy to manufacture at a low cost.
    Type: Application
    Filed: November 12, 2007
    Publication date: July 17, 2008
    Applicants: TSINGHUA UNIVERSITY, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: ZHEN-FENG XU, GUO-FAN JIN, SHOU-SHAN FAN
  • Publication number: 20080169480
    Abstract: An optoelectronic device package. The optoelectronic device package includes a substrate, a reflector formed on a first plane of the substrate, a cover bonded to the reflector to form a closed space, a plurality of microlenses formed on a first plane of the cover, a phosphor film formed on a second plane of the cover within the closed space, a thermal-conductive film formed on a second plane of the substrate, an electrode formed on the sidewall and the second plane of the substrate uncovered by the thermal-conductive film, and an optoelectronic device formed on the first plane of the substrate within the closed space. The invention also provides a method of packaging the optoelectronic device.
    Type: Application
    Filed: January 11, 2007
    Publication date: July 17, 2008
    Inventors: Jui-Ping Weng, Hsiao-Wen Lee
  • Publication number: 20080169481
    Abstract: A semiconductor light emitting device including: a support substrate; a composite connection layer formed above the support substrate, the composite connection layer including a first connection layer and a second connection layer; a diffusion barrier layer formed above the composite connection layer; a semiconductor lamination structure formed above the diffusion barrier layer; and a reflective electrode layer formed between the diffusion barrier layer and the semiconductor lamination structure, wherein: at least one of the first and second connection layers is made of eutectic material; and the diffusion barrier layer has a lamination structure having TaN layers sandwiching at least one refractory metal layer made of one or more refractory metal materials of Ta, Ti, Mo, W and TiW or alloy thereof. It is possible to prevent defects such as stripping and cracks at bonding planes and improve reliability of a final semiconductor light emitting device.
    Type: Application
    Filed: October 4, 2007
    Publication date: July 17, 2008
    Applicant: Stanley Electric Co., Ltd.
    Inventors: Seiichiro Kobayashi, Kazuyuki Yoshimizu
  • Publication number: 20080169482
    Abstract: Disclosed is a semiconductor light emitting device comprising a reflective structure layer comprising a dopant layer and a roughness layer, a first conductive semiconductor layer on the reflective structure layer, an active layer on the first conductive semiconductor layer, and a second conductive semiconductor layer on the active layer.
    Type: Application
    Filed: January 9, 2008
    Publication date: July 17, 2008
    Inventor: Dae Sung KANG
  • Publication number: 20080169483
    Abstract: There is provided a method of producing a thin GaN film-joined substrate, including the steps of: joining on a GaN bulk crystalline body a substrate different in type or chemical composition from GaN; and dividing the GaN bulk crystalline body at a plane having a distance of at least 0.1 ?m and at most 100 ?m from an interface thereof with the substrate different in type, to provide a thin film of GaN on the substrate different in type, wherein the GaN bulk crystalline body had a surface joined to the substrate different in type, that has a maximum surface roughness Rmax of at most 20 ?m. Thus a GaN-based semiconductor device including a thin GaN film-joined substrate including a substrate different in type and a thin film of GaN joined firmly on the substrate different in type, and at least one GaN-based semiconductor layer deposited on the thin film of GaN, can be fabricated at low cost.
    Type: Application
    Filed: June 28, 2007
    Publication date: July 17, 2008
    Inventors: Hitoshi Kasai, Akihiro Hachigo, Yoshiki Miura, Katsushi Akita
  • Publication number: 20080169484
    Abstract: A strain-induced layer is formed atop a MOS device in order to increase carrier mobility in the channel region. The dimension of the strain-induced layer in preferred embodiments may lead to an optimized drive current increase and improved drive current uniformity in an NMOS and PMOS device. An advantage of the preferred embodiments is that improved device performance is obtained without adding complex processing steps. A further advantage of the preferred embodiments is that the added processing steps can be readily integrated into a known CMOS process flow. Moreover, the creation of the photo masks defining the tensile and compressive strain-induced layers does not require extra design work on an existed design database.
    Type: Application
    Filed: September 4, 2007
    Publication date: July 17, 2008
    Inventors: Harry Chuang, Kong-Beng Thei, Wen-Huei Guo, Mong Song Liang
  • Publication number: 20080169485
    Abstract: A semiconductor device is disclosed. In one aspect, the device comprises a channel area, the channel area comprising a channel layer in which charge carriers can move when the transistor is turned on, in order to pass a current through the transistor. The device further comprises a source area and a drain area contacting the channel layer for providing current to and from the channel layer. The method further comprises a gate electrode, preferably provided with a gate dielectric between the gate electrode and the channel layer. The channel layer may comprise a III-V material, and the source and drain areas comprise SiGe, being SixGe1-x, with x between 0 and 100%, arranged so that heterojunctions are present between III-V material and SiGe, wherein the heterojunctions are oriented so as to intersect with the gate dielectric or the gate electrode.
    Type: Application
    Filed: December 21, 2007
    Publication date: July 17, 2008
    Applicant: Interuniversitair Microelektronica Centrum (IMEC) vzw
    Inventors: Marc Heyns, Marc Meuris
  • Publication number: 20080169486
    Abstract: To provide a semiconductor integrated circuit device advantageous against EM and ESD. A plurality of I/O cells; a power wire formed of a plurality of interconnect layers over the above-described I/O cells; a bonding pad formed in an upper layer of the power wire and in a position corresponding to the I/O cell; and lead-out areas capable of electrically coupling the I/O cell to the bonding pad are provided. The above-described power wire includes a first power wire and a second power wire, and the above-described I/O cell includes first elements coupled to the first power wire and second elements coupled to the second power wire. The first element is placed on the first power wire side, and the second element is placed on the second power wire side. The first power wire and the second power wire can allow for a high current due to the interconnect layers over the I/O cells, thus having robustness against EM and ESD.
    Type: Application
    Filed: December 22, 2007
    Publication date: July 17, 2008
    Inventors: Shunsuke Toyoshima, Kazuo Tanaka, Masaru Iwabuchi
  • Publication number: 20080169487
    Abstract: In a layout structure of a semiconductor integrated circuit, when transistors are arranged in a constant gate wiring pitch, a common source diffusion region is provided between two adjacent transistors, a CA via is provided on the common source diffusion region, and a source wiring connected to the CA via is provided on the common source diffusion region. An inter-drain wiring connecting the drain regions of the two transistors is formed in a wiring layer higher than the source wiring. Therefore, the wiring path of the source wiring is not limited by the wiring path of the inter-drain wiring, and can be provided, covering the common source diffusion region to a further extent. As a result, the number of high-resistance CA vias or the flexibility of arrangement is increased, leading to a reduction in source resistance, resulting in an increase in operating speed of the semiconductor integrated circuit.
    Type: Application
    Filed: January 3, 2008
    Publication date: July 17, 2008
    Inventors: Hiroyuki Shimbo, Hidetoshi Nishimura
  • Publication number: 20080169488
    Abstract: A memory system having electromechanical memory cells and decoders is disclosed. A decoder circuit selects at least one of the memory cells of an array of such cells. Each cell in the array is a crossbar junction at least one element of which is a nanotube or a nanotube ribbon. The decoder circuit is constructed of crossbar junctions at least one element of each junction being a nanotube or a nanotube ribbon.
    Type: Application
    Filed: September 11, 2007
    Publication date: July 17, 2008
    Applicant: NANTERO, INC.
    Inventors: Brent M. SEGAL, Darren K. BROCK, Thomas RUECKES