Patents Issued in July 17, 2008
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Publication number: 20080169489Abstract: A method of forming multi-wall tube from a single-wall piece of tube. The multi-wall tube is formed by relative motion between a die shoe and the single-wall tube to deform the material.Type: ApplicationFiled: October 27, 2006Publication date: July 17, 2008Inventors: Robert Raymond Petkovsek, Louis Hagedorn
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Publication number: 20080169490Abstract: Disclosed is a semiconductor device using an SOI substrate and improving carrier mobility of transistors. Over a thin Si layer formed over a Si substrate through a buried insulating film, a gate electrode is formed through a gate insulating film. On both sides of the gate electrode, S/D layers are formed which penetrate through the Si layer and the buried insulating film into the Si substrate and which have a crystal structure with a lattice constant different from that of the Si substrate or the Si layer. Since a channel region is formed within the Si layer, the short channel effect can be suppressed. In addition, since the S/D layer having a crystal structure different from that of a Si crystal is thickly formed to reach the Si substrate, sufficient stress is generated in the channel region, so that the carrier mobility can be efficiently improved.Type: ApplicationFiled: March 24, 2008Publication date: July 17, 2008Applicant: FUJITSU LIMITEDInventor: Shinichi KAWAI
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Publication number: 20080169491Abstract: A solid-state imaging device including an imaging area formed of a plurality of pixels arrayed in a two-dimensional matrix is provided. The solid-state imaging device includes: a photoelectric conversion portion including a charge accumulation region provided on a semiconductor substrate; a read transistor for reading electric charges from the photoelectric conversion portion; and a gettering site for separating metal impurities within the semiconductor substrate from at least the photoelectric conversion portion. The photoelectric conversion portion is provided on the surface side of the semiconductor substrate, and the gettering site is provided on the rear side away from the semiconductor substrate.Type: ApplicationFiled: January 7, 2008Publication date: July 17, 2008Applicant: SONY CORPORATIONInventor: Yasushi Maruyama
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Publication number: 20080169492Abstract: Disclosed herein is a spin transistor including: a semiconductor substrate having a channel layer formed therein; first and second electrodes which are formed to be spaced apart from each other on the substrate at a predetermined distance along a longitudinal direction of the channel layer; a source and drain which include magnetized ferromagnetic materials and are formed to be spaced apart form each other between the first electrode and the second electrode at a predetermined distance along the longitudinal direction of the channel layer; and a gate which is formed on the substrate between the source and the drain, and adjusts spin orientations of electrons passing through the channel layer, wherein the electrons passing through the channel layer are spin-aligned at a lower side of the source by a stray magnetic field of the source and spin-filtered at a lower side of the drain by a stray field of the drain.Type: ApplicationFiled: July 12, 2007Publication date: July 17, 2008Applicant: Korea Institute of Science And TechnologyInventors: Hyun Cheol Koo, Jong Hwa Eom, Suk Hee Han, Joon Yeon Chang, Hyung Jun Kim
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Publication number: 20080169493Abstract: Semiconductor devices include an active region defined in a semiconductor substrate having first type impurity ions. A retrograde region is in the active region and has second type impurity ions. An upper channel region is on the retrograde region in the active region and has the first type impurity ions. Source and drain regions are on the upper channel region in the active region and spaced apart from each other. A gate electrode fills a gate trench formed in the active region. The gate electrode is disposed between the source and drain regions and extends into the retrograde region through the upper channel region. DRAM devices and methods are also provided.Type: ApplicationFiled: May 31, 2007Publication date: July 17, 2008Inventors: Jin-Woo Lee, Tae-Young Chung
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Publication number: 20080169494Abstract: A structure and method of forming a body contact for a semiconductor-on-insulator trench device. The method including: forming set of mandrels on a top surface of a substrate, each mandrel of the set of mandrels arranged on a different corner of a polygon and extending above the top surface of the substrate, a number of mandrels in the set of mandrels equal to a number of corners of the polygon; forming sidewall spacers on sidewalls of each mandrel of the set of mandrels, sidewalls spacers of each adjacent pair of mandrels merging with each other and forming a unbroken wall defining an opening in an interior region of the polygon, a region of the substrate exposed in the opening; etching a contact trench in the substrate in the opening; and filling the contact trench with an electrically conductive material to form the contact.Type: ApplicationFiled: March 24, 2008Publication date: July 17, 2008Inventors: Kangguo Cheng, Ramachandra Divakaruni
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Publication number: 20080169495Abstract: The embodiments of the invention provide a structure, method, etc. for a fin differential MOS varactor diode. More specifically, a differential varactor structure is provided comprising a substrate with an upper surface, a first vertical anode plate, and a second vertical anode plate electrically isolated from the first vertical anode plate. Moreover, a semiconductor fin comprising a cathode is between the first vertical anode plate and the second vertical anode plate, wherein the semiconductor fin, the first vertical anode plate, and the second vertical anode plate are each positioned over the substrate and perpendicular to the upper surface of the substrate.Type: ApplicationFiled: January 17, 2007Publication date: July 17, 2008Inventors: Bradley A. Orner, Edward J. Nowak, Robert M. Rassel
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Publication number: 20080169496Abstract: Some embodiments include methods of forming a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate. Some embodiments include utilization of an etch comprising HBr and O2 to extend a pattern through a carbon-containing layer. The patterned carbon-containing layer may be used to pattern NAND cell unit gates. Some embodiments include structures having a patterned carbon-containing layer defining a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate.Type: ApplicationFiled: January 12, 2007Publication date: July 17, 2008Inventors: David J. Keller, Hongbin Zhu, Alex J. Schrinsky
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Publication number: 20080169497Abstract: A non-volatile semiconductor memory includes memory cell transistors arranged in a matrix, wherein each of the memory cell transistors is a depletion mode MIS transistor.Type: ApplicationFiled: August 1, 2007Publication date: July 17, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Naohisa Iino, Yasuhiko Matsunaga, Fumitaka Arai
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Publication number: 20080169498Abstract: A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.Type: ApplicationFiled: March 25, 2008Publication date: July 17, 2008Applicant: ACTEL CORPORATIONInventors: Fethi Dhaoui, John McCollum, Frank Hawley, Leslie Wilkinson
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Publication number: 20080169499Abstract: A flash memory includes a memory cell portion and peripheral circuit portion. The memory cell portion has first gate dielectric films formed on the main surface of a semiconductor substrate and floating gate electrode layers formed on the first gate dielectric films. The peripheral circuit portion has second gate dielectric films formed on the main surface of the semiconductor substrate and gate electrode layers formed on the second gate dielectric films. The penetration depth of a bird's beak formed in contact with the upper and bottom surfaces of the second gate dielectric film is larger than the penetration depth of a bird's beak formed in contact with the upper and bottom surfaces of the first gate dielectric film.Type: ApplicationFiled: January 16, 2008Publication date: July 17, 2008Inventor: Masahiro KIYOTOSHI
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Publication number: 20080169500Abstract: A non-volatile transistor memory array having memory cells, each with a control transistor and a floating gate memory transistor. The cells are arranged in symmetric quadrants with active regions appearing as tic-tac-toe style strips having a central shared drain erase region. Within the drain erase region is an avalanche diode that has overlying regions of four floating gates of the memory transistors and serving to supply erase current of holes and electrons to addressed floating gates. The cells have four voltage lines or contacts, including a wordline and a bitline, a common source line and a substrate contact that are used both for addressing and for controlling distributed device capacitance in a manner that treats the floating gate as one plate of a virtual capacitor, the other plate being distributed device capacitance in the control transistor, and the memory transistor including the four voltage lines or contacts.Type: ApplicationFiled: January 16, 2007Publication date: July 17, 2008Applicant: ATMEL CORPORATIONInventor: Bohumil Lojek
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Publication number: 20080169501Abstract: A flash memory device including a hybrid structure charge trap layer and a related method of manufacture are disclosed. The charge trap layer includes at least one hybrid trap layer including a first trap layer formed from a first material having a first band gap energy, and a plurality of nano dots separated from each other such that each nano dot is at least partially encircled by the first trap layer, the plurality of nano dots being formed from a second material having a second band gap energy lower than the first band gap energy.Type: ApplicationFiled: July 12, 2007Publication date: July 17, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jun-kyu YANG, Seung-jae BAIK, Jin-tae NOH, Seung-hyun LIM, Kyong-hee JOO, Zong-liang HUO
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Publication number: 20080169502Abstract: Methods for fabricating dual bit flash memory devices are provided. Method steps include forming a charge trapping layer overlying a substrate and fabricating two insulating members overlying the charge trapping layer. A polycrystalline silicon layer is provided overlying the charge trapping layer and about sidewalls of the insulating members. Sidewall spacers are formed overlying the polycrystalline silicon layer and about the sidewalls of the insulating members. A portion of the first polycrystalline silicon layer and a first portion of the charge trapping layer are removed. A first insulating layer is conformally deposited overlying the insulating members and the substrate. A gate spacer is formed between the two insulating members and overlying the first insulating layer. The two insulating members are removed and the charge trapping layer is etched to form charge storage nodes. Impurity dopants are implanted into the substrate to form impurity-doped bitline regions within the substrate.Type: ApplicationFiled: March 24, 2008Publication date: July 17, 2008Inventors: Amol Ramesh Joshi, Ning Cheng, Minghao Shen
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Publication number: 20080169503Abstract: A semiconductor structure is provided, which includes multiple sections arranged along a longitudinal axis. Preferably, the semiconductor structure comprises a middle section and two terminal sections located at opposite ends of the middle section. A semiconductor core having a first dopant concentration preferably extends along the longitudinal axis through the middle section and the two terminal sections. A semiconductor shell having a second, higher dopant concentration preferably encircles a portion of the terminal sections, but not at the middle section, of the semiconductor structure. It is particularly preferred that the semiconductor structure is a nanostructure having a cross-sectional dimension of not more than 100 nm.Type: ApplicationFiled: January 11, 2007Publication date: July 17, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joerg Appenzeller, Supratik Guha, Emanuel Tutuc
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Publication number: 20080169504Abstract: Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C4F6 and C4F8. The recessed materials may be within isolation regions, and the recessing may be utilized to form trenches for receiving gatelines. Some embodiments include structures having an island of semiconductor material laterally surrounded by electrically insulative material. Two gatelines extend across the insulative material and across the island of semiconductor material. One of the gatelines is recessed deeper into the electrically insulative material than the other.Type: ApplicationFiled: January 12, 2007Publication date: July 17, 2008Inventors: Larson Lindholm, Aaron R. Wilson, David K. Hwang
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Publication number: 20080169505Abstract: A trench MOSFET with copper metal connections is disclosed. A substrate is provided with a plurality of trenches. A gate oxide layer is formed on the sidewalls and bottoms of the trenches. A conductive layer is filled in the trenches to be used as a gate of the MOSFET. A plurality of source and body regions are formed in an epi layer. An insulating layer is formed on the epi layer and formed with a plurality of metal contact holes therein for contacting respective source and body regions. A barrier metal layer is formed on the sidewalls and bottoms of the metal contact holes in direct contact with respective source and body regions. A metal contact layer is filled in the metal contact holes. A copper metal layer is formed on another barrier metal layer on the insulating layer connected to respective source regions through the metal contact layer to form metal connections of the MOSFET.Type: ApplicationFiled: August 30, 2007Publication date: July 17, 2008Inventor: Fu-Yuan Hsieh
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Publication number: 20080169506Abstract: A power actuator of the emitter-switched type is described, the power actuator comprising at least one high voltage bipolar transistor and a low voltage DMOS transistor connected in cascode configuration between a collector terminal of the bipolar transistor and a source terminal of the DMOS transistor and having respective control terminals. Advantageously, the power actuator further comprises at least a Zener diode, inserted between the source terminal of the DMOS transistor and the control transistor of the bipolar transistor.Type: ApplicationFiled: January 8, 2008Publication date: July 17, 2008Applicant: STMICROELECTRONICS S.R.L.Inventors: Cesare Ronsisvalle, Vincenzo Enea
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Publication number: 20080169507Abstract: A semiconductor resistor, method of making the resistor and method of making an IC including resistors. Buried wells are formed in the silicon substrate of a silicon on insulator (SOI) wafer. At least one trench is formed in the buried wells. Resistors are formed along the sidewalls of the trench and, where multiple trenches form pillars, in the pillars between the trenches by doping the sidewalls with an angled implant. Resistor contacts are formed to the buried well at opposite ends of the trenches and pillars, if any.Type: ApplicationFiled: March 24, 2008Publication date: July 17, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Edward J. Nowak, Richard Q. Williams
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Publication number: 20080169508Abstract: A method is provided for fabricating a semiconductor-on-insulator (“SOI”) substrate including (i) an SOI layer of monocrystalline silicon separated from (ii) a bulk semiconductor layer by (ii) a buried oxide (“BOX”) layer, the BOX layer including a layer of doped silicate glass. In such method, a sacrificial stressed layer is deposited to overlie the SOI layer and trenches are etched through the sacrificial stressed layer and into the SOI layer. The SOI substrate is heated with the sacrificial stressed layer sufficiently to cause the glass layer to soften, thereby causing the sacrificial stressed layer to apply stress to the SOI layer to form a stressed SOI layer. A dielectric material can then be deposited in the trenches to form isolation regions contacting peripheral edges of the stressed SOI layer, the isolation regions extending from a major surface of the stressed SOI layer towards the BOX layer. The sacrificial stressed layer can then be removed to expose the stressed SOI layer.Type: ApplicationFiled: January 11, 2007Publication date: July 17, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dureseti Chidambarrao, William K. Henson, Yaocheng Liu
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Publication number: 20080169509Abstract: A semiconductor device includes a first well of a first conductive type formed in a surface portion of a semiconductor substrate; a first contact group connected with the first well; a second well of a second conductive type formed to surround the first well in the surface portion of the semiconductor substrate; a first guard ring provided on the second well; a second contact group connected with the first guard ring; a third well of the first conductive type formed to surround the second well in the surface portion of the semiconductor substrate; a second guard ring provided on the third well; and a third contact group connected with the second guard ring. The first to third wells form a transistor, and a current flowing through the transistor is suppressed.Type: ApplicationFiled: January 15, 2008Publication date: July 17, 2008Applicant: NEC ELECTRONICS CORPORATIONInventor: Masanori Tanaka
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Publication number: 20080169510Abstract: In an integrated circuit comprising both PMOSFETs and NMOSFETs, carrier mobility is enhanced on both types of FETs using dual stressed films. The adverse impact of having both layers of stressed films along the boundary between different types of films is eliminated by utilizing self-alignment of the edges of a second stressed film to a preexisting edge of a first stressed film. At the boundary between the two stressed films, one stressed film abuts another but no stressed film overlies another stressed film. By avoiding any overlap of stressed films, the stress exerted on the MOSFET channels is maximized.Type: ApplicationFiled: January 17, 2007Publication date: July 17, 2008Applicant: International Business Machines CorporationInventors: Mahender Kumar, Huilong Zhu
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Publication number: 20080169511Abstract: The invention relates to a method of fabricating a CMOS device, comprising providing a semiconductor substrate (101) having therein a layer of insulating material (102), the method comprising providing a layer (106) of a first material over the insulating layer (102), the thickness of the layer (106) of the first material being less in a first region (103) for supporting a first active device than in a second region (104) for supporting a second active device. A layer (107) of a second material is then deposited over the layer (106) of a first material, and the structure is then subjected to a thermal treatment to alloy the first and second materials. The portion of the layers over the first region is entirely alloyed, whereas the portion of the layers over the second region is not, so that a portion (109) of the layer (106) of the first material remains.Type: ApplicationFiled: August 1, 2005Publication date: July 17, 2008Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.Inventors: Markus Muller, Peter Stolk
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Publication number: 20080169512Abstract: A non-planar tri-gate p-MOS transistor structure with a strained channel region and a non-planar tri-gate integrated strained complimentary metal-oxide-semiconductor (CMOS) structure are described. A relaxed Si1-x Gex layer is formed on the silicon-on-isolator (SOI) substrate. The relaxed Si1-x Gex layer is patterned and subsequently etched to form a fin on the oxide. The compressively stressed Si1-y Gey layer, having the Ge content y higher than the Ge content x in the relaxed Si1-x Gex layer, is epitaxially grown on the fin. The Si1-y Gey layer covers the top and two sidewalls of the fin. The compressive stress in the Si1-y Gey layer substantially increases the hole mobility in a channel of the non-planar tri-gate p-MOS transistor structure.Type: ApplicationFiled: December 20, 2007Publication date: July 17, 2008Inventors: Brian S. Doyle, Suman Datta, Been-Yih Jin, Nancy M. Zelick, Robert Chau
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Publication number: 20080169513Abstract: Integrated circuits (ICs) utilize bipolar transistors in electro-static discharge (ESD) protection circuits to shunt discharge currents during ESD events to protect the components in the ICs. Bipolar transistors are subject to non-uniform current crowding across the emitter-base junction during ESD events, which results in less protection for the IC components and degradation of the bipolar transistor. This invention comprises multiple contact islands (126) on the emitter (116) of a bipolar transistor, which act to spread current uniformly across the emitter-base junction. Also included in this invention is segmentation of the emitter diffused region to further improve current uniformity and biasing of the transistor. This invention can be combined with drift region ballasting or back-end ballasting to optimize an ESD protection circuit.Type: ApplicationFiled: September 28, 2007Publication date: July 17, 2008Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Marie Denison
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Publication number: 20080169514Abstract: A resistor structure for an integrated circuit includes a first set of contacts connected between a semiconductor layer and a first conductive layer; and a second set of plugs connected between the first conductive layer and a second conductive layer, wherein the first set of contacts and the second set of plugs are coupled together as a first resistor segment to provide a predetermined resistance for the integrated circuit.Type: ApplicationFiled: January 11, 2007Publication date: July 17, 2008Inventors: Fu-Lung Hsueh, Sung-Chieh Lin
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Publication number: 20080169515Abstract: Semiconductor devices are disclose that include a first doped region and a second doped region spaced apart from each other and defined within a same well of a semiconductor substrate. A gate insulating layer and a gate electrode are stacked on a channel region between the first and second doped regions. Spacers are on opposite sidewalls of gate electrode. A first surface metal silicide layer extends across a top surface of the first doped region adjacent to the spacer. A second surface metal silicide layer extends across a top surface of the second doped region adjacent to the spacer. At least one insulation layer extends across the semiconductor substrate including the first and second surface metal silicide layers. A first contact plug extends through the insulation layer and contacts the first surface metal silicide layer. A second contact plug extends through the insulation layer, the second surface metal silicide layer, and the second doped region into the well within the semiconductor substrate.Type: ApplicationFiled: January 2, 2008Publication date: July 17, 2008Inventor: Sun-Ha Hwang
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Publication number: 20080169516Abstract: A semiconductor device is disclosed for alleviating well proximity effects. The semiconductor device comprises a well in a substrate; and a transistor with an active region and a gate of 0.13 um or less in gate length, wherein the gate is entirely within or extended to outside of the well, and a minimum spacing between an edge of the active region and an edge of the well is at least 3 times the gate length.Type: ApplicationFiled: January 17, 2007Publication date: July 17, 2008Inventor: Shine Chung
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Publication number: 20080169517Abstract: A method for manufacturing electronic devices on a semiconductor substrate with wide band gap that includes the steps of: forming a screening structure on the semiconductor substrate to include at least a dielectric layer that leaves a plurality of areas of the semiconductor substrate exposed, carrying out at least a ion implantation of a first type of dopant in the semiconductor substrate to form at least a first implanted region, carrying out at least a ion implantation of a second type of dopant in the semiconductor substrate to form at least a second implanted region inside the at least a first implanted region, carrying out an activation thermal process of the first type and second type of dopant with low thermal temperature suitable to complete the formation of the at least first and second implanted regions without diffusing the at least first and at least second type dopants in the substrate.Type: ApplicationFiled: January 8, 2008Publication date: July 17, 2008Applicant: STMICROELECTRONICS S.R.L.Inventors: Ferrucio Frisina, Mario Giuseppe Saggio, Angelo Magri
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Publication number: 20080169518Abstract: Disclosed is semiconductor structure that incorporates a field shield below a semiconductor device (e.g., a field effect transistor (FET) or a diode). The field shield is sandwiched between upper and lower isolation layers on a wafer. A local interconnect extends through the upper isolation layer and connects the field shield to a selected doped semiconductor region of the device (e.g., a source/drain region of a FET or a cathode or anode of a diode). Current that passes into the device, for example, during back-end of the line charging, is shunted by the local interconnect away from the upper isolation layer and down into the field shield. Consequently, an electric charge is not allowed to build up in the upper isolation layer but rather bleeds from the field shield into the lower isolation layer and into the substrate below.Type: ApplicationFiled: January 15, 2007Publication date: July 17, 2008Inventors: William F. Clark, Edward J. Nowak
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Publication number: 20080169519Abstract: An electronic device includes a semiconductor substrate of a first conductivity type and a drain layer adjacent the semiconductor substrate and having a plurality of drains. The drain layer includes a first semiconductor layer of the first conductivity type adjacent the semiconductor substrate, and at least one second semiconductor layer of a second conductivity type adjacent the first semiconductor layer. Moreover, a plurality of first column regions of the first conductivity type extends through the at least one second semiconductor layer to contact the first semiconductor layer. A plurality of second column regions of the second conductivity type delimits the plurality of first column regions. Furthermore, a plurality of body regions of the second conductivity type are adjacent respective ones of the plurality of second column regions.Type: ApplicationFiled: February 12, 2008Publication date: July 17, 2008Applicant: STMicroelectronics S.r.l.Inventors: Monica Micciche, Antonio Giuseppe Grimaldi, Luigi Arcuri
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Publication number: 20080169520Abstract: In order to provide a dielectric film which can avoid both boron leakage and an increase of the leak current, a semiconductor apparatus which has the dielectric film, a production method of the dielectric film and a production method of the semiconductor apparatus, a dielectric film layered product is applied which includes: a semiconductor substrate (2); a first hafnium-containing silicon oxide nitride layer (3a) made from a microcrystalline structure; a second hafnium-containing silicon oxide nitride layer (3b) made from a non-crystalline structure; and a layered film which is made from the first and second hafnium-containing silicon oxide nitride layers that are layered on the semiconductor substrate, and which has a nitrogen ratio of 15-40 atomic percent.Type: ApplicationFiled: January 11, 2008Publication date: July 17, 2008Applicant: ELPIDA MEMORY, INC.Inventors: Takakazu KIYOMURA, Takuo Ohashi
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Publication number: 20080169521Abstract: A MEMS device is encapsulated in a carbon dioxide environment, which effectively insulates the MEMS device against arcing in high voltage applications. The carbon dioxide environment may have a pressure of between about 0.2 atm and about 4 atm. Carbon dioxide is shown to be more effective than other insulating gases such as sulfur hexafluoride in preventing arcing for applications having dimensions on the order of microns.Type: ApplicationFiled: January 12, 2007Publication date: July 17, 2008Applicant: Innovative Micro TechonologyInventors: John S. Foster, Alok Paranjpye, Jeffery F. Summers, Douglas L. Thompson
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Publication number: 20080169522Abstract: A moving element includes at least a substrate including a support, a moving body, and an elastic body connecting the moving body to the support. The support includes a buried film formed in it. The buried film of the support is formed only near end faces of the support that faces the moving body.Type: ApplicationFiled: January 15, 2008Publication date: July 17, 2008Applicant: OLYMPUS CORPORATIONInventor: Michitsugu ARIMA
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Publication number: 20080169523Abstract: An imaging optical module is designed to be placed in front of an optical image sensor of a semiconductor component. The module includes at least one element which has a refractive index that varies between its optical axis and its periphery, over at least an annular part and/or over its central part. The element may be a tablet in front of the semiconductor sensor or a lens in front of the semiconductor sensor. The direction of variation in refractive index may be oppositely oriented with respect to the table and lens.Type: ApplicationFiled: December 27, 2007Publication date: July 17, 2008Applicant: STMicroelectronics S.A.Inventors: Emmanuelle Vigier-Blanc, Guillaume Cassar
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Publication number: 20080169524Abstract: A method for forming an image sensor is provided. The method includes providing a semiconductor substrate having a pixel region and a peripheral circuit region, forming a photoelectric transformation section at the semiconductor substrate of the pixel region, forming a plurality of interlayer dielectrics over the semiconductor substrate with interconnections interposed therebetween, forming a passivation layer, partially patterning the passivation layer at the peripheral circuit region to form a via hole exposing the interconnection and removing the passivation layer and the underlying interlayer dielectric at the pixel region. The method further includes forming a conductive layer to fill the via hole and etching the conductive layer to remove the conductive layer at the pixel region and form a via plug and a conductive pad at the peripheral circuit region. The via plug fills the via hole and the conductive pad protrudes outwardly from the via hole.Type: ApplicationFiled: March 13, 2008Publication date: July 17, 2008Inventor: KI-HONG KIM
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Publication number: 20080169525Abstract: A chip device with a number of individually powered parts, such as photoreceptors. A mesh is provided to provide power to the individual photoreceptors. The mesh may be provided for ground and power and/or both. The mesh may be on different layers, so that one portion of the mesh is exactly over the other portion of the mesh. The mesh takes up a portion of real estate on the chip in between the individual photoreceptors, in locations where image sensing parts cannot be located. In an embodiment, the mesh can be intentionally broken at various locations to optimize the path length.Type: ApplicationFiled: January 17, 2007Publication date: July 17, 2008Inventors: Lin Ping Ang, Steven Huang
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Publication number: 20080169526Abstract: A power semiconductor device is provided having a field plate that employs a thick metal film in an edge termination structure and which permits edge termination structure width reduction even with large side etching or etching variation, which exhibits superior long-term forward blocking voltage capability reliability, and which allows minimal forward blocking voltage capability variation. The edge termination structure has multiple ring-like p-type guard rings, a first insulating film covering the guard rings, and ring-like field plates, provided via the first insulating film atop the guard rings. The field plates have a polysilicon film and a thicker metal film. The polysilicon film is provided on a first guard ring via first insulating film, and a dual field plate made of the polysilicon film and metal film is provided on a second guard ring. The dual field plate is stacked via a second insulating film. The first and second guard rings alternate.Type: ApplicationFiled: January 11, 2008Publication date: July 17, 2008Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.Inventors: Hiroki WAKIMOTO, Masahito OTSUKI, Takashi SHIIGI
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Publication number: 20080169527Abstract: The invention relates to a semiconductor device (10) with a semiconductor body (1) comprising a high-ohmic semiconductor substrate (2) which is covered with a dielectric layer (3) containing charges, on which dielectric layer one or more passive electronic components (4) comprising conductor tracks (4) are present, and at the location of the passive elements (4) a semiconductor region (5) is present at the interface between the semiconductor substrate (2) and the dielectric layer (3, 4), a first conductivity-type conducting channel induced in the semiconductor substrate (2) by the charges being interrupted by, and at the location of, the semiconductor region (5). According to the invention, the semiconductor region (5) is monocrystalline and of a second conductivity type, opposite to the first conductivity type. In this way the charge of an induced channel is locally compensated by the charge of the semiconductor regions (5).Type: ApplicationFiled: April 12, 2005Publication date: July 17, 2008Applicant: KONINKLIJKE PHILIPS ELECTRONICSInventor: Wibo Daniel Van Noort
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Publication number: 20080169528Abstract: This invention provides a hybrid orientation (HOT) semiconductor-on-insulator (SOI) structure having an isolation region, e.g. a shallow trench isolation region (STI), and a method for forming the STI structure that is easy to control. The method of forming the isolation region includes an etch of the insulating material, selective to the semiconductor material, followed by an etch of the semiconductor material, selective to the insulating material, and then filling any high aspect ratio gaps with a CVD oxide, and filling the remainder of the STI with an HDP oxide.Type: ApplicationFiled: January 16, 2007Publication date: July 17, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Byeong Y. Kim, Munir D. Naeem, Frank D. Tamweber, Xiaomeng Chen
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Publication number: 20080169529Abstract: An eFuse, includes: a substrate and an insulating layer disposed on the substrate; a first layer including a single crystal or polycrystalline silicon disposed on the insulating layer; a second layer including a single crystal or polycrystalline silicon germanium disposed on the first layer, and a third layer including a silicide disposed on the second layer. The Ge has a final concentration in a range of approximately five percent to approximately twenty-five percent.Type: ApplicationFiled: January 12, 2007Publication date: July 17, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Deok-Kee Kim, Dureseti Chidambarrao, William K. Henson, Chandrasekharan Kothandaraman
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Publication number: 20080169530Abstract: Multilayer ceramic chip capacitors which satisfy X8R requirements and which are compatible with reducing atmosphere sintering conditions so that non-noble metals such as nickel and nickel alloys thereof may be used for internal and external electrodes are made in accordance with the invention. The capacitors exhibit desirable dielectric properties (high capacitance, low dissipation factor, high insulation resistance), excellent performance on highly accelerated life testing, and very good resistance to dielectric breakdown. The dielectric layers comprise a barium titanate base material doped with other metal oxides such as BaO, Y2O3, ZrO2, SiO2, MgO, MnO, MoO3, CaO, Lu2O3, Yb2O3, or WO3 in various combinations.Type: ApplicationFiled: January 17, 2007Publication date: July 17, 2008Applicant: FERRO CORPORATIONInventors: Gerhardus W. Koebrugge, Knuth Albertsen, Willibrordus J. L. M. J. Coppens
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Publication number: 20080169531Abstract: A method of forming a microelectronic device includes forming a groove structure having opposing sidewalls and a surface therebetween on a substrate to define a nano line arrangement region. The nano line arrangement region has a predetermined width and a predetermined length greater than the width. At least one nano line is formed in the nano line arrangement region extending substantially along the length thereof and coupled to the surface of the groove structure to define a nano line structure. Related devices are also discussed.Type: ApplicationFiled: September 11, 2007Publication date: July 17, 2008Inventors: ZongLiang Huo, Subramanya Mayya, Xiaofeng Wang, In-Seok Yeo
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Publication number: 20080169532Abstract: A III nitride single-crystal manufacturing method in which a liquid layer (3) of 200 ?m or less thickness is formed in between a substrate (1) and a III nitride source-material baseplate (2), and III nitride single crystal (4) is grown onto the face (1s) on the liquid-layer side of the substrate (1). Herein, the substrate (1) in at least a superficial layer (1a) on the liquid-layer side may be formed of a III nitride single crystal, while the III nitride source-material baseplate (2) can be formed of a III nitride polycrystal. Further, the substrate (1) in at least a superficial layer (1a) on the liquid-layer side, and the III nitride source-material baseplate (2) can be formed of a III nitride single crystal, while the face (1s) on the liquid-layer side of the substrate (1) can be made a III-atom surface, and the face (2s) on the liquid-layer side of the III nitride source-material baseplate (2) can be made a nitrogen-atom surface.Type: ApplicationFiled: July 13, 2005Publication date: July 17, 2008Applicant: Sumitomo Electric IndustriesInventor: Seiji Nakahata
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Publication number: 20080169533Abstract: A novel die saw crack stopper that consists of placing formations into the scribe line of multiple metal layers of a die. These formations comprise multiple right-angle shapes that are interconnected at right angles. In an embodiment the formations have an overall shape that has a special meaning, such as the Chinese symbol for “Stop”, , a modified Yin-Yang design, the Buddhist “Wan” symbol, the Christian Cross, or the like. The formations in a single layer can be placed such that they are located adjacent to each other along an axis that runs substantially parallel with the scribe line. These formations can also be connected to other formations in other metal layers located either above or below the formation.Type: ApplicationFiled: January 17, 2007Publication date: July 17, 2008Inventors: Shin-Puu Jeng, Shih-Hsun Hsu
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Publication number: 20080169534Abstract: A method is provided for reduced defect such as void free or reduced void Si or SiGe deposition in a micro-feature on a patterned substrate. The micro-feature includes a sidewall and the patterned substrate contains an isolation layer on the field area and on the sidewall and bottom of the micro-feature. The method includes forming a Si or SiGe seed layer at the bottom of the micro-feature, and at least partially filling the micro-feature from the bottom up by selectively growing Si or SiGe onto the Si or SiGe seed layer. According to one embodiment, the Si or SiGe seed layer is formed by depositing a conformal Si or SiGe layer onto the patterned substrate, removing the Si or SiGe layer from the field area, heat treating the Si or SiGe layer in the presence of H2 gas to transfer at least a portion of the Si or SiGe layer from the sidewall to the bottom of the micro-feature, and etching Si or SiGe residue from the field area and the sidewall.Type: ApplicationFiled: January 11, 2007Publication date: July 17, 2008Applicant: TOKYO ELECTRON LIMITEDInventors: Anthony Dip, John Gumpher, Allen John Leith, Seungho Oh
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Publication number: 20080169535Abstract: The present invention provides structures and methods for providing multiple parallel V-shaped faceted grooves with sub-lithographic widths on a semiconductor substrate for enhanced performance MOSFETs. A self-aligning self-assembling material is used to pattern multiple parallel sub-lithographic lines. By employing an anisotropic etch that produces crystallographic facets on a semiconductor surface, multiple adjoining parallel V-shaped grooves with sub-lithographic groove widths are formed. While providing enhanced mobility for the MOSFET, the width of the MOSFET is not limited by the depth of focus in subsequent lithographic steps or the thickness of semiconductor layer above a BOX layer due to the sub-lithographic widths of the V-shaped grooves and the consequent reduction in the variation of the vertical profile. Also, the MOSFET has a well defined threshold voltage due to the narrow widths of each facet.Type: ApplicationFiled: January 12, 2007Publication date: July 17, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shahid A. Butt, Thomas W. Dyer, Oh-Jung Kwon, Jack A. Mandelman, Haining S. Yang
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Publication number: 20080169536Abstract: A semiconductor device may include a semiconductor chip including a signal terminating resistor coupled between a signal input pad and a first ground voltage pad, a semiconductor package including a signal input terminal and a first ground voltage terminal, the signal input terminal being electrically coupled to the signal input pad of the semiconductor chip and the first ground voltage terminal being electrically coupled to the first ground voltage pad of the semiconductor chip, a capacitor and a resistor that are coupled between the signal input terminal and the first ground voltage terminal, and a first inductor realized by coupling the signal input terminal and the signal input pad.Type: ApplicationFiled: January 9, 2008Publication date: July 17, 2008Inventor: Dae-Hyun Chung
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Publication number: 20080169537Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.Type: ApplicationFiled: March 12, 2008Publication date: July 17, 2008Inventors: Ryoichi KAJIWARA, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
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Publication number: 20080169538Abstract: A semiconductor device of the present invention includes a semiconductor chip, a die pad to which the semiconductor chip is bonded with solder to be mounted thereon, a plurality of leads electrically conducted to the semiconductor chip, a stress reducing layer that is provided on a rear face of the die pad opposite to a face of the die pad on which the semiconductor chip is mounted and that reduces stress applied to the semiconductor chip, and a sealing body for sealing at least the semiconductor chip.Type: ApplicationFiled: January 11, 2008Publication date: July 17, 2008Applicant: Rohm Co., Ltd.Inventors: Yasumasa Kasuya, Motoharu Haga, Shoji Yasunaga