Abstract: A package for a semiconductor integrated circuit die comprises a redistributed layer formed over a first barrier layer electrically connected to a bonding pad of a die. A second barrier layer is formed over the redistributed layer. A multi-metal layer is formed over the second barrier layer for coupling to a solder ball, wherein the multi-metal layer has an extending part that extends outside a second opening over the upper of the second dielectric layer to prevent tin infiltration from the solder ball to the redistribution layer.

Abstract: A lead frame structure of a light emitting diode is disclosed. The lead frame structure comprises a bonding zone, two wing-shaped reflective surfaces, a first electrode lead, and a second electrode lead. The first electrode lead and the second electrode lead are respectively connected to the bonding zone. The bonding zone bonds the light emitting diode. The reflective surfaces are formed on both sides of the bonding zone. A predetermined angle is formed between the bonding zone and the wing-shaped reflective surfaces for reflecting the side light emitted from the light emitting diode towards a predetermined direction.

Abstract: A memory card comprising a leadframe having a plurality of contacts. Electrically connected to the leadframe is at least one semiconductor die. A body at least partially encapsulates the leadframe and includes opposed top and bottom surfaces, an opposed pair of longitudinal sides, and an opposed pair of lateral sides. The contacts of the leadframe are exposed in the bottom surface of the body and extend to one of the lateral sides thereof.

Abstract: A semiconductor device having a multilayer wiring structure and a manufacturing method thereof are provided. A semiconductor device and a manufacturing method thereof are provided in which the reliability and the manufacturing yield are high and the design constraint is small. Wirings are formed on a substrate. Low dielectric constant films are formed around the wirings. Reinforcement insulating films are formed in a dielectric material of a larger elastic modulus than that of a formation material of the low dielectric constant films and are arranged to overlap with the wirings when viewed perpendicularly to a substrate surface. Reinforcement insulating films are arranged to intersect with the wirings.

Abstract: A two dimensional stacking structure for integrated chip stacking on a printed circuit board having a controller electrically coupling on the printed circuit board, comprising a first integrated circuit package, a second integrated circuit package and two interposers. The first integrated circuit package is located beside the controller and electrically coupled on the printed circuit board, and has first leads. The second integrated circuit package is located on the controller, and has second leads. The two interposers having first metal contacts attaching to the corresponding first leads, second metal contacts attaching to the corresponding second leads, and circuit traces extending from the first metal contacts to the corresponding second metal contacts providing electrical communication between the first integrated circuit package and the second integrated package. The two dimensional stacking structure may be applied to a circuit module to decrease the profile of the circuit module.

Abstract: A method of fabricating a semiconductor device includes: mounting a semiconductor chip on a substrate; forming an upper connection terminal on a side of the substrate on which the semiconductor chip is mounted; forming a resin seal portion that seals the semiconductor chip and the upper connection terminal so that an upper surface of the upper connection terminal is exposed; and shaping the upper connection terminal so that the upper surface of the upper connection terminal becomes lower than an upper surface of the resin seal portion.

Abstract: A stacked structure of semiconductor devices may include a plurality of stacked semiconductor devices, each having an upper surface and a lower surface and one or more via electrodes protruding from the upper surface to the lower surface. The via-electrodes may have upper parts (heads) protruding from the upper surface and lower parts (ends) protruding from the lower surface. The stacked semiconductor devices may be electrically connected to each other through the via-electrodes. A first adhesive film (e.g., patternable material) and a second adhesive film (e.g. puncturable material) may be formed between the stacked semiconductor devices. The stacked structure of semiconductor devices may be mounted on the upper surface of a printed circuit board (PCB) having a mount-specific adhesive film to form a semiconductor device package. The mounted stacked structure and the upper surface of the PCB may be further covered with a molding material.

Abstract: A stack type semiconductor chip package includes a first wafer mold, a protection substrate, and a second wafer mold that are stacked in a wafer level process. The first wafer mold includes a first chip having first pads and a first mold layer encapsulating the first chip. The protection substrate is placed on the first wafer mold, is mechanically bonded with the first wafer mold using a first adhesive layer, and includes wiring layers facing the first pads. The second wafer mold is placed under the first wafer mold, is mechanically bonded with the first wafer mold using a second adhesive layer, and includes a second chip having second pads, and a second mold layer encapsulating the second chip. First vias electrically connect the wiring layers of the protection substrate with the second pads. Second vias electrically connect the wiring layers of the protection substrate with external connection terminals.

Abstract: Provided is a semiconductor module with enhanced joint reliability. The semiconductor module includes a package, a printed circuit board (PCB), and conductive joint structures for electrically connecting the package with the PCB. The PCB includes at least one buffer layer that can alleviate the thermal deformation of the semiconductor module due to a difference in the coefficient of thermal expansion between the PCB and the conductive joint structures.

Abstract: Example embodiments relate to a semiconductor package having a semiconductor chip provided in a substrate and a method of fabricating the same. The semiconductor package may include a semiconductor substrate having a first through hole and a plurality of second through holes spaced apart from the first through hole. A semiconductor chip having a plurality of pads may be disposed in the first through hole. Solder balls electrically connected to the pads may be attached to end portions of the second through holes. A plurality of the above semiconductor substrates may be stacked to form a multi-chip package.

Abstract: An integrated circuit package system including providing a base substrate, attaching a base integrated circuit on the base substrate, attaching a core substrate over the base integrated circuit, attaching a substrate electrical connector between the core substrate and the base substrate, and applying an encapsulant having the core substrate partially exposed over the base integrated circuit.

Abstract: A thin, planar semiconductor device having electrodes on both surfaces is disclosed. This semiconductor device is provided with an IC chip and a wiring layer having one side that is electrically connected to surface electrodes of the IC chip. On this surface of the wiring layer, conductive posts are provided on wiring of the wiring layer, and an insulating resin covers all portions not occupied by the IC chip and conductive posts. The end surfaces of the conductive posts are exposed from the insulating resin and are used as first planar electrodes. In addition, a resist layer is formed on the opposite surface of the wiring layer. Exposed portions are formed in the resist layer to expose desired wiring portions of the wiring layer. These exposed portions are used as second planar electrodes. Stacking semiconductor devices of this construction enables an improvement in the integration of semiconductor integrated circuits.

Abstract: An IC package with a near-substrate-scale die-attaching layer includes a substrate, a near-substrate-scale die-attaching layer, a chip, a plurality of bonding wires, an encapsulant, and a plurality of solder balls. A plurality of ball pads are formed on the bottom surface of the substrate for solder ball placement. The near-substrate-scale die-attaching layer is formed on the top surface of the substrate covering most of the top surface above the ball pads without extending to the edges of the top surface. The active surface of the chip is attached to a first portion of the near-substrate-scale die-attaching layer and is electrically connected to the substrate by the bonding wires. The encapsulant is formed above the top surface of the substrate to cover a second portion of the near-substrate-scale die-attaching layer extending between the substrate and the encapsulant.

Abstract: The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the chip mounting portion, to seal the semiconductor chips. According to an aspect of the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, by which it is possible to reduce the size of the package and to prevent the generation of an unfilled portion in a resin sealing portion or a filler-removed portion or to prevent the exposure of wire from the resin sealing portion.

Abstract: A method of fabricating a micro-electromechanical system (MEMS) device from a complementary metal oxide semiconductor (CMOS) having a silicon layer and an oxide layer, the oxide layer being on the silicon layer and containing at least one metal layer. The method includes etching the silicon layer of the CMOS to form a trench through the silicon layer to expose a portion of the oxide layer. The method also includes depositing a silicon oxide layer on the silicon layer and on an exposed portion of the oxide layer within the trench. Additionally, the method includes etching the silicon oxide layer deposited on the exposed portion of the oxide layer to expose a portion of the metal within the oxide layer. The method further includes electrodepositing a conductor within the trench such that the conductor extends through the trench to the exposed portion of the metal and etching the silicon layer of the CMOS to remove portions of the silicon layer adjacent the conductor.

Abstract: A semiconductor device having a plastic package with a linear array of metal lands (202, 212) with parallel perimeter portions (203a, 213a). Pairs of adjacent lands have their facing parallel perimeter portions oriented in parallel, defining a centerline. The land perimeters have flanges remote from the surface, each flange shaped by an outline. For adjacent lands, the flanges (207b, 218, 219) of the parallel perimeter portions have asymmetrical outlines relative to the centerline and are in concord so that alternately the flange of one land diminishes its outline where the flange of the adjacent land protrudes its outline. This coordinated variation shapes the space between the adjacent flanges in a meander-like mode. Adhesive plastic material is anchored in the space to hinder a land shift along the parallel perimeter portions.

Abstract: An integrated circuit product includes a die and an insulation layer. The insulation layer is operatively coupled to the die. The insulation layer includes a plurality of bump apertures. The insulation layer also includes an underfill anchor structure. Methods for making such an integrated circuit product are also described.

Abstract: A heat sink mechanism including multiple heat passages in the base of a casing of a chip package module penetrating through a substrate packed in the module; a metal material being deposited in each heat passage to become a heat sink conductor connecting the substrate and the surface of the casing to effectively solve the problem of excessive heat generated in the course of HF operation of the chip package module thus to prevent chip failure.

Abstract: A system-in-package (SiP) package is provided. In one embodiment, the SiP package comprises a substrate having a first surface and a second surface opposite the first surface, the substrate having a set of bond wire studs on bond pads formed on the second surface thereof; a first semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the first semiconductor chip is mounted to the second surface of the substrate by means of solder bumps; an underfill material disposed between the first semiconductor chip and the substrate, encapsulating the solder bumps; a second semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the second semiconductor chip is mounted to the second surface of the first semiconductor chip; and a set of bond wires electrically coupled from the second semiconductor chip to the set of bond wire studs on the substrate.

Abstract: A method of manufacturing a redistribution circuit structure is provided. First, a substrate is provided. The substrate has a plurality of pads and a passivation layer. The passivation layer has a plurality of first openings exposing a portion of each of the pads, respectively. A first patterned photoresist layer is formed on the passivation layer. The first patterned photoresist layer has a plurality of second openings exposing a portion of each of the pads. A plurality of first bumps is formed in the second openings, respectively. An under ball metal (UBM) material layer is formed over the substrate to cover the first patterned photoresist layer and the first bumps. A plurality of conductive lines is formed on the UBM material layer. The UBM material layer is patterned to form a plurality of UBM layers using the conductive lines as a mask.

Abstract: A bump structure with an annular support suitable for being disposed on a substrate is provided. The substrate has at least one pad and a passivation layer that has at least one opening exposing a portion of the pad. The bump structure with the annular support includes an under ball metal (UBM) layer, a bump, and an annular support. The UBM layer is disposed on the passivation layer and covers the pad exposed by the passivation layer. The bump is disposed on the UBM layer over the pad, and a diameter of a lower surface of the bump is less than the diameter of an upper surface thereof. The annular support surrounds and contacts the bump, and a material of the annular support is photoresist. An under cut effect is not apt to happen on the bump structure.

Abstract: Provided is a semiconductor device. The semiconductor device includes a first bump column on an active surface of the semiconductor device and including a plurality of first bumps spaced a first distance from an edge of the semiconductor device, a second bump column on the active surface and including a plurality of second bumps spaced a second distance that is greater than the first distance from the edge of the semiconductor device, and a third bump column on the active surface, and including a plurality of third bumps spaced a third distance that is greater than the second distance from the edge of the semiconductor device. The second bumps and the third bumps are sequentially alternated at least twice between the first bumps.

Abstract: A polygonal semiconductor device includes a substrate and a wiring layer. The substrate includes semiconductor circuit elements. The wiring layer includes a dielectric sealing layer, a plurality of first electrodes, and a plurality of second electrodes. The first and second electrodes both extend through the dielectric sealing layer in its thickness direction. The first electrodes are electrically connected to the semiconductor circuit elements. Each of the corners of the polygonal device is formed, throughout the thickness of the wiring layer, by one of the second electrodes. The corners of the device are thereby reinforced, as the electrode material is tougher than the dielectric sealing material.

Abstract: A semiconductor device having conductive bumps and a fabrication method thereof are provided. The fabrication method mainly including steps of: providing a semiconductor substrate having a solder pad and a passivation layer formed thereon with a portion of the solder pads exposed from the passivation layer; disposing a first metal layer on the solder pad and a portion of the passivation layer around the solder pad; disposing a covering layer on the first metal layer and the passivation layer, and forming an aperture in the covering layer to expose a portion of the first metal layer, wherein a center of the aperture is deviated from that of the solder pad; deposing a metal pillar on the portion of the first metal layer; and deposing a solder material on an outer surface of the metal pillar for providing a better buffering effect.

Abstract: A semiconductor package is disclosed that includes a semiconductor device; a circuit board; and a connection mechanism including a first conductive terminal provided on the semiconductor device, and a second conductive terminal provided on the circuit board side, the connection mechanism electrically connecting the semiconductor device and the circuit board via the first conductive terminal and the second conductive terminal. At least one of the first conductive terminal and the second conductive terminal of the connection mechanism includes one or more carbon nanotubes each having one end thereof fixed to the surface of the at least one of the first conductive terminal and the second conductive terminal, and extending in a direction away from the surface. The first conductive terminal and the second conductive terminal engage each other through the carbon nanotubes.

Abstract: A multi-layer substrate includes a plurality of substrate main bodies, a plurality of layers which are alternately layered with the main bodies, a signal via hole which is connected with a signal line and includes a signal column which passes through at least one substrate main body; and a sub via hole which includes a sub column which surrounds the signal column, and a pair of sub pads which extend from end parts of the sub column to be formed to the layers, the layers which are formed with the sub pads being disposed in the same layer as the layers which are formed with the signal line of the signal via hole, or being disposed outside the layers which are formed with the signal line which is connected with the signal via hole.

Abstract: The embodiments of the invention provide a metal capping process for a BEOL interconnect with air gaps. More specifically an apparatus is provided comprising metal lines within a first dielectric. Metal caps are over the metal lines, wherein the metal caps contact the metal lines. In addition, air gaps are between the metal lines, wherein the air gaps are between the metal caps. A second dielectric is also provided over the bottom portion of a first dielectric, wherein a top portion of the second dielectric is over the metal caps, and wherein top portions of the first dielectric and bottom portions of the second dielectric comprise sides of the air gap. The apparatus further includes dielectric caps over the metal lines, wherein the dielectric caps contact the metal caps.

Abstract: A press-fit diode, e.g., for rectifier applications, includes a diode chip, a base contact for pressing into a substrate, which base contact forms a first terminal of the press-fit diode, and a wire contact which forms a second terminal of the press-fit diode. An easily solderable corrosion-resistant press-fit diode is provided by coating the wire contact at least partially with a silver layer, the base contact having no silver layer.

Abstract: High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.

Abstract: A multilayer interconnect element is provided which includes at least one dielectric element in which metal interconnect patterns are exposed at an outer surface thereof, the metal interconnect patterns having outer surfaces which are co-planar with an exposed outer surface of the dielectric element. In addition, multilayer interconnect elements are provided in which second interconnect elements which do not have co-planar interconnect patterns are integrated therewith as intermediate elements, and the resulting multilayer interconnect element has co-planar interconnect patterns.

Abstract: According to the present invention, a bonding pad 10 of a semiconductor integrated circuit is arranged such that the opening pathways P through which metal wiring layers are connected have openings of at least two different widths including: a first width required to fill the opening pathway; and a second width being larger than the first width, and the openings are arranged lengthwise and crosswise.

Abstract: An AlCu film is formed by simultaneously depositing AlCu within a via hole and on top of an interlayer dielectric film. The surface of the AlCu film is polished using a CMP process, and a TiN antireflection layer is formed thereon. The TiN antireflection layer having a flat surface prevents halation during pattering the interconnections including the AlCu film, thereby preventing ingress of etching solution during a subsequent wet etching process.

Abstract: A semiconductor device, and a method for manufacturing the semiconductor device, has forming a layer having an in-plane polishing amount distribution, and setting the approximate uniform thickness of the layer over the whole semiconductor wafer by the process such that the in-plane polishing amount distribution is approximately uniform.

Abstract: A structure for improving the electrostatic discharge robustness of an integrated circuit having an electrostatic discharge (ESD) device and a receiver network connected to a pad by interconnects. The interconnect between the pad and the ESD device has a high-k material placed adjacent to at least one surface of the interconnect and extending over the thermal diffusion distance of the interconnect. The high-k material improves the critical current density of the interconnect by increasing the heat capacity and thermal conductivity of the interconnect. The high-k material can be placed on the sides, top and/or bottom of the interconnect. In multiple wire interconnects, the high-k material is placed between the wires of the interconnect. A low-k material is placed beyond the high-k material to reduce the capacitance of the interconnect. The combination of low-k and high-k materials provides an interconnect structure with improved ESD robustness and low capacitance that is well suited for an ESD device.

Abstract: The present invention relates to a circuit substrate comprising an upper surface, a first layout area, a second layout area, and a third layout area. The first layout area is on the upper surface, and has a plurality of first electrical contacts. The second layout area is on the upper surface, and has a plurality of second electrical contacts. The third layout area is on the upper surface, and has a plurality of third electrical contacts. The second and the third electrical contacts that have the same electrical property are electrically connected to each other. Thus, the circuit substrate can be applied to memory chips with different size.

Abstract: A method is presented for bare die attachment using conductive ink dots. Dielectric ink dots may be applied, for example as spacer bumps or for attaching. The conductive ink dots are not cured until die and substrate are placed on top of each other, and then cured to form a conductive connection between die and substrate.

Abstract: An improved portable misting fan device of the type formed by a body carrying fan means for creating and moving a stream of air, the body further provided with a reservoir and having a power source for driving the fan means and electrical means for driving the power source which further includes a powered mist generator having driving means and an actuator for actuating the mist generator, the mist generator being in fluid communication with the reservoir and a mist nozzle adapted to receive a fluid mist from the mist generator and deliver the same into the air stream created by the fan means.

Abstract: Disclosed is a gas-liquid contact system. The system includes a vessel arranged approximately perpendicular to the ground in a longitudinal direction, a static fluid mixer in the vessel having a passage tube and a spiral blade provided in the passage tube, a gas supplier supplying gas having foreign substances to the static fluid mixer from a lower end of the vessel, a gas discharger discharging the gas passed through the static fluid mixer from an upper end of the vessel, a first liquid supplier supplying liquid to the static fluid mixer, and a liquid discharger discharging the liquid supplied from the first liquid supplier outside of the vessel. In the system, the gas supplier includes a gas generator generating gas, a pipe connecting the gas generator with the vessel, a blowing device provided in the pipe, and a second liquid supplier supplying liquid to the pipe between the gas generator and the blowing device.

Abstract: In a process for the production of mouldings, e.g. contact lenses, a starting material which contains a photoinitiator with a spectral absorption (AC) in a given wavelength range is exposed to a predefined amount of light of a wavelength from this given wavelength range. Polymerisation and/or crosslinking of the starting material is thereby initiated, and in this way a demouldable moulding is formed The intensity of light is measured, to which end a broadband photoreceiver (511) is used, in front of which receiver a filter (510) is arranged, the transmission (TC1, TC2, TC3; TC4) of which is designed such that the light passing through the filter (510) and impinging on the photoreceiver (511) corresponds in its intensity to the light absorbed by the photoinitiator based on its spectral absorption (AC) at the wavelength from the given wavelength range.

Abstract: A new, faster and more efficient process to replace heating walls and ceilings in coke oven batteries. Thus, when replaced, at least one heating wall is constructed of thermally stable non-expanding large size modular cast modules from end to end and the ceiling adjacent the heating wall is constructed of thermally stable non-expanding large modular cast blocks.

Abstract: In a process for depositing large dry textile fiber webs on a component shape, a rolled up textile fiber web is deposited fully automatically, by means of robots. A robot-carrier cloth gripper grips the end of the textile fiber web to be deposited, and places it on the component shape. The web is then unwound from the roll by a robot-carried cloth unwinding stand, and is deposited on the component shape. During the depositing, the textile fiber web is draped by means of robot-carried heated sliding metal sheets or robot-carried movably disposed heated rollers. The depositing operation is continuously monitored and automatically readjusted to maintain a constant depositing rate. Alignment of the textile fiber web relative to the component shape is also monitored continuously by optical devices, and is readjusted as required.

Abstract: An apparatus for manufacturing a non-woven fabric is provided. The apparatus includes a spinning device and a coagulation device. The spinning device has at least one spinning nozzle, and the coagulation device has an ice sheet thereover and is disposed corresponding to the spinning device. Furthermore, a method for manufacturing the non-woven fabric is described as followed. First, a spinning solution containing a solvent and a fiber material dissolved therein is provided. Then, a spinning step is performed, in which the fibrous spinning solution extruded from the spinning device is coagulated by the coagulation device to form a plurality of mutually stacked fibers, thus forming a non-woven fabric. The non-woven fabric made by the apparatus and the method has desired uniformity.

Abstract: A method and water-jet laser processing device for forming a honeycomb structure molding die are disclosed. The water-jet laser processing device includes a bed on which a workpiece is set, a nozzle injecting a high-pressure water stream in a water column onto the workpiece at a recess forming position thereof, a laser head for guiding the laser beam through the water column to be irradiated onto the recess forming position of the workpiece, a window member disposed between the laser head and the nozzle and transmitting and focusing the laser beam through the water column, and moving means for moving the bed and the nozzle relative to each other to shift a laser beam irradiating position along the recess forming position.

Abstract: A polymeric medical device is constructed from bioabsorbable polymers. The device is constructed from a tube comprised of at least one polymer. The polymer is treated at pre-determined heating and cooling temperatures to obtain a desired morphology. The morphology or arrangement of the polymeric structure ensures that the device maintains its shape characteristics to ensure proper modeling of the vessel. In particular, the crystallinity of the polymeric structure is adjusted so as to resist recoil. The device can also contain a therapeutic agent dispersed throughout the structure or coated on the structure in such a manner as to elute the therapeutic agent when implanted in an anatomical conduit. The device can also be constructed from a blend of polymers and other agents such as plasticizers.

Abstract: In a processing method of a fine structure according to the present invention, an opposed platen (211)is moved from a retreat position to a molding/processing position, so that a film (1) is pressed against a mold (5) and processed. Thereafter a second block (211b) is separated from a first block (211a). Thus, improvement of the cooling rate for the opposed platen (211) can be attained by reducing the total thermal capacity of the opposed platen (211) by reducing the volume of the opposed platen (211) in cooling and physically discharging heat stored in the opposed platen (211). Thus, cooling efficiency for the opposed platen (211) is improved, and the heat cycle of the opposed platen (211) can be reduced.

Abstract: Mold (20) for manufacturing plastic products provided with a bottom and a sidewall, wherein the mold comprises at least a first (21) and second (22) mold part which jointly define at least partly at least one mold cavity (100) and are movable in a first direction, wherein the at least one mold cavity comprises at least one first, in particular bottom-forming part (101) and one second (102), in particular sidewall-forming part, wherein on the first mold part at least one fixed wall part (24) is provided which supports a first movable wall part (20) which is movable relative to the respective fixed wall part (24) in at least a second direction which includes an angle with the first direction, wherein in said first movable wall part a second movable wall part (35) is provided, on the side facing the mold cavity, which is movable between a forwardly moved position and a retracted position relative to the first movable wall part.

Abstract: A method for forming a surface-treated, three-dimensional object, comprising: solvent smoothing an exterior surface of a rapid-manufactured, three-dimensional object, and media blasting at least a portion of the solvent-smoothed exterior surface.

Abstract: Solid imaging apparatus and methods for use are disclosed that reduce the amount of uncured solid imaging build material remaining on a completed build object following the completion of the solid imaging build process. The amount of uncured build material is reduced through the use of either an uncoating web that removes excess build material from the build object during the course of the building process or an ink jet source of build material that uses only as much build material as is necessary for the fabrication of the build part. Also disclosed is an imager assembly for use with such a solid imaging apparatus that incorporates two or more individual imagers in an array and accounts for variations in the intensity and alignment of adjacent imagers. The apparatus can be modified for semi-continuous operation and for integrating into a manufacturing operation, if desired.

Abstract: There is provided an optical modeling apparatus that forms a model of a desired shape by sequentially forming hardened layers by irradiating a light-curable resin with light. The apparatus includes a first light source that emits a light beam for plotting on the resin, a scanning device that scans the light beam from the first light source over the resin, a second light source that emits light that irradiates one fixed region of the resin at a time, and a spatial light modulator that spatially modulates the light from the second light source to blanket-expose a specified region of the resin. The light beam from the scanning device and the light from the spatial light modulator form each hardened layer.

Abstract: Two methods of extending the lifetime of yttrium oxide as a plasma chamber material are provided. One method comprises making a three-layer component of a plasma processing chamber by co-sintering a dual-layer green body where one layer comprises ceramic particles and a second layer comprises yttria particles. The two layers are in intimate contact during the sintering process. In a preferred embodiment, the three layer component comprises an outer layer of yttria, an intermediate layer of YAG, and a second outer layer of alumina. Optionally, the disks are pressed together during the sintering process. The resulting three-layer component is very low in porosity. Preferably, the porosity of any of the outer layer of yttria, the intermediate layer of YAG, and the second outer layer of alumina, is less than 3%.