Abstract: A bolometric detector for electromagnetic radiation comprising a sensitive part or membrane comprising one or more layers of a sensitive material, the resistivity of which varies with temperature; first electric conductor elements in electrical continuity with a readout circuit associated with the bolometric detector and acting as electrodes for the detector and being in contact with the sensitive material and acting as an electromagnetic radiation absorber; second electric conductor elements at a floating potential acting only as an electromagnetic radiation absorber; at least one support area for the sensitive part fulfilling the function of positioning the sensitive part and electric conductor in relation to the readout circuit; at least one thermal isolation structure electrically and mechanically linking each support area to the sensitive part.

Abstract: The present invention provides a new scintillator, cerium bromide (CeBr3), for gamma ray spectroscopy. Crystals of this scintillator have been grown using the Bridgman process. In CeBr3, Ce3+ is an intrinsic constituent as well as a luminescence center for the scintillation process. The crystals have high light output (˜68,000 photons/MeV) and fast decay constant (˜17 ns). Furthermore, it shows excellent energy resolution for ?-ray detection. For example, energy resolution of <4% (FWHM) has been achieved using this scintillator for 662 keV photons (137Cs source) at room temperature. High timing resolution (<200 ps-FWHM) has been recorded with CeBr3-PMT and BaF2-PMT detectors operating in coincidence using 511 keV positron annihilation ?-ray pairs.

Abstract: A method and system for reconstructing an image in a time-of-flight (TOF) positron emission tomography (PET) system is provided. The method includes using a reconstructed image to determine predicted timing information. Timing bias data is updated based on received timing information associated with acquired scan data from a PET system and the predicted timing information. The method further includes reconstructing the image, based on the updated timing bias data.

Abstract: Radiation detection assemblies and related methods, including methods of making radiation detection assemblies and devices, as well as methods of performing radiation detection. A radiation detection assembly includes a radiation detector comprising a scintillator layer and an optically transparent substrate, the detector having a first side and a second side, a first imaging photodetector optically coupled to the first side of the detector, and a second imaging photodetector optically coupled to the second side of the detector, wherein at least one of the photodetectors is a position-sensitive imaging photodetector.

Abstract: A therapy system using an ion beam, which can shorten the time required for positioning a couch (patient). The therapy system using the ion beam comprises a rotating gantry provided with an ion beam delivery unit including an X-ray tube. An X-ray detecting device having a plurality of X-ray detectors can be moved in the direction of a rotation axis of the rotating gantry. A couch on which a patient is lying is moved until a tumor substantially reaches an extension of an ion beam path in the irradiating unit. The X-ray tube is positioned on the ion beam path and the X-ray detecting device is positioned on the extension of the ion beam path. With rotation of the rotating gantry, both the X-ray tube emitting an X-ray and the X-ray detecting device revolve around the patient. The X-ray is emitted to the patient and detected by the X-ray detectors after penetrating the patient. Tomographic information of the patient is formed based on signals outputted from the X-ray detectors.

Abstract: The invention relates to an X-ray detector with detector elements (1) arranged in a layer. The detector elements (1) contain a scintillator element (2) for the conversion of X-rays (X) into photons (v), a photodiode (5) for detection of the photons (v), and a processing circuit (4) for the processing of electric signals generated by the photodiode (5). In order to protect the electronics (4) from X-rays a shielding (3) of variable effective thickness (d1, d2) is disposed in front of the electronics (4). This shielding (3) can in particular be L-shaped. By reduction of the effective thickness of the shielding (3) to a necessary minimum the volume of the scintillator unit (2) can be maximized.

Abstract: A neutron elastic scattering detector device for non-invasively detecting the presence of at least one predetermined element of an object of interest. The detector device comprises a neutron source that simultaneously outputs, at a creation time, a neutron in a first direction and an associated baseline particle in a second direction. The first direction is opposite of the second direction. The neutron can impinge upon the predetermined element of the object of interest and scatter therefrom in a third direction. A baseline particle detector system detects the baseline particle and outputs a baseline signal characteristic thereof. A neutron detector system detects the neutron and outputs a scattering signal in characteristic thereof. The processing unit analyzes the baseline signal and the scattering signal to determine the presence of the predetermined element.

Abstract: An apparatus and method of use for injection, confinement, neutralization, acceleration and compression of an ion field using a solenoid having an axis of symmetry and supported within a vacuum space. A pair of magnetizable elements are positioned initially in spaced apart positions within the solenoid and after the solenoid is filled with ions from an ion source, the magnetizable elements are brought into close proximity to compress the ion field and accelerate its ions.

Abstract: In certain example embodiments of this invention, there is provided an ion source including an anode and a cathode. In certain example embodiments, a multi-piece outer cathode is provided. The multi-piece outer cathode allows precision adjustments to be made, thereby permitting adjustment of the magnetic gap between the inner and outer cathodes. This allows improved performance to be realized, and/or prolonged operating life of certain components. This may also permit multiple types of gap adjustment to be performed with different sized outer cathode end pieces. In certain example embodiments, cathode fabrication costs may also be reduced.

Abstract: A method for calibrating a radiation detection medium by exposing arbitrary locations of a radiation detection medium to a plurality of known radiation dose levels is described. One particular aspect of the method includes the steps of automatically determining the location of each arbitrary exposed location, measuring the density of each of the arbitrary exposed locations, matching each measurement for the arbitrary exposed locations with the corresponding radiation dose level thereby generating an array of paired data values for radiation dose level and measured density and calculating a calibration based on the array of paired data values.

Abstract: The invention is directed to an arrangement for providing target material for the generation of short-wavelength electromagnetic radiation, in particular EUV radiation. It is the object of the invention to find a novel possibility for providing target material for the generation of short-wavelength radiation based on an energy beam induced plasma which makes it possible to supply a reproducible successive flow of mass-limited targets in the interaction chamber in such a way that only the amount of target material needed for efficient generation of radiation achieves plasma generation. This object is met, according to the invention, in that the target generator opens into a selection chamber which precedes the interaction chamber and which has, along the target path, an outlet opening into the interaction chamber and in which a target selector is arranged.

Abstract: The present invention relates to a method for creating a pattern on a workpiece sensitive to electromagnetic radiation. Electromagnetic radiation is emitted onto a computer controlled reticle having a multitude of modulating elements (pixels). The pixels are arranged in said computer controlled reticle according to a digital description. An image of said computer controlled reticle is created on said workpiece, wherein said pixels in said computer controlled reticle are arranged in alternate states along at least a part of one feature edge in order to create a smaller address grid. The invention also relates to an apparatus for creating a pattern on a workpiece. The invention also relates to a semiconducting wafer and a mask.

Abstract: An ion source (1) to be used in optical thin film deposition by IAD process includes a discharge chamber (10), a gas source, an actuator (11), a grid assembly (20) and an outer shell (30). The grid assembly includes a screen grid (21), an accelerator grid (22) and a decelerator grid (23). The screen grid is kept at anode potential and is disposed near the ions. The accelerator grid is kept at cathode potential and is spaced from the screen grid. The decelerator grid is equal to the ground and is disposed beyond the accelerator grid. Each grid has a curved central portion (24) defining a plurality of apertures aligned with those of the other two grids to form extraction channels for an ion beam (40).

Abstract: An EUV plasma formation target delivery system and method is disclosed which may comprise: a target droplet formation mechanism comprising a magneto-restrictive or electro-restrictive material, a liquid plasma source material passageway terminating in an output orifice; a charging mechanism applying charge to a droplet forming jet stream or to individual droplets exiting the passageway along a selected path; a droplet deflector intermediate the output orifice and a plasma initiation site periodically deflecting droplets from the selected path, a liquid target material delivery mechanism comprising a liquid target material delivery passage having an input opening and an output orifice; an electromotive disturbing force generating mechanism generating a disturbing force within the liquid target material, a liquid target delivery droplet formation mechanism having an output orifice; and/or a wetting barrier around the periphery of the output orifice.

Abstract: A lithographic apparatus is disclosed. The apparatus includes a projection system configured to project a first radiation beam onto a target portion of a substrate, and at least one monitoring device for detecting contamination in a interior space. The monitoring device includes at least one dummy element having at least one contamination receiving surface. In an aspect of the invention, there is provided at least one dummy element which does not take part in transferring a radiation beam onto a target portion of a substrate, wherein it is monitored whether a contamination receiving surface of the dummy element has been contaminated.

Abstract: The invention relates to a memory device electrode, in particular for a resistively switching memory device, wherein the surface of the electrode is provided with a structure, in particular comprises one or a plurality of shoulders or projections, respectively. Furthermore, the invention relates to a memory cell comprising at least one such electrode, a memory device, as well as a method for manufacturing a memory device electrode.

Abstract: A method of forming and a device including an interconnect structure having a unidirectional electrical conductive material is described. The unidirectional conductive material may overlie interconnect materials, and/or may surround interconnect materials, such as by lining the walls and base of a trench and via. The unidirectional conductive material may be configured to conduct electricity in a direction corresponding to a projection to or from a contact point and conductive material overlying the unidirectional conductive material, but have no substantial electrical conductivity in other directions. Moreover, the unidirectional conductive material may be electrically conductive in a direction normal to a surface over which it is formed or in directions along or across a plane, but have no substantial electrical conductivity in other directions.

Abstract: Chalcogenide-based nanowire memories are implemented using a variety of methods and devices. According to an example embodiment of the present invention, a method of manufacturing a memory circuit is implemented. The method includes depositing nanoparticles at locations on a substrate. Chalcogenide-based nanowires are created at the locations on the substrate using a vapor-liquid-solid technique. Insulating material is deposited between the chalcogenide-based nanowires. Lines are created to connect at least some of the chalcogenide-based nanowires.

Abstract: The present invention provides an optical device integrating an active device with a passive device without any butt joint structure between two devices. The optical integrated device of the invention includes a GaAs substrate, first and second cladding layers, and an active layer sandwiched by the first and second cladding layers. These layers are disposed on the GaAs substrate. The GaAs substrate provides a first region and a second region. The active layer comprises of the first active layer disposed on the first region and the second active layer disposed on the second region of the GaAs substrate. The first active layer has a quantum well structure whose band-gap energy smaller than 1.3 eV, while the second active layer has a quantum well structure whose band-gap energy is greater than that of the first active layer.

Abstract: A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitaxial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon <1020 cm?3, the as-grown p- or n-type dopant profile can withstand furnace anneals to temperatures of 850° C. and rapid thermal anneal temperatures to 1000° C.

Abstract: The objective is to provide a random number generating device having a smaller circuit size and a smaller value of output bias. The random number generating device includes a pair of first and second current paths arranged in parallel with each other, and a pair of first and second fine particles, which can mutually exchange charges, and are located in the vicinity of the first and second current paths.

Abstract: An electronic device and a method of fabricating the electronic device includes forming a first electrical contact, a dielectric layer and a second electrical contact wherein the dielectric layer is located between the first and the second electrical contacts, forming an electrically insulating layer over the dielectric layer and the first electrical contact, exposing the first and second electrical contact, the dielectric layer and a first portion of the electrically insulating layer to radiation from the side of the first electrical contact, removing a second portion of the electrically insulating layer that was not irradiated by the radiation, providing a semiconductor material over a portion of the dielectric layer, and forming at least a third electrical contact over at least a portion of the electrically insulting layer and the semiconductor material.

Abstract: A thin film transistor includes a gate electrode on a substrate, a gate insulating layer on the substrate, a channel pattern, a source electrode and a drain electrode. The channel pattern includes a semiconductor pattern formed on the gate electrode and overlaying the gate electrode as well as first and second conductive adhesive patterns formed on the semiconductor pattern and spaced apart from each other. The source electrode includes a first barrier pattern, a source pattern and a first capping pattern sequentially formed on the first conductive adhesive pattern. The drain electrode includes a second barrier pattern, a drain pattern and a second capping pattern sequentially formed on the second conductive adhesive pattern. Etched portions of the first and second conductive adhesive patterns have a substantially vertical profile to prevent the exposure of the source and drain electrodes, thereby improving the characteristics of the thin film transistor.

Abstract: An active device array substrate is provided. The active device array substrate comprises a substrate, multiple first lines, second lines, active devices, pixel electrodes and common lines. The first lines and second lines are disposed on the substrate and they form multiple pixel regions on the substrate. The active devices are respectively disposed in the pixel regions and each of the active devices is electrically connected to a first line and a second line, respectively. The pixel electrodes are respectively disposed in the pixel regions and each of the pixel electrodes is electrically connected to an active device, respectively. The common lines and first lines are roughly parallel and they are staggeringly disposed on the substrate. Each of the common lines has multiple branches which extend outside from their edges of two sides, and each of these branches is partly overlapped with the second lines.

Abstract: A thin film transistor array panel according to an embodiment of the present invention includes: a gate line; a data line intersecting the gate line; a thin film transistor connected to the gate line and the data line; a pixel electrode connected to the thin film transistor; and a shielding electrode electrically isolated from the data line, covering the data line at least in part, and having an aperture exposing the data line.

Abstract: A transistor array panel comprises a substrate, a transparent electrode disposed on the substrate, a gate line disposed on the substrate, a gate insulating layer disposed on the transparent electrode and the gate line, a semiconductor layer disposed on the gate insulating layer, a data line and a drain electrode disposed on the semiconductor layer, a first insulating layer having an uneven surface, the first insulating layer disposed on the data line and the drain electrode, and a reflective electrode disposed on the first insulating layer, the reflective electrode connected to the transparent electrode and the drain electrode, wherein at least a portion of the transparent electrode is exposed.

Abstract: A method of fabricating a thin film transistor is disclosed. First, a substrate is provided and a patterned polysilicon layer is formed on the substrate. A metal layer is formed on the patterned polysilicon layer. Then, a portion of the metal layer is removed so that the remaining metal layer beside the patterned polysilicon layer forms a source and a drain. A gate insulation layer is formed on the substrate to cover the source, the drain and the patterned polysilicon layer. A gate is formed on the gate insulation layer over the patterned polysilicon layer.

Abstract: A semiconductor structure is disclosed that includes a silicon carbide wafer having a diameter of at least 100 mm with a Group III nitride heterostructure on the wafer that exhibits high uniformity in a number of characteristics. These include: a standard deviation in sheet resistivity across the wafer less than three percent; a standard deviation in electron mobility across the wafer of less than 1 percent; a standard deviation in carrier density across the wafer of no more than about 3.3 percent; and a standard deviation in conductivity across the wafer of about 2.5 percent.

Abstract: An LED includes a light-generating semiconductor region having an active layer sandwiched between two confining layers of opposite conductivity types for generating light. A cathode is arranged centrally on one of the opposite major surfaces of the semiconductor region from which is emitted the light. A reflector of electroconductive material is formed on the other major surface of the semiconductor region for reflecting the light back toward the light-emitting surface of the semiconductor region. For protecting the LED against breakdown from overvoltages, a zener diode is employed which takes the form of a baseplate having two semiconductor regions of opposite conductivity types sandwiched between a pair of electrodes in the form of metal layers. The protector baseplate is integrated with the light-generating semiconductor region by joining one of the metal layers to the reflector under heat and pressure, thus serving as both mechanical support and overvoltage protector for the LED.

Abstract: The present invention provides a highly controllable device for exposure from the back side and an exposure method, and also provides a method of manufacturing a semiconductor device using the same. The present invention involves exposure with the use of the back side exposure device of which a reflecting means is disposed on the front side of a substrate, apart from a photosensitive thin film surface by a distance X (X=0.1 ?m to 1000 ?m), and formation of a photosensitive thin film pattern in a self alignment manner, with good controllability, at a position a distance Y away from the end of a pattern. The invention fabricates a TFT using that method.

Abstract: A light-emitting diode (“LED”) device has an LED chip attached to a substrate. The terminals of the LED chip are electrically coupled to leads of the LED device. Elastomeric encapsulant within a receptacle of the LED device surrounds the LED chip. A second encapsulant is disposed within an aperture of the receptacle on the elastomeric encapsulant.

Abstract: A nanofluidic channel fabricated in fused silica with an approximately 500 nm square cross section was used to isolate, detect and identify individual quantum dot conjugates. The channel enables the rapid detection of every fluorescent entity in solution. A laser of selected wavelength was used to excite multiple species of quantum dots and organic molecules, and the emission spectra were resolved without significant signal rejection. Quantum dots were then conjugated with organic molecules and detected to demonstrate efficient multicolor detection. PCH was used to analyze coincident detection and to characterize the degree of binding. The use of a small fluidic channel to detect quantum dots as fluorescent labels was shown to be an efficient technique for multiplexed single molecule studies. Detection of single molecule binding events has a variety of applications including high throughput immunoassays.

Abstract: A semiconductor device includes a thyristor, trigger circuit and surge detection/leakage reduction circuit. The anode of the thyristor is connected to a first terminal and the cathode thereof is connected to a second terminal. The trigger circuit is configured to fire the thyristor when surge voltage is applied to the first terminal. The surge detection/leakage reduction circuit is provided between the gate of the thyristor and the second terminal and configured to interrupt current flowing from the trigger circuit to the second terminal in the normal operation mode and set trigger voltage which is used to fire the thyristor in cooperation with the trigger circuit at the surge voltage application time.

Abstract: A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device located on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel. The present invention also provides methods of fabricating the same. In general terms, the inventive method includes providing a hybrid oriented substrate having at least two planar surfaces of different crystallographic orientation, and forming at least one CMOS device on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel.

Abstract: A CMOS image sensor includes a first conductive type semiconductor substrate defined by a photodiode area and a transistor area, a trench formed in the semiconductor substrate corresponding to a transfer transistor of the transistor area, a gate electrode of the transfer transistor, formed in the trench, a second conductive type impurity ion area formed in the semiconductor substrate of the photodiode area, and a first conductive type impurity ion area formed on a surface of the second conductive type impurity ion area.

Abstract: The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second semiconductor layer is formed over the first semiconductor layer. Subsequently, a third semiconductor layer is formed over the second semiconductor layer, and semiconductor-containing seeds are formed over the third semiconductor layer. The seeds are annealed to form the rugged semiconductor-containing surface. The first, second and third semiconductor layers are part of a common stack, and can be together utilized within a storage node of a capacitor construction. The invention also includes semiconductor structures comprising rugged surfaces. The rugged surfaces can be, for example, rugged silicon.

Abstract: A memory cell structure comprises a first memory capacitor that is arranged in a first local area, and includes a first lower electrode, a first upper electrode, and a first dielectric oxide film interposed between the first lower electrode and the first upper electrode; a second memory capacitor that is spaced apart from the first memory capacitor and arranged in the first local area, and includes a second lower electrode, a second upper electrode, and a second dielectric oxide film interposed between the second lower electrode and the second upper electrode; and a first local interconnection layer.

Abstract: A nonvolatile semiconductor memory on a semiconductor chip includes: a cell array region configured with a memory cell transistor having a first metallic salicide film, a first control gate electrode electrically coupled with the first metallic salicide film, and a floating gate electrode adjacent to the first control gate electrode; a high voltage circuit region including a high voltage transistor made of a second metallic salicide film, a first source region and a first drain region, and a first gate region arranged between the first source region and the first drain region; and a low voltage circuit region including a low voltage transistor made of a third metallic salicide film, a second source region and a second drain region electrically coupled with the third metallic salicide film, and a second gate region arranged between the second source region and the second drain region and is electrically coupled with the third metallic salicide film.

Abstract: A non-volatile semiconductor memory (30) comprising a semiconductor substrate (1) and a plurality of memory cells (19) and methods for manufacturing such a memory is provided. Each memory cell (19) comprises a charge-trapping element (5), a gate stack (20), nitride spacers (10) and electrically insulating elements (21). The charge-trapping element (5) is arranged on the semiconductor substrate (1) and comprises a nitride layer (3) sandwiched between a bottom oxide layer (2) and a top oxide layer (4), the charge-trapping element (5) having two lateral sidewalls (24) opposed to one another. The gate stack (20) is arranged on top of the charge-trapping element (5), the gate stack having two lateral sidewalls (25) opposing one another. The electrically insulating elements (21) are disposed at opposing sidewalls (24) of the charge-trapping element (5) and cover the sidewalls (24) of the charge-trapping element (5).

Abstract: A manufacturing method and a device of an EEPROM cell are provided. The method includes the following steps. First, a tunnel layer and an inter-gate dielectric layer are formed over a surface of a substrate respectively, and a doped region is formed in the substrate under the inter-gate dielectric layer and used as a control gate. Thereafter, a floating gate is formed over the inter-gate dielectric layer and the tunnel layer. Thereafter, a source region and a drain region are formed in the substrate beside two sides of the floating gate under the tunnel layer. Especially, the manufacturing method of the memory cell can be integrated with the manufacturing process of high operation voltage component and low operation voltage component.

Abstract: Method and apparatus for providing a lateral double-diffused MOSFET (LDMOS) transistor having a dual gate. The dual gate includes a first gate and a second gate. The first gate includes a first oxide layer formed over a substrate, and the second gate includes a second oxide layer formed over the substrate. The first gate is located a pre-determined distance from the second gate. A digitally implemented voltage regulator is also provided that includes a switching circuit having a dual gate LDMOS transistor.

Abstract: A semiconductor structure embodiment comprises a semiconductor membrane with local strained areas. The membrane with local strained areas is formed by a process including performing a local oxidation of silicon (LOCOS) process in a substrate and removing resulting oxide to form a recess in the substrate, and bonding a semiconductor membrane to the substrate to induce a strain where the membrane conforms to the recess in the substrate.

Abstract: A semiconductor integrated circuit structure includes a plurality of diodes disposed in the substrate. These diodes are electrically coupled in series. At least one insertion region is disposed in the substrate between two of the diodes and a supply voltage node electrically coupled to the insertion region. Preferably, a guard ring surrounds the diodes.

Abstract: Systems and methods are disclosed herein to provide improved electrostatic protection for electrical circuits. For example, in accordance with an embodiment of the present invention, an electrostatic protection device includes: a drain region formed in a substrate; a gate separated from the substrate by a gate oxide; and an isolation region formed in the substrate, the isolation region being adapted to isolate the gate oxide from a DC voltage coupled to the drain region.

Abstract: Semiconductor devices and memory cells are formed using silicon rich barrier layers to prevent diffusion of dopants from differently doped polysilicon films to overlying conductive layers or to substrates. A polycilicide gate electrode structure may be formed using the silicon rich barrier layers. Methods of forming the semiconductor devices and memory cells are also provided.

Abstract: A first insulating substrate is formed on a heat sink, and a semiconductor element is formed thereon. An insulating resin casing is formed so as to cover the first insulating substrate and the semiconductor element. A second insulating substrate is mounted inside the insulating resin casing apart from the first insulating substrate. On the second insulating substrate, a resistance element that functions as a gate balance resistance is fixed by soldering. The second insulating substrate on which the resistance element was thus mounted was made apart from the first insulating substrate on which the semiconductor element was mounted, and was mounted on the side of the insulating resin casing.

Abstract: A semiconductor device includes a semiconductor substrate, and a MOS transistor provided on the semiconductor substrate and having a channel type of a first conductivity, the MOS transistor comprising a semiconductor region of the first conductivity type including first and second channel regions, gate insulating films provided on the first and second channel regions, a gate electrode provided on the gate insulating films, and first and second source/drain regions which are located at a distance from each other so as to sandwich the first and second channel regions, the first and second source/drain regions contacting the semiconductor region of the first conductivity type and forming a Schottky junction.

Abstract: Semiconductor devices that include a semiconductor substrate and a gate line are provided. The gate line is on the semiconductor substrate and includes a gate insulation pattern and a gate electrode which are stacked on the substrate in the order named. A spacer is on a sidewall of the gate line. A conductive line pattern is on the gate line. The conductive line pattern is parallel with the gate line and is electrically connected to the gate electrode.

Abstract: The present invention is to obtain an MIS transistor which allows considerable reduction in threshold fluctuation for each transistor and has a low threshold voltage. First gate electrode material for nMIS and second gate electrode material for pMIS can be mutually converted to each other, so that a process can be simplified. Such a fact that a dependency of a work function on a doping amount is small is first disclosed, so that fluctuation in threshold voltage for each transistor hardly occurs.

Abstract: A semiconductor device includes a field shield region that is doped opposite to the conductivity of the substrate and is bounded laterally by dielectric sidewall spacers and from below by a PN junction. For example, in a trench-gated MOSFET the field shield region may be located beneath the trench and may be electrically connected to the source region. When the MOSFET is reverse-biased, depletion regions extend from the dielectric sidewall spacers into the “drift” region, shielding the gate oxide from high electric fields and increasing the avalanche breakdown voltage of the device. This permits the drift region to be more heavily doped and reduces the on-resistance of the device. It also allows the use of a thin, 20 ? gate oxide for a power MOSFET that is to be switched with a 1V signal applied to its gate while being able to block over 30V applied across its drain and source electrodes, for example.