Patents Issued in July 29, 2008
  • Patent number: 7405554
    Abstract: Systems and/or methods for detecting a rotating wheel's speed and/or acceleration are provided. A sensor is attached to the rotating wheel. The sensor includes a circuit (e.g. a Wheatstone bridge circuit) having a plurality of resistors (e.g. 4 resistors). Each resistor includes a giant magnetoresistance (GMR) element and has a resistance changeable based at least in part on a change in magnetic field intensity with respect to an external magnetic field. The sensor generates a signal based at least in part on the resistors' resistances. A processor is operable to calculate the rotating wheel's speed and/or acceleration based at least in part on the signal.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: July 29, 2008
    Assignee: SAE Magnetics (H.K.) Ltd.
    Inventor: MingGao Yao
  • Patent number: 7405555
    Abstract: A local magnetic susceptibility unit is adapted to measure the AC magnetic susceptibility of a surface region of a sample. The unit comprises a sensing element and one or more balancing elements arranged in a circuit. When a sample is placed proximate to the sensing element the sample induces an imbalance voltage in the circuit.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: July 29, 2008
    Assignee: Philip Morris USA Inc.
    Inventors: Kudumboor V. Rao, Valter Ström, Ziyan Gu, Seetharama C. Deevi
  • Patent number: 7405556
    Abstract: A magnetic encoder system according to one embodiment includes a magnetic sensor mounted on a first substrate above a magnetic medium, the magnetic medium carrying at least one magnetic track, the sensor detecting changes in the magnetic track during a relative movement between the sensor and the magnetic medium. The first substrate is provided with a second substrate rotatably engaging the magnetic medium.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: July 29, 2008
    Assignee: International Business Machines Corporation
    Inventors: Marcus Breuer, Hubert Grimm, Hans-Guenter Kraemer, Nikolaus Luckner
  • Patent number: 7405557
    Abstract: A ball and socket joint with integrated angle sensor, especially for use as a vehicle level control in the chassis of a motor vehicle. The ball and socket joint has a ball and socket joint housing (1), a ball pivot (2) mounted in the ball and socket joint housing (1), a bipolar field transducer (4) arranged at the joint ball (3) of the ball pivot (2), and at least one magnetic field direction sensor (5), which is arranged at the ball and socket joint housing (1) and interacts with the magnetic field generated by the field transducer (4), wherein only one pole of the bipolar field transducer (4) is arranged on the surface of the ball.
    Type: Grant
    Filed: August 19, 2004
    Date of Patent: July 29, 2008
    Assignees: ZF Friedrichshafen AG, Sensitec GmbH
    Inventors: Joachim Spratte, Uwe Loreit
  • Patent number: 7405558
    Abstract: A method to determine deposits in a steam generator having the steps of creating a calibration standard having at least two rings of deposit material, subjecting the calibration standard to an eddy current signal, wherein an amplitude of the signal reflected from the calibration standard is used to obtain a polynomial equation fit of the reflected eddy current signals to actual thickness of the rings, obtaining a steam generator with tubes, initiating an eddy current signal into the tubes of the steam generator, detecting and recording reflections of the eddy current signal initiated into the tubes of the steam generator, and determining a thickness of the deposits in the steam generator from the recorded reflections of the eddy current signal and the polynomial equation.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: July 29, 2008
    Assignee: Areva NP, Inc.
    Inventors: Joseph R. Wyatt, John Griffith, Victor Newman, Jeffrey M. Fleck
  • Patent number: 7405559
    Abstract: The present invention is an electrical circuit for a sensor designed to detect external magnetic fields. The circuit is composed of a stable voltage reference source, connected to a low frequency amplifier where the operating point of the amplifier depends on the voltage reference source that is biased for maximum allowable voltage swings of the amplifier. A GMI fiber is connected to the low frequency amplifier and to a crystal oscillator that generates a square wave excitation signal with which to excite the GMI fiber. A decoupling network connected to the amplifier allows stable excitation of the GMI fiber by separating the direct current paths of the amplifier from the excitation signal. When the GMI fiber is excited by the square wave signal the GMI fiber impedance varies with impressed magnetic fields, which in turn varies the output voltage of the amplifier.
    Type: Grant
    Filed: June 26, 2006
    Date of Patent: July 29, 2008
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: James D. Hagerty
  • Patent number: 7405560
    Abstract: A GMR angle sensor for vehicles includes a GMR element in which the element resistance is changed in response to an external magnetic field, lead conductors connected to either end of the GMR element, and a protective layer that seals the GMR element and the lead conductors, wherein the protective layer has a laminated structure including an oxidation-resistant inorganic film that ensures that the GMR element and the lead conductors are sufficiently insulated and a silicone-based organic film laminated on the inorganic film.
    Type: Grant
    Filed: January 9, 2007
    Date of Patent: July 29, 2008
    Assignee: Alps Electric Co., Ltd
    Inventors: Yoshikazu Shimizu, Ichiro Tokunaga, Kenji Honda
  • Patent number: 7405561
    Abstract: A sensing apparatus includes a fluxgate module which outputs an analog signal corresponding to terrestrial magnetism using a fluxgate having a magnetic substance core and a driving coil, and an analog-to-digital (A/D) converter which converts an analog signal output from the fluxgate module into a digital signal. The fluxgate module includes first and second current amplifiers for exciting the magnetic substance core by applying pulses to first and second ends of the driving coil, and a pulse restricting part for driving the first and second current amplifiers to apply the pulses and for stopping driving the first and second current amplifiers when converting the analog signal into the digital signal is completed.
    Type: Grant
    Filed: September 14, 2006
    Date of Patent: July 29, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-jong Lee, Sang-on Choi, Seung-choul Song
  • Patent number: 7405562
    Abstract: A detection apparatus for detecting the presence of a sample, the detection apparatus comprising a chamber, ports for introducing a sample within the chamber, an actuation unit for establishing a controllable electromagnetic field in the chamber; and a sensing unit for sensing changes in the electromagnetic field due to the presence of the sample within the chamber. The sensing unit comprises a sensor device comprising a source and a drain embedded in a FET a gate for the FET, in which the gate is formed of a material whose conductivity is related to the electromagnetic field established in a nonconductive medium in contact with the gate.
    Type: Grant
    Filed: July 23, 2004
    Date of Patent: July 29, 2008
    Inventors: Yehya Ghallab, Wael Badawy
  • Patent number: 7405563
    Abstract: The present disclosure provides a downhole tool that includes a magnetometer and a nuclear magnetic resonance (NMR) sensor. One or more compensating magnets are provided on the tool to cancel or offset the effect of the magnetic field of the magnets of the NMR sensor on the magnetometer measurements made during drilling of a wellbore. The compensating magnets may have the same magnetic field characteristics as the sensor magnets and may be made of the same material.
    Type: Grant
    Filed: February 19, 2007
    Date of Patent: July 29, 2008
    Assignee: Baker Hughes Incorporated
    Inventors: Thomas Kruspe, Volker Krueger, Martin Blanz, Roland E. Chemali
  • Patent number: 7405564
    Abstract: A magnetic resonance method is described for forming a dynamic image from a plurality of signals of an object moving relative to at least one RF? receiving antenna. Imaging is acquired by at least two adjacent fields of view (FOV), which are reconstructed to an image over a region of interest which includes both FOVs. Prior to imaging a sensitivity map of the at least one RF receiving antenna at each position relative to the object is determined for each FOV. Thereafter data from the object to be imaged is sampled for each FOV with a reduced number of phase encoding steps with respect to the full set thereof at a fixed position relative to the main magnetic field. The image is then reconstructed from the subsampled signals, which are weighted with the sensitivity factor of the RF receiving antenna at the respective imaging position.
    Type: Grant
    Filed: December 10, 2003
    Date of Patent: July 29, 2008
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Paul Royston Harvey
  • Patent number: 7405565
    Abstract: The present invention provides an MRI apparatus with selective saturation without affection to the integral value of gradient magnetic field in 1TR. The MRI apparatus comprises a signal acquisition device for applying static field, gradient magnetic field pulses and RF pulses to an object to acquire magnetic resonance signals therefrom, an image reconstruction device for reconstructing an image based on the magnetic resonance signals acquired, and a controller device for controlling both device. The controller device directs the signal acquisition device to apply gradient magnetic field pulses and RF pulses for selective saturation for a number of times prior to applying gradient magnetic field pulses and RF pulses for signal acquisition.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: July 29, 2008
    Assignee: GE Medical Systems Global Technology Company, LLC
    Inventor: Mitsuharu Miyoshi
  • Patent number: 7405566
    Abstract: The effects of prior pulses are to be enhanced. A pulse string which monotonically decreases the flip angle is inserted between the prior pulse in one round and the imaging pulse in the previous round, and a pulse string which monotonically increases the flip angle is inserted between the prior pulse and the imaging pulse in one round. A return from the steady state to the equilibrium state can be achieved not only for on-resonance magnetization but also for off-resonance magnetization before the prior pulse is applied. Therefore, the effects of the prior pulse P can be fully attained. Further, not only on-resonance magnetization but also off-resonance magnetization can be brought close to the steady state before the imaging pulse is applied.
    Type: Grant
    Filed: September 7, 2006
    Date of Patent: July 29, 2008
    Assignee: GE Medical Systems Technology Company, LLC
    Inventor: Kenji Asano
  • Patent number: 7405567
    Abstract: A method and apparatus for tuning and matching extremely small sample coils with very low inductance for use in magnetic resonance experiments conducted at low frequencies. A circuit is disclosed that is appropriate for performing measurements in fields where magnetic resonance is beneficially utilized. The circuit has a microcoil, an adjustable tuning capacitance, and added inductance in the form of a tuning inductor. The microcoil is an electrical coil having an inductance of about 25 nanohenries (nH) or less. Because additional inductance is purposefully added, the capacitance required for resonance and apparatus function is proportionally and helpfully reduced. The apparatus and method permit the resonant circuit and the magnet to be made extremely small, which is crucial for new applications in portable magnetic resonance imaging, for example.
    Type: Grant
    Filed: August 21, 2006
    Date of Patent: July 29, 2008
    Assignee: ABQMR, Inc.
    Inventor: Andrew F. McDowell
  • Patent number: 7405568
    Abstract: A method and apparatus for digital quadrature lock-in detection capable of receiving magnetic resonance signals or electron spin resonance signals at high sensitivity. The method starts with digitizing a signal wave consisting of a magnetic resonance or electron spin resonance signal. The digitized signal wave is multiplied by digitized reference waves of sine and cosine functions to obtain signals of real and imaginary parts which are 90° out of phase (multiplying step). The frequencies of the sine and cosine functions are varied according to the observation width. The multiplying step is repeated.
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: July 29, 2008
    Assignee: Jeol Ltd.
    Inventor: Nobuaki Nemoto
  • Patent number: 7405569
    Abstract: A method and an apparatus are disclosed for measuring contact erosion in an electrical switching device by a dynamic resistance measurement (DRM). To determine an overlap time and a contact erosion in an exemplary switching device, a change in current across the switching device can be measured indirectly by a measurement current being passed across the switching device and a parallel conductor, the change in current in the parallel conductor being measured. Exemplary embodiments relate, to the following: detection of a differential current measurement signal in the parallel conductor with the aid of a Rogowski coil; and selection of a parallel conductor resistance on an order of the switch resistance.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: July 29, 2008
    Assignee: ABB Technology AG
    Inventors: Marek Hagel, Patrick Fehlmann
  • Patent number: 7405570
    Abstract: A connector assembly includes a battery pole terminal, a measurement element for a battery sensor, and a ground wire in the battery. The measurement element has two connections for connecting to the battery pole terminal and/or the battery cable, such that an electrically-conductive connection exists between the ground wire and the battery pole terminal by means of the measurement element. At least one of the connections is connected to the battery cable or the battery pole terminal by way of a force-locking or interference connection.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: July 29, 2008
    Assignee: Siemens Aktiengesellschaft
    Inventor: Armin Hirthammer
  • Patent number: 7405571
    Abstract: Methods and apparatuses for determining a battery capacity are described. According to one embodiment, an exemplary method includes generating virtual calibration data of the battery based on one or more characteristics of the battery, determining a virtual open circuit voltage (Voc) of the battery while the battery is being used, and estimating the capacity of the battery based on the determined virtual open circuit voltage of the battery and the virtual calibration data of the battery, while the battery is being used.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: July 29, 2008
    Assignee: HDM Systems Corporation
    Inventor: David S. C. Liu
  • Patent number: 7405572
    Abstract: A non metallic flow through electrodeless conductivity sensor is provided with a conduit having primary and secondary process fluid flowpaths to form a fluid loop. At least one drive and one sense toroid surround the conduit on the fluid loop. Voltage supplied to the drive toroid induces a current in the sense toroid via the fluid loop to eliminate any need for metallic electrodes in contact with the process fluid. At least one additional drive and/or sense toroid is disposed on the fluid loop to enhance induction. Optionally one or more sense coils are disposed about the conduit outside of the fluid loop to cancel out stray electrical noise. An optional conductor disposed along the conduit detects any fluid leakage through changes in resistance thereof.
    Type: Grant
    Filed: February 9, 2006
    Date of Patent: July 29, 2008
    Assignee: Invensys Systems, Inc.
    Inventors: John Kevin Quackenbush, Michael M. Bower, Stephen B. Talutis, Donald S. McKinlay
  • Patent number: 7405573
    Abstract: An interconnect assembly is for use in connection with a semiconductor device under test (DUT) having a plurality of leads to electronic test equipment. The interconnect assembly includes a cable including a plurality of wires with at least one wire for sensing a signal from a DUT, at least one wire for a forcing signal to the DUTY and at least one wire for a guarding signal driven by the same electrical potential as the forcing signal. A male connector includes the plurality of wires, an outer metal coating surrounding the plurality of wires, and an insulating coating around the outer metal coating. A receptacle connector is for receiving the male connector and plurality of wires with corresponding contacts.
    Type: Grant
    Filed: March 16, 2005
    Date of Patent: July 29, 2008
    Assignee: QualiTau, Inc.
    Inventor: Peter P. Cuevas
  • Patent number: 7405574
    Abstract: A signal suppression filter (22) that inhibits high-frequency signals contained in power voltage and a signal separation filter (23) that prevents transmission of the high-frequency signals are provided in series on power lines (21A), (21B) connected to a power input terminal (T1), and a common-mode signal detection circuit (25) and a normal-mode signal detection circuit (26) are provided separately from each other. While bi-directionally blocking transmission of a high-frequency signal (noise) between the power supply and the device to be measured by the signal suppression filter (22) and the signal separation filter (23), the common mode signal and the normal mode signal generated in the device to be measured (3) and entering through a power output terminal (T2) are detecting separately. The analysis of the cause of occurrence of a high-frequency signal produced in the device to be measured (3) is facilitated, and proper noise countermeasure may be taken.
    Type: Grant
    Filed: January 26, 2005
    Date of Patent: July 29, 2008
    Assignee: TDK Corporation
    Inventors: Hitomi Wasaki, legal representative, Yoshihiro Saitoh, Masaru Wasaki
  • Patent number: 7405575
    Abstract: A method and apparatus adapted to calibrate a signal path of a signal analysis system such that digital samples of a signal under test acquired by the system are processed for representing the impedance of a device under test. The method and apparatus calibrates the signal path to characterize transfer parameters of the device under test within a spectral domain. A reference impedance (Zref) is retrieved that is associated with the signal analysis system. The transfer parameters of the device under test and the reference impedance (Zref) are processed to effect thereby a representation of the device under test impedance (Zeq) as a function of frequency.
    Type: Grant
    Filed: August 23, 2006
    Date of Patent: July 29, 2008
    Assignee: Tektronix, Inc.
    Inventors: Kan Tan, John J. Pickerd, Ping Qiu
  • Patent number: 7405576
    Abstract: Two ends of a transmission line whose electrical characteristics per unit length are known are connected to associated measurement ports of a network analyzer. A short standard is shunt-connected to at least three points in the longitudinal direction of the transmission line, and electrical characteristics are measured in a short-circuited state, thereby calculating error factors of a measurement system. Then an electronic device to be measured is shunt-connected to the transmission line, and electrical characteristics of the electronic device are measured. Then the error factors of the measurement system are removed from the measured values of the electronic device to be measured, thereby obtaining true values of the electrical characteristics of the electronic device to be measured. Accordingly, a highly accurate high-frequency electrical characteristic measuring method that is not affected by connection variations can be implemented.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: July 29, 2008
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Gaku Kamitani
  • Patent number: 7405577
    Abstract: An apparatus and a method for detecting the material of a surface of flat objects on a stack, in particular of objects individually separated from one another in the stack by interlayers, preferably of printing plates. The object is to reliably detect the material of the surface of the object that was taken from the stack before it is provided for further processing. The object is achieved by a sensor apparatus that carries out a measurement of the electrical resistance in the region of the object surface to be determined. For this purpose, contact is made between the surface and sensor electrodes, and a measuring current is conducted through the surface. On the basis of the current intensity determined, a distinction is made as to the material of which the object surface is formed.
    Type: Grant
    Filed: August 26, 2003
    Date of Patent: July 29, 2008
    Assignee: Heidelberger Druckmaschinen AG
    Inventors: Stephan Limper, Volker Haushahn
  • Patent number: 7405578
    Abstract: The invention relates to a device that can be used to monitor the contact integrity of a joint that is of an impervious contact surface between two parts (4 and 5) including a set of conductive patterns (8) which are distributed over the two contact surfaces (1 and 2) and which are separated by insulating zones (9). When the aforementioned two parts (4 and 5) are brought into contact, the conductive patterns (8) also come into contact and form a conductor between the two measuring points (6 and 7), which is made by positioning the resistances of the patterns (8) in series. Any local change in the contact between the patterns causes the intensity and voltage between points (6) and (7) to vary and is measured with a measuring device (22). The invention is particularly suitable for the detection of an intrusion or a leak between two sealed contact parts.
    Type: Grant
    Filed: January 6, 2004
    Date of Patent: July 29, 2008
    Inventor: Dautrey Mikael
  • Patent number: 7405579
    Abstract: The present invention is to provide a voltage detector having a common communication line for reducing a manufacturing cost. A low voltage line CPU transmits a detection instruction including an assignment of one address among a plurality of blocks. The detection instruction is branched by a transmitting bus line for concurrently transmitting to a plurality of voltage detector units. When one of the voltage detector units receives the detection instruction with the address being same as a self-address thereof, the voltage detector unit detects output voltages of unit cells and transmits the detected result to the low voltage line CPU. When the received address is not the self-address, the voltage detector unit does not transmit the detected result.
    Type: Grant
    Filed: December 11, 2006
    Date of Patent: July 29, 2008
    Assignee: Yazaki Corporation
    Inventors: Hajime Okamoto, Satoshi Ishikawa, Ryosuke Kawano
  • Patent number: 7405580
    Abstract: The surface photovoltage dopant concentration measurement of a semiconductor wafer is calibrated by biasing the semiconductor wafer into an avalanche breakdown condition in a surface depletion region; determining a contact potential difference value corresponding to an avalanche breakdown; determining small signal ac-surface photovoltage value corresponding to an avalanche breakdown; and using the values of the contact potential and the surface photovoltage to calculate a calibration constant that relates depletion layer capacitance and an inverse of the surface photovoltage.
    Type: Grant
    Filed: March 16, 2006
    Date of Patent: July 29, 2008
    Assignee: Semiconductor Diagnostics, Inc.
    Inventor: Dmitriy Marinskiy
  • Patent number: 7405581
    Abstract: A probing system for electrical testing of a semiconductor device uses a probe device including probe tips on a surface of a semiconductor die. The probe tips can be fabricated as metal bumps on contact pads having a pattern that is the same as the pattern of contact pads on the semiconductor device. The semiconductor die can provide the probe device with substantially the same thermal properties as the semiconductor device, so that the same probe can be used for testing over a broad temperature range. Further, the probe device can be fabricated using semiconductor device fabrication techniques, so that probe designs can scale down as device fabrication techniques move to smaller dimensions.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: July 29, 2008
    Assignee: Novellus Development Company, LLC
    Inventor: Mark L. DiOrio
  • Patent number: 7405582
    Abstract: A performance board able to secure low loss, low reflection, stable transmission characteristics even when using a high frequency signal to test an electronic device and able to suppress signal leakage to the outside and entry of noise, provided with a base board having a signal pattern electrically connected with a socket formed on its front surface, a coaxial connector to which a coaxial cable electrically connecting the performance board and test apparatus is connected, passing through the base board from the back surface toward the front surface, and having a front exposed part of the center contact bent and electrically connected to the signal pattern, and a cover member covering the front exposed part of the center contact and correcting the impedance of the front exposed part.
    Type: Grant
    Filed: June 1, 2006
    Date of Patent: July 29, 2008
    Assignee: Advantest Corporation
    Inventors: Hiroyuki Mineo, Atsunori Shibuya
  • Patent number: 7405583
    Abstract: Improved methods, systems, and apparatuses are disclosed for testing LGA devices. One example embodiment include vertical routing of test nest assembly cooling lines in order to minimize the test nest footprint and increase available test sites on a single test card. Another example embodiment includes isolating and adjusting external loads and moments into the heatsink/cold plate, wherein these loads and moments involve controlling the centroid to restore more ideal thermal performance of the heatsink/chip interface. Still another example embodiment includes a nest architecture facilitating easy and low-cost replacement of LGA sockets. Finally, another example embodiment includes efficient condensation control of test nest assembly parts by using dry-air exhaust.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: July 29, 2008
    Assignee: International Business Machines Corporation
    Inventors: John Saunders Corbin, Jr., Jose Arturo Garza, Dales Morrison Kent, Kenneth Carl Larsen, Howard Victor Mahaney, Jr., Hoa Thanh Phan, John Joseph Salazar
  • Patent number: 7405584
    Abstract: A prober that has improved positional precision of probing without reducing throughput is disclosed.
    Type: Grant
    Filed: May 3, 2007
    Date of Patent: July 29, 2008
    Assignee: Tokyo Seimitsu Co., Ltd.
    Inventors: Taichi Fujita, Takahiro Hokida, Tetsuo Hata, Satoshi Moriyama, Yoshiyuki Yokoyama
  • Patent number: 7405585
    Abstract: This invention discloses a semiconductor test structure array comprising a plurality of unit cells for containing devices under test (DUT) arranged in an addressable array, and an access-control circuitry within each unit cell for controlling accesses to one or more DUTs, wherein the access-control circuitry comprises at least four identical controlled transmission gates (CTGs), and a plurality of the access-control circuitries are isomorphic.
    Type: Grant
    Filed: September 15, 2006
    Date of Patent: July 29, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yih-Yuh Doong
  • Patent number: 7405586
    Abstract: An apparatus, a method and a system to test a device. An input/output (I/O) block communicates with an external tester to receive test data and to send test result using first and second communication modes. A logic block parses the test data. A memory stores microcode from the parsed test data. The microcode contains a test program to test a circuit. A controller executes the test program.
    Type: Grant
    Filed: March 20, 2006
    Date of Patent: July 29, 2008
    Assignee: Intel Corporation
    Inventors: Sunil Gupta, Reed Linde, Rich Fackenthal
  • Patent number: 7405587
    Abstract: Provided is an interface circuit having a terminator, in which the terminator includes parallel-connected first to an Nth resistance elements, where N is an integral number equal to or more than 2, and a first to an nth cut-off elements connected in serial with each of the corresponding n(1?n<N) first to the Nth resistance elements of the first to the Nth resistance elements.
    Type: Grant
    Filed: July 3, 2006
    Date of Patent: July 29, 2008
    Assignee: Seiko Epson Corporation
    Inventors: Fumikazu Komatsu, Yasunari Furuya
  • Patent number: 7405588
    Abstract: The present invention relates to an LSI in which functions can be changed, and realizes, particularly, a system LSI in which functions are changed by changing connections of the circuit by use of MEMS switches. A bistable MEMS switch which can maintain states, and exhibits optimal stitching property, i.e., the switch has a very small resistance of several ? or less in an on-state, and has an infinite resistance in an off-state; is employed. An element in which functions can be changed during operation, is produced by utilizing a wiring layer of a CMOS semiconductor to form the MEMS switch. A semiconductor device exhibiting high-degree of freedom for changing functions, high-speed, and having small area, is realized.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: July 29, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Takayuki Kawahara, Masayuki Miyazaki, Yasushi Goto, Natsuki Yokoyama, Takahiro Onai
  • Patent number: 7405589
    Abstract: A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: July 29, 2008
    Assignee: Altera Corporation
    Inventors: David Lewis, Christopher F. Lane, Sarathy Sribhashyam, Srinivas Perisetty, Tim Vanderhoek, Vaughn Betz, Thomas Yau-Tsun Wong, Andy L. Lee
  • Patent number: 7405590
    Abstract: Systems and methods for controlling the programming current directed through a fuse or set of fuses in a device such as an integrated circuit. One embodiment comprises a method for applying different currents to a set of calibration fuses, identifying which currents cut the corresponding fuses without destroying them, and selecting one of the identified currents to use in programming one or more target fuses. In one embodiment, fuses that are cut but not destroyed are identified by passing the same read current through each of the calibration fuses and comparing resulting voltages to reference voltages which correspond to impedances between the impedances of the possible fuse states (uncut, cut and destroyed.) Fuse voltages between the reference voltages identify fuses which are cut but not destroyed.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: July 29, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masaaki Kaneko
  • Patent number: 7405591
    Abstract: An apparatus interfaces a first circuit using a first supply voltage and a second circuit using a second supply voltage different from the first supply voltage. The apparatus includes a driver circuit having a driver network comprising driver supply voltage terminals connected to controllable switches. The controllable switches include resistive elements or are separated from resistive elements. A receiver circuit has a receiving network comprising a resistive element and receiver supply voltage terminals and a connection line connecting the driver circuit and the receiving circuit. The controllable switches have two switch configurations, a first switch configuration resulting in a high voltage on the connection line and a second switch configuration resulting in a low voltage on the connection line.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: July 29, 2008
    Assignee: Qimonda AG
    Inventors: Georg Braun, Dirk Scheideler, Steve Wood, Richard Johannes Luyken, Edoardo Prete, Hans-Peter Trost, Anthony Sanders
  • Patent number: 7405592
    Abstract: A method according to one embodiment may include switching, by an integrated circuit, a plurality of switches to generate at least one output signal having a first amplitude and a second amplitude. The method according to this embodiment may also include controlling, by the integrated circuit, a conduction state of the plurality of switches to include a first conduction state and a second conduction state. The method according to this embodiment may also include minimizing, by the integrated circuit, the number of switch transitions between the first conduction state and the second conduction state of at least one switch when the output signal goes from the first amplitude to the second amplitude.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: July 29, 2008
    Assignee: Intel Corporation
    Inventor: Farzad Ghobadian
  • Patent number: 7405593
    Abstract: Disclosed are on-chip global electrical signaling systems and methods employing differential current-mode sensing having reduced delay and energy dissipation compared to conventional inverter repeaters. The present inventions can be used for point-to-point connections as well as N-to-1 connections.
    Type: Grant
    Filed: November 1, 2005
    Date of Patent: July 29, 2008
    Assignee: Fujitsu Limited
    Inventors: Nestor Tzartzanis, William W. Walker
  • Patent number: 7405594
    Abstract: A current mode driver generates a differential output signal that has a constant voltage swing between a lower voltage level and an upper voltage level. A feedback module determines an intermediate voltage between the lower voltage level and the upper voltage level, compares the intermediate voltage with a reference voltage, and generates a control signal based on a result of the comparison. The current mode driver maintains the voltage swing of the differential output signal at a constant voltage based on the control signal. The differential output signal may have a data signal component and a pre-emphasis signal component.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: July 29, 2008
    Assignee: Integrated Device Technology, Inc.
    Inventor: Chao Xu
  • Patent number: 7405595
    Abstract: A high-side transistor driver including a driver circuit for generating a driving signal to drive a high-side transistor is provided. A floating supply terminal provides a supply voltage to the driver circuit. A floating ground terminal is connected to a source of the high-side transistor. A bootstrap diode is coupled between the floating supply terminal and a voltage source. A capacitor is connected to the bootstrap diode and is coupled between the floating supply terminal and the floating ground terminal. A high-voltage transistor is used for switching off the driving signal and the high-side transistor in response to an input signal. A speed-up capacitor is coupled to the driver circuit for speeding up the driving signal. Furthermore, the positive feedback circuits in the driver circuit further accelerate the driving signal and save power for the driver circuit.
    Type: Grant
    Filed: November 16, 2005
    Date of Patent: July 29, 2008
    Assignee: System General Corp.
    Inventors: Ta-yung Yang, Chuh-Ching Li, Yu-Min Chen
  • Patent number: 7405596
    Abstract: A driver circuit is improved in drive capability corresponding to a resolution increase for a CCD sensor while suppressing chip size of a driver circuit. A preceding-stage circuit, operating on VDD2 (>VDD) and VLOW2 (<VLOW), is provided in a stage preceding an output-stage circuit operating on VDD and VLOW. The output-stage has a transistor QPd that turns on when supplied with a gate voltage VLOW2 from the preceding-stage circuit, thus outputting, onto an output terminal Vout, a voltage VDD and a current according to a voltage Vgs (=VDD?VLOW2). In addition, a transistor QNd turns on when supplied with a gate voltage VDD2 from the preceding-stage circuit, thus outputting, onto an output terminal Vout, a voltage VLOW and a current according to a voltage Vgs (=VDD2?VLOW). Because these Vgs are greater than VDD?VLOW, the output-stage circuit can be improved in drive capability and transistor size be correspondingly suppressed.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: July 29, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Takashi Tanimoto
  • Patent number: 7405597
    Abstract: An advanced repeater with duty cycle adjustment. In accordance with a first embodiment of the present invention, an advanced repeater includes an output stage for driving an output signal line responsive to an input signal and a plurality of active devices for selectably adjusting a duty cycle of the signal. The advanced repeater may further include circuitry for producing a delayed version of the signal.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: July 29, 2008
    Assignee: TRANSMETA Corporation
    Inventor: Scott Pitkethly
  • Patent number: 7405598
    Abstract: A differential line compensation apparatus is disclosed that has a first terminal to receive a first differential signal supplied by a first trace and a second terminal to receive a second differential signal supplied by a second trace. The apparatus has at least one detector to detect a first condition of a first signal at least related to the first differential signal, and a second condition of a second signal at least related to the second differential signal and to provide an output containing the results of the detections. A comparator is coupled to the at least one detector to receive and process the at least one output and to provide a control output. At least one delay controller receives the control output and applies a phase correction to a selected one of the first signal and the second signal. A corresponding method and system are also disclosed.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: July 29, 2008
    Assignee: Infineon Technologies AG
    Inventors: Ban Hok Goh, Dieter Draxelmayr
  • Patent number: 7405599
    Abstract: A magnetic transistor circuit with the OR, NOR, NAND and AND functions has a first, a second, a third, a fourth magnetic transistor, and a routing line. These four magnetic transistors as ordinary transistors that can be turned on or turned off by the control of several metal devices respectively disposed around the magnetic transistors. The OR, NOR, NAND and AND logic functions of the binary system can be implemented by the control of these metal devices.
    Type: Grant
    Filed: October 16, 2006
    Date of Patent: July 29, 2008
    Assignee: Northern Lights Semiconductor Corp.
    Inventors: Tom Allen Agan, James Chyi Lai
  • Patent number: 7405600
    Abstract: A current mode logic (CML)-CMOS converter comprises an input stage that is turned on/off by receiving an input voltage from the outside; a voltage control unit that outputs a constant voltage; a first switching unit that is connected to the input stage and the voltage control unit and is turned on/off by the constant voltage applied from the voltage control unit; and a second switching unit that is connected to the input stage and is turned on/off by a signal applied from the input stage.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: July 29, 2008
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Yu Sin Kim, Jeong Ho Moon, Moo Il Jeong, Chang Seok Lee, Chang Soo Yang, Sang Gyu Park, Kwang Du Lee
  • Patent number: 7405601
    Abstract: In at least one embodiment of the invention, a method for dividing a first signal having a first frequency by a divide ratio to generate a lower frequency signal includes generating a first plurality of signals having a common frequency, a first pulse width, and different phases. The first plurality of signals is based, at least in part, on at least one signal having a second pulse width. The first pulse width is selected from a plurality of pulse widths based, at least in part, on the divide ratio. The method includes sequentially selecting individual pulses of the first plurality of signals as an output signal of a select circuit to generate an output signal having a frequency lower than the first frequency.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: July 29, 2008
    Assignee: Silicon Laboratories Inc.
    Inventors: Akhil K. Garlapati, Lizhong Sun, Douglas F. Pastorello, Richard J. Juhn, Axel Thomsen
  • Patent number: 7405602
    Abstract: To present a reset control circuit and a reset control method used in a system including clock synchronous circuit, capable of resetting appropriately, especially in case of abnormality, when the clock signal is stopped or its period is longer as compared with the reset response required for detection of abnormal state. A reset control circuit 200 for output control of reset signal RS depending on reset request signal RR comprises a clock transforming unit 210 for transforming and issuing a clock signal CK, while generating a clock output signal RC at delay of clock output waiting period DC depending on the reset request signal RR, and a reset signal generator 220 for generating a reset signal RS at delay of reset output waiting period D depending on the clock output signal RC.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: July 29, 2008
    Assignee: Fujitsu Limited
    Inventor: Teruhiko Saitou
  • Patent number: 7405603
    Abstract: A Delayed Locked Loop Circuit of DLL comprises a buffer that receives a power-down signal and an inverted signal of a first clock signal; first and second delay lines an output device that outputs signals corresponding to the output signals of the first and second delay lines respectively; a replica delay unit, a phase comparator for comparing a phase difference between the output signal of the second buffer and the output signal of the replica delay unit; and a delay line controller for controlling delay times of the first delay line and the second delay line by corresponding to a comparison result of the phase comparator. The DLL circuit is configured such that the first and second buffers are disabled when the power-down mode entry notifying signal corresponding to a power-down mode is provided.
    Type: Grant
    Filed: October 6, 2006
    Date of Patent: July 29, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventor: Young Jun Ku