Patents Issued in July 29, 2008
  • Patent number: 7405453
    Abstract: A high k dielectric film and methods for forming the same are disclosed. The high k material includes two peaks of impurity concentration, particularly nitrogen, such as at a lower interface and upper interface, making the layer particularly suitable for transistor gate dielectric applications. The methods of formation include low temperature processes, particularly CVD using a remote plasma generator and atomic layer deposition using selective incorporation of nitrogen in the cyclic process. Advantageously, nitrogen levels are tailored during the deposition process and temperatures are low enough to avoid interdiffusion and allow maintenance of the desired impurity profile.
    Type: Grant
    Filed: May 17, 2005
    Date of Patent: July 29, 2008
    Assignee: ASM America, Inc.
    Inventors: Eric J. Shero, Christophe Pomarede
  • Patent number: 7405454
    Abstract: An atomic layer deposited dielectric layer and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. Depositing a hafnium metal layer on a substrate surface by atomic layer deposition and depositing a hafnium oxide layer on the hafnium metal layer by atomic layer deposition form a hafnium oxide dielectric layer substantially free of silicon oxide. Dielectric layers containing atomic layer deposited hafnium oxide are thermodynamically stable such that the hafnium oxide will have minimal reactions with a silicon substrate or other structures during processing.
    Type: Grant
    Filed: August 26, 2005
    Date of Patent: July 29, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 7405455
    Abstract: One aspect of the invention encompasses a method of forming a semiconductor structure. A patterned line is formed to comprise a first layer and a second layer. The first layer comprises silicon and the second layer comprises a metal. The line has at least one sidewall edge comprising a first-layer-defined portion and a second-layer-defined portion. A third layer is formed along the at least one sidewall edge. The third layer comprises silicon and is along both the first-layered-defined portion of the sidewall edge and the second-layered-defined portion of the sidewall edge. The silicon of the third layer is reacted with the metal of the second layer to form a silicide along the second-layer-defined portion of the sidewall edge. The silicon of the third layer is removed to leave the silicon of the first layer, the metal of the second layer, and the silicide.
    Type: Grant
    Filed: May 10, 2005
    Date of Patent: July 29, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn, Luan C. Tran
  • Patent number: 7405456
    Abstract: The present invention relates to an optical sensor chip package in a cavity of forming frame thereof and has a gap between protection layer and optical sensor chip. The optical sensor chip avoids accepting the pressure from protection layer that damage the reliability between pads and metallic traces when protection layer lay on the forming frame. It improves drawbacks of the glue pass trough the gap between optical sensor chip and pads into the optical sensor area of optical sensor chip. It improves the high process yield and reduces the height of optical sensor chip package to achieve lightly and thinly.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: July 29, 2008
    Assignee: Sigurd Microelectronics Corp.
    Inventors: Po-Hung Chen, Chin-Cheng Lo, Mao-Jung Chen
  • Patent number: 7405457
    Abstract: A high temperature NTC thermistor includes a polycrystalline thermistor body, selected from a list consisting of polycrystalline Si with intrinsic conductivity and polycrystalline Ge with intrinsic conductivity. At least one ohmic contact is disposed on at least one surface of the polycrystalline thermistor body.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: July 29, 2008
    Assignee: AdSem, Inc.
    Inventor: Michael Kozhukh
  • Patent number: 7405458
    Abstract: A semiconductor structure and a method for forming the same. The structure includes (a) a semiconductor channel region, (b) a semiconductor source block in direct physical contact with the semiconductor channel region; (c) a source contact region in direct physical contact with the semiconductor source block, wherein the source contact region comprises a first electrically conducting material, and wherein the semiconductor source block physically isolates the source contact region from the semiconductor channel region, and (d) a drain contact region in direct physical contact with the semiconductor channel region, wherein the semiconductor channel region is disposed between the semiconductor source block and the drain contact region, and wherein the drain contact region comprises a second electrically conducting material; and (e) a gate stack in direct physical contact with the semiconductor channel region.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: July 29, 2008
    Assignee: International Business Machines Corporation
    Inventor: Edward J. Nowak
  • Patent number: 7405459
    Abstract: The present invention provides a zeolite sol which can be formed into a porous film that can be thinned to an intended thickness by a method used in the ordinary semiconductor process, that excels in dielectric properties, adhesion, film consistency and mechanical strength, and that can be easily thinned; a composition for film formation; a porous film and a method for forming the same; and a high-performing and highly reliable semiconductor device which contains this porous film inside. More specifically, the zeolite sol is prepared by hydrolyzing and decomposing a silane compound expressed by a general formula: Si(OR1)4 (wherein R1 represents a straight-chain or branched alkyl group having 1 to 4 carbons, and when there is more than one R1, the R1s can be independent and the same as or different from each other) in a conventional coating solution for forming a porous film in the presence of a structure-directing agent and a basic catalyst; and then by heating the silane compound at a temperature of 75° C.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: July 29, 2008
    Assignees: Shin-Etsu Chemical Co. Ltd., Matsushita Electric Industrial Co., Ltd.
    Inventors: Tsutomu Ogihara, Fujio Yagihashi, Hideo Nakagawa, Masaru Sasago
  • Patent number: 7405460
    Abstract: A semiconductor device has a configuration in which more than three kinds of wells are formed with small level differences. One kind of well from among the more than three kinds of wells has a surface level higher than other kinds of wells from among the more than three kinds of wells. The one kind of well is formed adjacent to and self-aligned to at least one kind of well from among the other kinds of wells. The other kinds of wells are different in one of a conductivity type, an impurity concentration and a junction depth, and include at least two kinds of wells having the same surface level.
    Type: Grant
    Filed: March 19, 2004
    Date of Patent: July 29, 2008
    Assignee: Ricoh Company, Ltd.
    Inventors: Masaaki Yoshida, Naohiro Ueda, Masato Kijima
  • Patent number: 7405461
    Abstract: A highly reliable semiconductor device that controls both defects and impurity diffusion and a method for manufacturing such a semiconductor device. An N+ embedment layer and an N-type epitaxial layer are formed on a main surface region of a P-type silicon substrate. An STI trench is formed in the N-type epitaxial layer. A thermal oxidation film is formed on the inner surface of the STI trench. The STI trench is filled with an HDP-NSG film. A deep trench is formed in the STI trench with a depth reaching the silicon substrate. A further thermal oxidation film is formed on the inner surface of the deep trench. The thermal oxidation film of the deep trench is thinner than that of the STI trench. A silicon oxidation film is also formed in the deep trench and filled with a polysilicon film.
    Type: Grant
    Filed: September 7, 2005
    Date of Patent: July 29, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Haruki Yoneda
  • Patent number: 7405462
    Abstract: Reconfigurable logic devices and methods of programming the devices are disclosed. The logic device includes a look-up table (LUT) and at least one storage element configured for sampling LUT output signals. The LUT comprises a plurality of input signals, an array of programmable impedance devices operably coupled to the input signals, and the LUT output signals. Each programmable impedance device in the array includes a first electrode operably coupled to one of the input signal, a second electrode disposed to form a junction wherein the second electrode at least partially overlaps the first electrode, and a programmable material disposed between the first electrode and the second electrode. The programmable material operably couples the first electrode and the second electrode such that each programmable impedance device exhibits a non-volatile programmable impedance. The array may be configured as a one-dimensional or two-dimensional array.
    Type: Grant
    Filed: January 31, 2006
    Date of Patent: July 29, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Gregory S. Snider, Philip J. Kuekes
  • Patent number: 7405463
    Abstract: According to embodiments of the present invention, circuits have elements to protect a high-voltage transistor in a gate dielectric antifuse circuit. An antifuse has a layer of gate dielectric between a first terminal coupled to receive an elevated voltage and a second terminal, and a high-voltage transistor is coupled to the antifuse and has a gate terminal. An intermediate voltage between the supply voltage and the elevated voltage is coupled to the gate terminal of the high-voltage transistor to protect the high-voltage transistor.
    Type: Grant
    Filed: June 26, 2006
    Date of Patent: July 29, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Kenneth W. Marr, John D. Porter
  • Patent number: 7405464
    Abstract: An array substrate includes a base substrate, a switching element, and a pixel electrode. The switching element is on the base substrate. The switching element includes a poly silicon pattern having at least one block. Grains are formed in each of the at least one block that are extended in a plurality of directions. The pixel electrode is electrically connected to the switching element. Therefore, current mobility and design margin of the switching element are improved.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: July 29, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soong-Yong Joo, Myung-Koo Kang
  • Patent number: 7405465
    Abstract: In deposited silicon, n-type dopants such as phosphorus and arsenic tend to seek the surface of the silicon, rising as the layer is deposited. When a second undoped or p-doped silicon layer is deposited on n-doped silicon with no n-type dopant provided, a first thickness of this second silicon layer nonetheless tends to include unwanted n-type dopant which has diffused up from lower levels. This surface-seeking behavior diminishes when germanium is alloyed with the silicon. In some devices, it may not be advantageous for the second layer to have significant germanium content. In the present invention, a first heavily n-doped semiconductor layer (preferably at least 10 at % germanium) is deposited, followed by a silicon-germanium capping layer with little or no n-type dopant, followed by a layer with little or no n-type dopant and less than 10 at % germanium. The germanium in the first layer and the capping layer minimizes diffusion of n-type dopant into the germanium-poor layer above.
    Type: Grant
    Filed: December 9, 2005
    Date of Patent: July 29, 2008
    Assignee: SanDisk 3D LLC
    Inventor: S. Brad Herner
  • Patent number: 7405466
    Abstract: A method of simultaneously bonding components, comprising the following steps. At least first, second and third components are provided and comprise: at least one glass component; and at least one conductive or semiconductive material component. The order of stacking of the components is determined to establish interfaces between the adjacent components. A hydrogen-free amorphous film is applied to one of the component surfaces at each interface comprising an adjacent: glass component; and conductive or semiconductive component. A sol gel with or without alkaline ions film is applied to one of the component surfaces at each interface comprising an adjacent: conductive or semiconductive component; and conductive or semiconductive component. The components are simultaneously anodically bonded in the determined order of stacking.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: July 29, 2008
    Assignee: Agency for Science, Technology and Research
    Inventors: Jun Wei, Stephen Chee Khuen Wong, Yongling Wu, Fern Lan Ng
  • Patent number: 7405467
    Abstract: A power module package structure is disclosed. The control circuits are fabricated on a circuit plate, instead of fabricating them directly on a main substrate. The fabrication cost is reduced because the size of the substrate is shrunk. Furthermore, the power chips are placed on a material with high thermal conductivity. The heat produced from the power chips can be transmitted quickly. Thus, the reliability of the power module package can be improved.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: July 29, 2008
    Assignee: Cyntec Co., Ltd.
    Inventors: Chun-Tiao Liu, Da-Jung Chen, Chun-Liang Lin, Jeng-Jen Li, Cheng Chieh Hsu, Chau Chun Wen
  • Patent number: 7405468
    Abstract: A plastic package includes a plurality of terminal members each having an outer terminal, an inner terminal, and a connecting part connecting the outer and the inner terminal; a semiconductor device provided with terminal pads connected to the inner terminals with bond wires; and a resin molding sealing the terminal members, the semiconductor device and the bond wires therein. The inner terminals of the terminal members are thinner than the outer terminals and have contact surfaces. The upper, the lower and the outer side surfaces of the outer terminals, and the lower surfaces of the semiconductor device are exposed outside. The inner terminals, the bond wires, the semiconductor device and the resin molding are included in the thickness of the outer terminals.
    Type: Grant
    Filed: April 9, 2004
    Date of Patent: July 29, 2008
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Masachika Masuda, Chikao Ikenaga
  • Patent number: 7405469
    Abstract: A semiconductor chip is sealed by resin without covering an outer terminal of a semiconductor device having a power transistor. A semiconductor chip having a power transistor is housed within a recess of a metal cap while a drain electrode on a first surface of the semiconductor chip is bonded to a bottom of the recess via a connection material. A gate electrode and a source electrode are formed on a second surface opposite to the first surface of the semiconductor chip, and the gate electrode and the source electrode are bonded with metal plate terminals 6G, 6S via connection materials 5b, 5c. In addition, the semiconductor chip is sealed by a resin sealing body with mounting-surfaces of the metal plate terminals 6G, 6S being exposed. Mounting surfaces of the metal plate terminals 6G, 6S and a third part of the metal cap are bonded to electrodes on a mounting board 10 via connection materials 5e, 5f and 5g.
    Type: Grant
    Filed: April 13, 2007
    Date of Patent: July 29, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Hidemasa Kagii, Akira Muto, Ichio Shimizu, Katsuo Arai, Hiroshi Sato, Hiroyuki Nakamura, Masahiko Osaka, Takuya Nakajo, Keiichi Okawa, Hiroi Oka
  • Patent number: 7405470
    Abstract: A storage apparatus 10 is disclosed, that comprises a wiring substrate 11 having a first surface and a second surface, a flat type external connection terminal 12a disposed on the first surface of the wiring substrate 11, a semiconductor device 14 disposed on the second surface of the wiring substrate 11 and having a connection terminal 14a connected to the flat type external connection terminal 12a, a molding resin 15 for coating the semiconductor device 14 on the second surface of the wiring substrate 11, a card type supporting frame 10a having a concave portion or a hole portion fitting the wiring substrate 11, the semiconductor device 14, and the molding resin 15 in such a manner that the flat type external connection terminal 12a is exposed to the first surface of the wiring substrate 11, and adhesive resin a adhering integrally the flat type external connection terminal 12a, the wiring substrate 11, the semiconductor device 14, the molding resin 15, and the card type supporting frame 10a.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: July 29, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Iwasaki
  • Patent number: 7405471
    Abstract: An improved multi-chip module includes a circuit board having an array of electrical interconnection pads to which are mounted a plurality of IC package units. Each IC package unit includes multiple IC packages, which are mounted on opposite sides of a package carrier. The package units may be mounted on one or both sides of the circuit board. A variety of package carriers are used to create a number of different modules. One type of package carrier has a pair of major planar surfaces. Each planar surface incorporates electrical contact pads. At least one IC package is surface mounted on each major planar surface, by interconnecting the connection elements, or leads, of the package with the contact pads on the planar surface, to form the IC package unit. Another type of package carrier substrate has a multiple recesses for back-to-back surface mounting of the IC packages. The package also includes in various versions heat sinks.
    Type: Grant
    Filed: August 26, 2003
    Date of Patent: July 29, 2008
    Assignee: Legacy Electronics, Inc.
    Inventors: Kenneth J. Kledzik, Jason C. Engle
  • Patent number: 7405472
    Abstract: A semiconductor device, which is constituted in such a way that a pad portion of a logic chip is connected to an element region of a semiconductor chip with a bump bonding, is capable of achieving high speed operability of the elements, because delay of transmission of an electrical signal is suppressed. a logic chip is directly connected to a DRAM, therefore, it is possible to suppress an increase of load capacitance caused by interconnects, and securing a wide bus width by a multiple pin connection. As a result, it becomes possible to enhance performance of the semiconductor device upon suppressing delay of information transmission from the logic chip to the DRAM.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: July 29, 2008
    Assignee: NEC Electronics Corporation
    Inventor: Masaya Kawano
  • Patent number: 7405473
    Abstract: Techniques are provided for placing and routing vias that conduct signals through a connector between two electrical units. Vias that conduct a first set of signals are placed next to vias that provide return paths for the first set of signals to reduce cross-talk or impedance. Vias that conduct input or output signals can be placed next to vias that provide return paths for the input or output signals to reduce cross-talk. The vias that provide the return paths can conduct, for example, ground signals, power supply signals, or both. Vias that conduct power supply signals can be placed next to vias that provide return paths for the power supply signals to reduce impedance. The vias that provide the return paths for the power supply signals can conduct, for example, ground signals. The via configurations reduce cost and increase yield, and the via configurations are modular.
    Type: Grant
    Filed: November 23, 2005
    Date of Patent: July 29, 2008
    Assignee: Altera Corporation
    Inventors: Hong Shi, Yuanlin John Xie
  • Patent number: 7405474
    Abstract: In one embodiment, a device is packaged using a low-cost thermally enhanced ball grid array (LCTE-BGA) package. The device may include a die with its backside mounted to the bottom side of a multi-layer packaging substrate. Thermal vias may be formed through the substrate to allow heat to be conducted away from the backside of the die to a top most metal layer of the substrate. Thermal balls may be attached to the bottom side of the substrate on the same plane as the die.
    Type: Grant
    Filed: October 7, 2005
    Date of Patent: July 29, 2008
    Assignee: Cypress Semiconductor Corporation
    Inventor: Brenor L. Brophy
  • Patent number: 7405475
    Abstract: A tape automated bonding (TAB) structure which includes a flex tape having a conductive lead pattern formed thereon. The conductive lead pattern includes a plurality of leads configured to form an inner lead bond (ILB) portion of the TAB structure. At least one of the plurality of leads is internally routed and has a contact exposed interior to the ILB portion of the TAB structure.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: July 29, 2008
    Assignee: Cardiac Pacemakers, Inc.
    Inventors: Nick A. Youker, Ronald L. Anderson, John E. Hansen
  • Patent number: 7405476
    Abstract: An apparatus includes a first semiconductor die and at least one further semiconductor die. A substrate is attached to the first die and the further die and has an electrical interconnect pattern that interconnects contacts on the first die with respective contacts on the further die. Features of the interconnect pattern have positions on the substrate with smaller tolerances relative to positions of the contacts on the first die than to positions of the contacts on the further die.
    Type: Grant
    Filed: October 27, 2005
    Date of Patent: July 29, 2008
    Assignee: LSI Logic Corporation
    Inventor: Gary S. Delp
  • Patent number: 7405477
    Abstract: A package-board co-design methodology preserves the signal integrity of high-speed signals passing from semiconductor packages to application PCBs. An optimal architecture of interconnects between package and PCB enhances the signal propagation, minimizes parasitic levels, and decreases electromagnetic interference from adjacent high frequency signals. The invention results in devices with superior signal quality and EMI shielding properties with enhanced capability for carrying data stream at multiple-gigabit per second bit-rates.
    Type: Grant
    Filed: December 1, 2005
    Date of Patent: July 29, 2008
    Assignee: Altera Corporation
    Inventors: Yuming Tao, Jon M. Long, Anilkumar Raman Pannikkat
  • Patent number: 7405478
    Abstract: A substrate package structure includes bumps disposed on a surface side of a first substrate and a surface side of a second substrate. The bump at the first substrate and the bump at the second substrate are press-fitted to each other while the one surface of the first substrate and the one surface of the second substrate are confronted to each other, thereby connecting the first and second substrates to each other. The bump at the first substrate is constructed so that the tip portion thereof is designed to have a flat surface, and the bump at the second substrate is constructed so that the tip portion is designed to have a projecting portion narrower than the tip portion of the bump at the first substrate.
    Type: Grant
    Filed: November 21, 2005
    Date of Patent: July 29, 2008
    Assignee: DENSO CORPORATION
    Inventors: Katsumi Ishikawa, Hiroshi Takei, Nobuya Makino, Tetsuro Yano
  • Patent number: 7405479
    Abstract: A wired circuit board having terminals that can ensure large electrical connection areas while preventing shorting of adjacent terminals, to ensure that the terminals are electrically connected with external terminals through molten metal. An insulating base layer 3 is formed on a supporting board 2 so that insulating concave portions 13 are formed at portions thereof where external connecting terminals 8 are to be formed. A conductive pattern 4 is formed on the insulating base layer 3 so that a number of lines of wire 4a, 4b, 4c, 4d, the magnetic head connecting terminals 7, and the external connecting portions 8 are integrally formed, and conductive concave portions 9 are formed in the external connecting terminals 8. Thereafter, an insulating cover layer 10 is formed on the insulating base layer 3 so that the magnetic head connecting terminals 7 and the external connecting terminals 8 are exposed from the insulating cover layer 10.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: July 29, 2008
    Assignee: Nitto Denko Corporation
    Inventors: Hitoki Kanagawa, Tetsuya Ohsawa, Yasunari Ooyabu
  • Patent number: 7405480
    Abstract: A flexible electronic display device is provided comprising a substrate; an imaging layer zone; a transparent superstrate; and a thermal control layer. The device is able to resist thermal deformation caused by the heating generated by the operation of the display.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: July 29, 2008
    Assignee: Eastman Kodak Company
    Inventors: Edward P. Furlani, Richard W. Wien, Tabrez Y. Ebrahim, David L. Patton
  • Patent number: 7405481
    Abstract: In an integrated circuit chip, a conductive line is formed in a first IMD layer. The conductive line is formed of a conductive line material that tends to form an oxide when exposed to an oxygen-containing substance. A glue layer is formed on the conductive line. The glue layer is formed of a non-oxygen-containing material capable of providing an oxygen barrier over the conductive line. The glue layer has a hardness greater than that of the conductive line. The glue layer preferably has a thickness between about 15 angstroms and about 75 angstroms. The etch stop layer is formed on the glue layer. The etch stop layer has a hardness greater than that of the glue layer. A second IMD layer is formed on the etch stop layer. The etch stop layer and/or the second IMD layer may be formed with a material comprising oxygen without oxidizing the conductive line.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: July 29, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Keng-Chu Lin, Yung-Cheng Lu, Shwang-Ming Cheng
  • Patent number: 7405482
    Abstract: A high-k dielectric film, a method of forming the high-k dielectric film, and a method of forming a related semiconductor device are provided. The high-k dielectric film includes a bottom layer of metal-silicon-oxynitride having a first nitrogen content and a first silicon content and a top layer of metal-silicon-oxynitride having a second nitrogen content and a second silicon content. The second nitrogen content is higher than the first nitrogen content and the second silicon content is higher than the first silicon content.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: July 29, 2008
    Assignee: Infineon Technologies AG
    Inventors: Kil-Ho Lee, Chan Lim
  • Patent number: 7405483
    Abstract: A circuit board assembled with an electronic package having a first and a second inner leads is provided. The first inner lead has a first and a second ends. The circuit board includes an insulating layer, a first pad, a second pad, an extension portion, a conductive via, and a ground layer. The first and the second pads are disposed on the insulating layer. The first end of the first inner lead is electrically connected to the second pad. The extension portion disposed on the insulating layer is electrically connected to the first pad and extends to the position under the second end of the first inner lead. The conductive via passing through the insulating layer is electrically connected to the extension portion and under the second end of the first inner lead. The ground layer disposed on the insulating layer is electrically connected to the conductive via.
    Type: Grant
    Filed: January 18, 2007
    Date of Patent: July 29, 2008
    Assignee: VIA Technologies, Inc.
    Inventors: Sheng-Yuan Lee, Hsiao-Chu Lin
  • Patent number: 7405484
    Abstract: An adhesive film is formed on an electrode film, and a coating film is formed thereon. Nickel, chrome, molybdenum, tungsten, aluminum or an alloy of them is used as a constituent material of the adhesive film. Gold, silver, platinum or an alloy of them is used as a constituent material of the coating film.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: July 29, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ryosuke Usui, Hideki Mizuhara, Takeshi Nakamura
  • Patent number: 7405485
    Abstract: A semiconductor device provided with a first semiconductor chip having a first functional surface formed with a first functional element and a first rear surface, a second semiconductor chip having a second functional surface which is formed with a second functional element, the second functional surface having a region opposed to the first functional surface of the first semiconductor chip and a non-opposed region defined outside the opposed region, a connection member electrically connecting the first functional element and the second functional element, an insulation film continuously covering the non-opposed region of the second semiconductor chip and the first rear surface of the first semiconductor chip, a rewiring layer provided on a surface of the insulation film, a protective resin layer covering the rewiring layer, and an external connection terminal projecting from the rewiring layer through the protective resin layer.
    Type: Grant
    Filed: June 9, 2005
    Date of Patent: July 29, 2008
    Assignee: Rohm Co., Ltd.
    Inventors: Kazumasa Tanida, Tadahiro Morifuji, Osamu Miyata
  • Patent number: 7405486
    Abstract: In stack packaging, an IC chip in an upper layer and an IC chip in a lower layer are insulated from each other by use of an insulating adhesive and the like. Thus, if an analog IC chip is stacked in the upper layer, a substrate is set in a floating state. Accordingly, there arises a problem that desired characteristics cannot be obtained. A conductive layer is disposed on an IC chip, and an analog IC chip is fixed on the conductive layer. The conductive layer is connected to a fixed potential pattern through a bonding wire and the like. Thus, a fixed potential can be applied to a rear surface (substrate) of the analog IC chip. Consequently, a mounting structure including the analog IC chip stacked in the upper layer can be realized. In addition, versatility of stack packaging for a circuit device including the analog IC chip can be improved, and a mounting area can be reduced. Moreover, characteristics can be improved.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: July 29, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Atsushi Kato
  • Patent number: 7405487
    Abstract: A method and apparatus for encapsulating microelectronic devices. In one embodiment, the method includes removing a portion of encapsulating material that at least partially surrounds a microelectronic substrate by directing a source of laser radiation toward the encapsulating material. The method can further include exposing a surface of the microelectronic substrate, for example, to enhance a rate at which heat is transferred away from the microelectronic substrate. Alternatively, the encapsulating material can be removed to form heat transfer structures, such as pins or ribs, also to enhance a rate at which heat is transferred away from the microelectronic substrate. In still another embodiment, a portion of the encapsulating material or a support member to which the substrate is attached can be removed to define interlocking features that allow one microelectronic substrate package to be stacked on another and to resist relative movement between the two packages.
    Type: Grant
    Filed: August 12, 2002
    Date of Patent: July 29, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Joseph M. Brand
  • Patent number: 7405488
    Abstract: There is provided a power generator including a plurality of power generation elements, and a fuel supply portion that communicates with the plurality of power generation elements through a fuel supply passage, the plurality of power generation elements are housed in a plurality of independent power generation casings having vent portions, and the plurality of power generation casings are movably connected via a connecting portion so as to enter a housing state where the casings are placed on top of each other and a power generation state where the casings are separated. There is provided a portable power generator that can ensure sufficient ventilation and power generation areas in use (during power generation), and becomes compact when carried.
    Type: Grant
    Filed: August 16, 2006
    Date of Patent: July 29, 2008
    Assignee: Hitachi, Ltd.
    Inventor: Koji Suso
  • Patent number: 7405489
    Abstract: The invention relates to a wave power assembly having a hull and a linear electric generator. The rotor of the generator is connected with the hull. The stator thereof is arranged to be anchored at a sea/lake bottom. According to an embodiment of the invention, the rotor is mounted in the cross direction by means of rolling elements. These are arranged between rolling surfaces on the rotor and support surfaces of a support means. The rolling elements are arranged to roll against the rolling surfaces and the support surfaces. The invention also relates to a wave power plant built up from wave power assemblies according to the invention. Furthermore, the invention relates to a use of the wave power assembly and a method for generating electric energy.
    Type: Grant
    Filed: March 22, 2004
    Date of Patent: July 29, 2008
    Assignee: Seabased AB
    Inventors: Mats Leijon, Hans Bernhoff
  • Patent number: 7405490
    Abstract: A wind turbine includes a turbine rotor with at least one blade and a generator with a rotor and a stator. The turbine rotor is mechanically coupled with the rotor of the generator. A diode rectifier is electrically coupled to the stator of the generator. A direct current link is electrically coupled with the diode rectifier. A line converter is electrically coupled with the direct current link.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: July 29, 2008
    Assignee: Converteam GmbH
    Inventor: Georg Moehlenkamp
  • Patent number: 7405491
    Abstract: There is provided an electric power generating device which includes a generator which is constituted by an interior permanent magnet (IPM) synchronous generator, and is connected to a steam turbine without interposition of a reduction gear, cooling means which flows a liquid coolant used to cool the generator, and a frequency converter which converts an electric power generated by the generator into an electric power at a commercial frequency, and outputs the converted electric power, the cooling means includes a circulation passage to which a tank which is used to store the liquid coolant (oil), a cooler which cools the liquid coolant, and a pump which pressure-feeds the liquid coolant are connected, and through which the liquid coolant circulates, and this configuration enables the generator to operate at a high rotational speed, thereby efficiently utilizing the steam energy.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: July 29, 2008
    Assignee: Kobe Steel, Ltd.
    Inventors: Masaki Matsukuma, Yasuo Fukushima, Toshikazu Miyaji, Katsuhiro Uehara
  • Patent number: 7405492
    Abstract: A twin ignition system for automotive vehicles and the like is disclosed and claimed. Ignition system #1 comprises a known ignition system which allows electrical access to the engine starter, and allows full function of all facilities with which the vehicle is equipped. Ignition system #2 has its own subsystems which can be set to control vehicle speed and/or other vehicle operating parameters. Each system can be accessed by its own discreet key which does not allow access to the other ignition system.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: July 29, 2008
    Inventor: Peter William Petersen
  • Patent number: 7405493
    Abstract: A double pole LED outlet switch includes a power outlet receptacle with upper and lower receptacles, and a double pole double throw (DPDT) switch. The DPDT switch is positionable between an UNSWITCHED position and a SWITCHED position. The DPDT switch enables a user to provide either continuous power or switched power to at least the lower receptacle outlet double pole LED outlet switch. The double pole LED outlet switch may be configured as either an independent or a dual double pole LED outlet switch. Both the independent and dual outlet double pole LED outlet switches are most efficiently utilized if installed during construction. A post construction double pole LED outlet switch receptacle may be realized in two types of configurations. One configuration is a master unit and one configuration is a slave unit.
    Type: Grant
    Filed: November 13, 2006
    Date of Patent: July 29, 2008
    Inventor: Robert J. Leo
  • Patent number: 7405494
    Abstract: Paralleled uninterruptible power supplies (UPSs) including respective pulse-width modulation (PWM) power converter circuits coupled in common to an AC load bus have PWM cycles that are synchronized. In particular, sampling of control inputs of the PWM power converter circuits may be synchronized, such that, for example, sampling of control inputs to the PWM power converter circuits occurs at substantially the same time for each of the PWM power converter circuits. A common phase reference corresponding to an AC voltage phase for the AC load bus may be provided, and the PWM cycles of each of the power converter circuits may synchronized, e.g., phase locked, to the common phase reference. More particularly, the respective PWM cycles of the UPSs may be phase locked to phase locked sinusoidal reference signals generated at each of the UPSs. Sampling for other control functions may also be synchronized to the PWM cycles.
    Type: Grant
    Filed: July 7, 2004
    Date of Patent: July 29, 2008
    Assignee: Eaton Corporation
    Inventors: Frederick Tassitino, Jr., Hans-Erik Pfitzer, Jason S. Anderson, Michael Westerfield
  • Patent number: 7405495
    Abstract: A DC/DC voltage converter between a high-voltage electrical network and a low-voltage electrical network comprises a plurality of cells connected in parallel. Each cell comprises a chopper DC/DC converter and a single protection transistor connected in a high-voltage portion of the converter thereby enabling any of the cells to be taken out of service independently of the other cells while minimizing power consumption in normal operation.
    Type: Grant
    Filed: January 22, 2003
    Date of Patent: July 29, 2008
    Assignee: Johnson Controls Automotive Electronics
    Inventors: Nicolas Guillarme, Bruno Condamin
  • Patent number: 7405496
    Abstract: A method and transfer circuit topology for a redundant power converter for switching a load between power conversion circuits in a redundant system. The transfer circuit topology includes a first contactor and a second contactor each having an input coupled to a source and an output coupled to a controlled commutating current path. The controlled commutating current path is coupled to the load for switching between the redundant power converters without interrupting current to the load.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: July 29, 2008
    Assignee: General Electric Company
    Inventors: Robert Gregory Wagoner, Scott Charles Frame, Brian Eric Lindholm, Pedro Monclova
  • Patent number: 7405497
    Abstract: An ultra-high-efficiency switching power supply system integrating, into a single package, power conversion switches for multiple power supplies, an input power switching block, an output power switching block, control logic for controlling the power conversion switches and control input/output ports. This integrated multiple power supply package is called a Power Bridge and preferably implements the integrated components as one or more integrated circuit chips housed in the package housing. The Power Bridge is a bridge between the microprocessor of a portable computer and its internal and external power sources. The power supply system facilitates board design because the ultra-high-efficiency power module generally requires less space and generates less heat than conventional power supply circuitry.
    Type: Grant
    Filed: April 13, 2004
    Date of Patent: July 29, 2008
    Assignee: Electrovaya Inc.
    Inventors: James K. Jacobs, Sankar DasGupta, David Vandermeer
  • Patent number: 7405498
    Abstract: A multi-phase active filter includes a group of power cells electrically connected in a three-phase configuration, a precharging circuit, and a controller that controls the voltage delivered to the plurality of power cells. Each power cell includes an inverter having a pair of direct current (DC) terminals, at least one capacitor electrically connected in parallel with the inverter, and an energy dissipating circuit that is electrically connected in parallel with the inverter. The energy dissipating circuit of each power cell self-regulates DC voltage within the cell.
    Type: Grant
    Filed: May 16, 2006
    Date of Patent: July 29, 2008
    Assignee: Siemens Energy & Automation, Inc.
    Inventors: Mukul Rastogi, Peter Hammond, Stan Simms
  • Patent number: 7405499
    Abstract: Amplitude, phase and frequency of a sine wave to be generated are calculated on the basis of feature quantity s1 delivered to feature quantity detecting means (2), and are sent to initialization means (3). The initialization means (3) calculates first two points of the sine wave to send the points thus calculated to oscillator (sine wave generating means) (4) as initial value s4. The oscillator (4) sequentially calculates values of respective sample points of waveform by using recurrence formula in accordance with initial value or values instructed from the initialization means (3) to thereby generate a sine wave signal. Thus, sine wave generation is performed without performing modulo-addressing.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: July 29, 2008
    Assignee: Sony Corporation
    Inventors: Chisato Kemmochi, Akira Inoue, Masayuki Nishiguchi
  • Patent number: 7405500
    Abstract: A wire bonding apparatus 10 including an X table 18 guided to move in the X direction on an XY table base 14 and a driving motor 20 mounted on a motor base 16 with the movable element 22 of the driving motor 20 connected to the X table 18. The motor main body 24 is guided by a pair of motor guides 26 so as to be movable in the X direction via the laminated bodies 40. In each laminated body 40, viscoelastic flat rubber plates that have a spring element and a damping element, and flat rigid plates, are alternately disposed and laminated, so that the rigidity is large in the direction perpendicular to the laminated surfaces, and the rigidity is small in the direction parallel to the laminated surfaces, and the laminated bodies have a recovery force and a damping force due to the viscoelasticity.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: July 29, 2008
    Assignee: Kabushiki Kaisha Shinkawa
    Inventor: Toru Maeda
  • Patent number: 7405501
    Abstract: An electric generator is disclosed, which comprises: at least a magnet, each having more than two poles; and at least a claw-pole set, each being composed of an inner claw-pole and an outer claw-pole; wherein, the inner claw-pole and the outer claw-pole are interlaced arranged and used for guiding magnetic flux; the inner claw-pole is connected to an iron core whose outer diameter is smaller than the magnet and thus the loop of the inner claw-pole and the outer claw-pole is conducted; the core is winded by a solenoid coil; the number of claws of the inner claw-pole is the half of the pole number of the magnet while the outer claw-pole is the same, so that, as the magnet is move relative to the claw-pole set, the magnetic flux passing through the solenoid coil will change continuously and thus an induction electromotive force is generated.
    Type: Grant
    Filed: October 26, 2006
    Date of Patent: July 29, 2008
    Assignee: Industrial Technology Research Institute
    Inventors: Wen-Yang Peng, Fuh-Yu Chang, Ching-Hsiang Cheng
  • Patent number: 7405502
    Abstract: Provided are a motor and a washing machine using the motor. The motor has a stator, a rotor, a rotor frame, a permanent magnet, and a comb polarizing ring. The rotor rotates against the stator. The permanent magnet is installed on the rotor frame and has protrusions with alternating North and South polarities. The comb polarizing ring includes a plurality of teeth disposed between the protrusions of the permanent magnet, and is formed of a material with a magnetism that is weaker than a magnetism of the protrusions.
    Type: Grant
    Filed: September 13, 2006
    Date of Patent: July 29, 2008
    Assignee: LG Electronics Inc.
    Inventors: Cha Seung Jun, Byoung Wook Min