Abstract: A light emitting device comprises a first metal member, a light emitting element mounted at one end of the first metal member, and a translucent covering material that covers at least the light emitting element, wherein the surface of the first metal member has a depression that determines the region where the translucent covering material is formed, and the inner wall of the depression is continuous.

Abstract: The present invention provides a lighting device package that is configured to enable degassing of the lighting device package. The lighting device package comprises a substrate upon which is operatively mounted one or more light-emitting elements and a retaining structure which is coupled to the substrate and configured to circumscribe the one or more light-emitting elements. In addition, the lighting device package includes an optically transmissive element, wherein two or more supports are configured to provide a separation between the optically transmissive element and the substrate or retaining structure. The volume defined by the substrate, retaining structure and the optically transmissive element, is partially or completely filled with an encapsulation material, thereby forming the lighting device package.

Abstract: The housing for a light fixture includes a plaster frame with an opening. The can light, having opened ends along the top and bottom, is positioned through the opening. A trim assembly and lamp assembly are connected to the bottom side of the can. An outer housing, having dimensions suitable for placing the housing between joists having sixteen inch centers, is connect to the plaster frame and about the top portion of the can. The outer housing includes a doubler panel positioned within the inner walls of the outer housing and having a geometry and size to match with and fit snugly into the upper portion of the outer housing. The open can allows for convection to draw the heat away from the lamp assembly and into the outer housing. The doubler panel evenly distributes the heat along the exterior surfaces of the housing.

Abstract: The invention is a motorcycle shock mounted illumination device. The invention features a base mount with metal strap for primary attachment to a motorcycle shock, an angled pair of light strips created from circuit boards and LEDs and attached to the base mount, and a tubular housing that also attaches to the base mount. The tubular housing is translucent and encloses the light strips. The generally rearward facing light strip is designed to flash in red when the motorcycle brakes are applied and the generally sideward facing light strip is designed to be generally on all the time in yellow or amber except when the motorcycle brakes are applied in which case the LEDs of the side facing strip turn off and on in a grouped sequence.

Abstract: A lighting system for a vehicle including a display panel and vehicle accessory includes a light source disposed within the display panel that illuminates the display panel. The display panel includes at least one aperture that selectively permits light from the light source to pass through the display panel to illuminate the vehicle accessory.

Abstract: A headlamp, developed especially for motor vehicle illumination, wherein the light source and reflector surfaces are fully concealed from the oncoming traffic users, having a light plane with fully adjusted height, operating according to the half-lens illumination principle, providing a long-distance illumination without glaring effect by preventing the all of the light rays generated at the light source from reaching to the eye level (EE) of oncoming traffic users. The preferred embodiment of the system (40, 50) consists of three independent reflector units (2, 3), (12, 13), (22, 23) with triple light pathway, designed similar to clover leaf, having a standard light source (1) located at their common first focal point (f1) mounted in a headlamp enclosure (20). The system consists of a lighting assembly that can be used not only in motor vehicle headlamp system but also in general lighting systems and in all optical devices. The system may be applied as an in-bulb structure.

Abstract: A vehicular lamp having a light source unit 30 provided inside a lamp chamber formed by a lamp body 10 and a front cover 20, wherein a millimeter wave radar 40 is provided inside the lamp chamber, and a light guide plate 60 is provided between the front cover 20 and the millimeter wave radar 40, and the light guide plate 60 is illuminated by the light source of the lamp or by a dedicated light source provided solely for the light guide plate 60.

Abstract: A headlight for motor vehicles comprising a light-shield mechanism having at least first and second rotary light shields for producing respectively at least first and second different light beams, wherein the shield mechanism also comprises at least one means of mechanically locating the idle position of the shield mechanism, and an actuator able to make the first and second light shields, turn in two directions of rotation.

Abstract: A lighting device for a vehicle includes: a light source; a light guide member that has a light-introducing part provided in a back surface side through which the light of the light source is introduced and finally emits the light from a front surface side; a part near the light-introducing part being thicker than an edge part of the light guide member, a plurality of reflecting parts and connecting parts being alternately formed continuously toward a direction separate from the light-introducing part in the back surface side, the reflecting parts respectively reflecting on interfaces the introduced light reaching there to form the light in the direction of the front surface of the light guide member; and a housing that is connected to a position between the edge part of the back surface of the light guide member and the light-introducing part and attached to the back surface side of the light guide member to house the light source.

Abstract: A vehicle headlamp can include a daytime running lamp with favorable light distribution characteristics. The vehicle headlamp can also include a headlight such as a low beam/high beam, a fog lamp, and the like. The vehicle headlamp can include a parabolic type reflector, a halogen bulb, and a driving circuit. The halogen bulb can include a first filament, a second filament and a shield member if necessary or desired. The first filament can be used as the above headlight, and the second filament adjacent the first filament can be used as the daytime running lamp. Because the second filament can be located at a closer position than the first filament with respect to the reflector, light emitted from the second filament can form a wider light distribution than that of the first filament. Therefore, the vehicle headlamp can provide a daytime running lamp with a favorable light distribution pattern along with the above headlight.

Abstract: A heat exchange structure includes a plurality of elongated air ducts. The heat exchange structure has an exterior heat exchange surface and interior heat exchange surfaces, the interior surfaces being in the elongated air ducts. The heat exchange structure includes a plurality of heat generators that are distributed on the exterior heat exchange surface along an elongated direction of the air ducts, in which air flowing in the air duct is heated successively by heat from the heat generators, and air flow in the air duct is enhanced by buoyancy of heated air.

Abstract: The light has a housing and a light disc, behind which a lighting unit is provided. The lighting unit is divided into at least two separate light-permeable and distanced light windows, having the same or different lighting functions. A partially light impermeable area is provided between them. In order to embody the light such that its divided light windows are perceived as a continuous lighting area, embodied in a simple fashion and produced cost-effectively, at least one additional light impermeable area is provided in the light impermeable area. Thereby, in spite of the divided light window, a continuous light window is discernible for the observer, as required by the legislature, when both light windows fulfill the same lighting function. The light is suitable as a tail light of motor vehicles.

Abstract: An illumination fiber optic ribbon includes optically-transmissive fibers which are adjacent to each other. At least two of the optically-transmissive fibers are twisted together to form a twisted segment. Where the two optically-transmissive fibers are not twisted forms a non-twisted segment. The twisted segments and non-twisted segments alternate along the length of the ribbon. Bends are disposed along the twisted segment and are formed by twisting adjacent optically-transmissive fibers. A light source is connected to one or both end of the optically-transmissive fibers. The light source emits a light flux into the ribbon so that light emits from the bends in the twisted segment.

Abstract: A light source device comprising: a point light source for emitting light; a light source substrate directly mounting the point light source; a light source substrate cover having a through hole or a notch in a position to which the point light source corresponds, the light source substrate cover arranged opposite to a surface of the light source substrate on which the point light source is mounted; and a support member for supporting the light source substrate, the support member arranged to be opposed to the reverse side of the mounting surface of the light source substrate, the support member has a substantially same size with the light source substrate; wherein the light source substrate cover and the support member sandwich the light source substrate to support the light source substrate.

Abstract: The present invention relates to a converter and a driving method thereof. The converter includes a main switch and a switching controller. The switching controller controls on/off of the main switch by using a first voltage corresponding to an output voltage and a first current flowing to the main switch. The switching controller determines a reference count according to the first voltage, and determines a peak value of the first current corresponding to a reference count and a switching frequency of the main switch.

Abstract: A technique for suppressing lowering of withstand voltage and lowering of breakdown resistance and reducing a feedback capacitance of a power MISFET is provided. A lateral power MISFET that comprises a trench region whose insulating layer is formed shallower than an HV-Nwell layer is provided in the HV-Nwell layer (drift region) formed on a main surface of a semiconductor substrate in a direction from the main surface to the inside. The lateral power MISFET has an arrangement on a plane of the main surface including a source layer (source region) and a drain layer (drain region) arranged at opposite sides to each other across a gate electrode (first conducting layer), and a dummy gate electrode (second conducting layer) that is different from the gate electrode is arranged between the gate electrode and the drain layer.

Abstract: Presented is a harmonic regulator that regulates a plurality of individual harmonics in a system having periodic torque disturbances to commanded values, including zero. For each harmonic being regulated, a feedback signal having at least one harmonic component due to the harmonic being regulated is transformed from a source reference frame to a harmonic reference frame of the harmonic being regulated to form a qd feedback signal. The qd feedback signal is subtracted from the commanded value to form a qd signal and regulated. The regulated qd signal is transformed to a destination reference frame to form a compensation signal and the compensation signal is added to a control signal to form a qd control signal that drives each harmonic being regulated towards the commanded value.

Abstract: An inverter capable of supplying power to utility grids of varying line voltages is described. In some examples, the inverter contains multiple output taps that are selected to output power to the utility grid based on the voltage of the utility grid. In some examples, the inverter includes a multi-pin connector that connects with one of multiple receptacles associated with a desired voltage configuration. In some examples, the inverter is capable of adapting to a defined line voltage in two steps.

Abstract: An exemplary power supply control circuit (200) includes a first port (201), a second port (202), a third port (203), a controllable switch (280), and a control circuit (270). The first and second ports are configured to receive a power supply voltage signal. The second and third ports are configured to output the power supply voltage signal to a load circuit. The controllable switch includes a control member (281) and a switch member (282 ). The control circuit is configured to control a working state of the control member. When the load circuit stops working, the control circuit controls the control member to control the switch member to be disconnected, so as to cut off the power supply voltage signal from outputting to the load circuit. A liquid crystal display (400) using the power supply control circuit is also provided.

Abstract: To provide a capacitor drop type power supply circuit that can withstand a surge-current generated at power-on by use of inexpensive elements without requiring a complicated circuit configuration. A capacitor drop type power supply circuit includes: an AC power supply (1) connected to a series circuit of a resistor (2), a first capacitor (3), and a first diode (4) whose cathode is connected to the first capacitor (3) ; a series circuit of a second diode (5) and a Zener diode (6), which is parallel-connected to the first diode (4); and a second capacitor (7) parallel-connected to the Zener diode (6), the circuit outputting a DC voltage generated across the second capacitor (7).

Abstract: Inverter bus structures, assemblies and associated methods are disclosed herein. One embodiment of the disclosure, for example, is directed to a power inverter including an inverter module for converting DC power to AC power, a printed circuit board carrying a capacitor array, a DC power source, and a bus structure. The bus structure is physically coupled each of the inverter module and the printed circuit board, and the bus structure electrically couples each of the inverter module, the printed circuit board to the DC power source.

Abstract: An SRAM device includes a first inverter; a second inverter cross-coupled with the first inverter; a first pass gate transistor connecting the first inverter to a bit line; and a second pass gate transistor connecting the second inverter to a complementary bit line, wherein the first or second pass gate transistor has a layout structure where a first distance between its gate conductive layer and its source contact is purposefully designed to be substantially different from a second distance between its gate conductive layer and its drain contact for reducing leakage current induced by misalignment of the gate conductive layer with respect to the source contact.

Abstract: A resistance semiconductor memory device of a three-dimensional stack structure, and a word line decoding method thereof, are provided.

Abstract: This invention relates to memory technology and new variations on memory array architecture to incorporate certain advantages from both cross-point and 1T-1Cell architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple memory cells, which can be stacked vertically above one another in a plurality of memory array layers arranged in a “Z” axis direction.

Abstract: A semiconductor device and method with a plurality of different one time programmable elements. One embodiment provides a semiconductor device having a plurality of different one time programmable elements that form a group of one time programmable elements, wherein at least one bit of information is jointly stored by the plurality of different one time programmable elements of the group.

Abstract: Disclosed is a semiconductor memory including ferroelectric capacitors. Memory cells each including a ferroelectric capacitor and an insulted-gate-type cell transistor are connected to a corresponding one of bit lines. Insulated-gate-type separating transistors are connected between multiple bit-line selecting transistors and multiple sense amplifiers, respectively. When the separating transistors are turned on, data retained in the sense amplifiers are capable of being written to the memory cells during the same time period substantially.

Abstract: A recording medium structure for a ferroelectric hard disc drive (HDD) and a method of fabricating the same are provided. A ferroelectric medium is deposited on a glass substrate so as to form a film with a uniform roughness, thereby improving data recording density and reducing the manufacturing costs of such a media structure. In addition, it is possible to remove a process problem occurring when a silicon substrate is employed. The method of fabricating a media structure comprises steps of (a) forming a nucleation template layer on a glass substrate; (b) forming a conductive layer on the nucleation template layer; (c) forming a ferroelectric layer on the conductive layer; and (d) forming a diamond-like carbon (DLC) layer and a lubricant layer in sequence on the ferroelectric layer.

Abstract: A first DRAM section including a first memory cell having a first capacitance and a second DRAM section including a second memory cell having a second capacitance different from the first capacitance are provided on the same semiconductor substrate.

Abstract: N-valued re-circulating latches using n-valued reversible inverters with n>3 are disclosed. Latches using n-valued self-reversing inverters are provided; latches using n-valued universal inverters are provided; and latches using inverters which are not self-reversing or universal are also provided. A latch may use two individually controlled gates. It may also use one individually controlled gate. N-valued latches are provided wherein a state is represented by a signal being an independent instance of a physical phenomenon. A latch not using absence-of-signal as a state is also provided.

Abstract: A direct writing method of a magnetic memory cell is provided. The magnetic memory cell includes a magnetic free stacked layer having a bottom and a top ferromagnetic layer. The bottom and top ferromagnetic layers respectively have a bi-directional easy axis in substantially the same direction. The method includes applying a first magnetic field in the direction of the bi-directional easy axis and performing a writing operation. To write a first memory state, a second magnetic field is supplied at a first side of the bi-directional easy axis with a first including angle. To write a second memory state, a third magnetic filed is supplied at a second side of the bi-directional easy axis with a second including angle. At least one of the bottom and top ferromagnetic layers has a unidirectional easy axis in different direction from the bi-directional easy axis.

Abstract: An integrated circuit memory device may include an integrated circuit substrate, and a multi-bit memory cell on the integrated circuit substrate. The multi-bit memory cell may be configured to store a first bit of data by changing a first characteristic of the multi-bit memory cell and to store a second bit of data by changing a second characteristic of the multi-bit memory cell. Moreover, the first and second characteristics may be different. Related methods are also discussed.

Abstract: A memory device including a memory cell comprising phase change material is described along with methods for programming the memory device. A method for programming disclosed herein includes applying an increasing first voltage across the memory cell and monitoring current in the memory cell to detect a beginning of a phase transition of the phase change material. Upon detection of the beginning of a phase transition of the phase change material, the method includes applying a second voltage across the memory cell that is a function of the level of the first voltage upon detection of the beginning of a phase transition of the phase change material.

Abstract: One embodiment of the present invention includes a memory element having a composite free layer including a first free sub-layer formed on top of the bottom electrode, a nano-current-channel (NCC) layer formed on top of the first free sub-layer, and a second free sub-layer formed on top of the NCC layer, wherein when switching current is applied to the memory element, in a direction that is substantially perpendicular to the layers of the memory element, local magnetic moments of the NCC layer switch the state of the memory element.

Abstract: A storage element includes a storage layer for holding information depending on a magnetization state of a magnetic material; and a magnetization fixed layer in which magnetization direction is fixed, that is arranged relative to the storage layer through a nonmagnetic layer. The magnetization direction of the storage layer is changed with application of an electric current in a laminating direction to enable information to be recorded to the storage layer. A plurality of magnetization regions respectively having magnetization components in laminating directions and having magnetizations in different directions from each other are formed in the magnetization fixed layer or on an opposite side of the magnetization fixed layer relative to the storage layer.

Abstract: An integrated circuit with magnetic memory has a silicon transistor layer, at least one magnetic memory layer, and a metal routing layer. The silicon transistor layer is arranged to generate several logic operation functions. The magnetic memory layer is arranged to store the data required by the logic operation functions. The metal routing layer has several conducting lines to transmit the data between the silicon transistor layer and the magnetic memory layer.

Abstract: A semiconductor memory device has a semiconductor substrate, first select transistors formed on the surface of said semiconductor substrate, first dummy transistors formed above said first select transistors, a plurality of memory cell transistors formed above said first dummy transistors so as to extend in a direction perpendicular to the surface of said semiconductor substrate, each of said memory cell transistor including an insulating layer having a charge-accumulating function, second dummy transistors formed above said memory cell transistors, and second select transistors formed above said second dummy transistors; wherein a first potential is provided to the gate electrodes of said first select transistors and the gate electrodes of said first dummy transistors and a second potential is provided to the gate electrodes of said second select transistors and the gate electrodes of said second dummy transistors at the time of write operation to write data to said memory cell transistors.

Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device includes an electrically floating body region, and a gate is disposed over a first portion of the body region. The device includes a source region adjoining a second portion of the body region, the second portion adjacent the first portion and separating the source region from the first portion. The device includes a drain region adjoining a third portion of the body region, the third portion adjacent the first portion and separating the drain region from the first portion.

Abstract: A memory includes a plurality of flash cells and circuitry for programming a first cell to store first data and one or more second cells to store second data. Either the circuitry itself, or a controller of he memory, or a host of the memory by executing driver code, causes the programming of the first cell to be in accordance with the second data, with at least a portion of the programming of the first cell being effected before any of the programming of the second cell(s).

Abstract: A high voltage regulator may include a first regulating unit, a second regulating unit, and an output node. The first regulating unit regulates the program voltage in a voltage-level-up interval of a program voltage of a memory cell. The second regulating unit regulates the program voltage in a voltage-level-down interval of the program voltage. The output node outputs the regulated program voltage.

Abstract: A method for reading a non-volatile memory arranged in columns and rows which reduces adjacent cell coupling, sometimes referred to as the Yupin effect. The method includes the steps of: selecting a bit to be read in a word-line; reading an adjacent the word line written after word line; and reading the selected bit in the word line by selectively adjusting at least one read parameter. In one embodiment, the read parameter is the sense voltage. In another embodiment, the read parameter is the pre-charge voltage. In yet another embodiment, both the sense and the pre-charge voltage are adjusted.

Abstract: As part of the present invention, a memory cell may be operated using reference cells having a threshold offset circuit. According to some embodiments of the present invention, a threshold offset value may be determined for a memory cell to be operated based on a location (e.g. memory segment within a memory array) of the memory cell. An input offset circuit of a global reference cell may be adjusted by the threshold offset value for the memory cell; and the memory cell may be operated (e.g. read, written or erased) using the global reference cell whose input offset circuit has been adjusted by the threshold offset value. According to some embodiments of the present invention global reference cells may consist of multiple sets of reference cells, wherein, according to some aspects, each set of the multiple sets of reference cells may be used for operating a different memory array segment.

Abstract: Data are stored in cells of a flash memory by assigning a first portion of the data to be stored in a first cell and a second portion of the data to be stored in one or more second cells. The first cell is programmed to store the first portion in accordance with the second portion. The second cell(s) is/are programmed to store the second portion. At least a portion of the programming of the first cell is effected before any of the programming of the second cell(s).

Abstract: A method for data storage in a memory that includes a plurality of analog memory cells includes storing data in the memory by writing first storage values to the cells. One or more read reference levels are defined for reading the cells, such that at least one of the read reference levels is negative. After storing the data, second storage values are read from the cells using the read reference levels, so as to reconstruct the stored data. In another disclosed method, data is stored in the memory by mapping the data to first storage values selected from a set of the nominal storage values, and writing the first storage values to the cells. The set of nominal storage values is defined such that at least one of the nominal storage values is negative.

Abstract: A charge loss restoration method detects a memory cell having a tendency of a charge loss within a memory cell array of an electrically writable and erasable nonvolatile semiconductor memory device, using a charge loss detecting reference cell having a threshold value set between a threshold value of a read reference cell and a threshold value of a write verify reference cell, where the threshold value of the write verify reference cell is higher than the threshold value of the read reference cell, and restores the memory cell having the tendency of the charge loss by making an additional write thereto.

Abstract: A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and a second page into a second primary data cache simultaneously, the first and second pages loaded from different blocks of flash memory. Data from the first primary data cache is stored in a first secondary data cache, and data from the second primary data cache is stored in a second secondary data cache. Data is sequentially provided from the first and second secondary data caches by a multiplexer coupled to the first and second data caches.

Abstract: An object of the present invention is to provide a memory system that offers enhanced security of ROM code that is data whose contents can be utilized for a given purpose in its intact form. In a memory system, data is read from a memory according to at least two or more addresses outputted from an address generator, from individual pages uniquely specified respectively by the addresses. A data generator generates one piece of data on the basis of the at least two or more pieces of data read from the individual pages.

Abstract: Data read from memory cells of one page in a memory cell array that corresponds to a page address of a copy source is sensed and latched by a sense/latch circuit. The sense/latch circuit has a plurality of latch circuits, and the plurality of latch circuits is specified according to the column address. The latch circuit specified in accordance with the column address is supplied with the data to be rewritten. The latch circuit specified in accordance with its address latches the data to be rewritten, whereby rewriting of the data is performed. The data of one page after rewritten is written into the page in the memory cell array that corresponds to the page address of a copy destination.

Abstract: A method of programming a memory cell is described. First, a first programming operation is performed to inject electrons into a nitride layer adjacent to a side of a drain. The first programming operation includes applying a first gate voltage to a gate, applying a first drain voltage to the drain, applying a first source voltage to a source, and applying a first substrate, voltage to a substrate. Then, a second programming operation is performed to inject the electrons into the nitride layer adjacent to a side of the source. The second programming operation includes applying a second gate voltage to the gate, applying a second drain voltage to the drain, applying a second source voltage to the source, and applying a second substrate voltage to the substrate. The second gate voltage is less than the first gate voltage.

Abstract: A method of manufacturing structures in a workpiece includes: providing a portion of a cover layer on a predetermined section of the workpiece, providing a resist layer over the workpiece and the cover layer, and patterning resist structures in the resist layer. The workpiece is patterned using the patterned resist layer and the cover layer as an etching mask. Another method of manufacturing structures in a workpiece includes: providing a resist layer over the workpiece, and patterning resist structures in the resist layer. The workpiece is patterned using the patterned resist layer as an etching mask, thereby obtaining workpiece structures. The workpiece structures are removed from a predetermined section of the workpiece. Thereafter, a pitch fragmentation process is carried out.

Abstract: A flash memory system capable of improving an access performance and an access method thereof. The system includes: a flash memory device including a plurality of storage regions; a contents memory storing setting information corresponding to the plurality of storage regions, respectively; and a processing unit setting operation conditions of the flash memory device by referring to the setting information during an access operation for the flash memory device.