Patents Issued in August 7, 2008
  • Publication number: 20080185551
    Abstract: The invention relates to a ball poppet valve having a valve body, a cylindrical valve bore disposed in the valve body, a ball poppet for closing the valve bore and a movable control stem intruding into the valve bore. The control stem acts on the ball poppet, and the control stem has a diameter (d) that at least approximately becomes larger and larger in the direction towards the ball poppet.
    Type: Application
    Filed: February 6, 2008
    Publication date: August 7, 2008
    Inventors: Florian Schulz, Gerd Strobel
  • Publication number: 20080185552
    Abstract: A device in a valve (1) comprises a valve housing (2) with at least a first (3) and a second (4) fluid port. A closure element (5) is arranged in the valve housing (2), said closure element (5) having a sealing portion (15) and comprising a diaphragm (30). The sealing portion (15) is movable along an axis of the closure element (5) by said diaphragm (30) between an open position and a closed position of at least one of the fluid ports of the valve housing. The closure element (5) together with the valve housing (2) forms a flow passage (11) in the valve housing (2) which communicates with said fluid ports when the sealing portion (15) leaves said closed position. A second sealing portion (14) of the closure element, which is an enclosing portion spaced from said axis, is arranged in contact with a support portion (25) of the valve housing (2).
    Type: Application
    Filed: February 1, 2008
    Publication date: August 7, 2008
    Inventors: Lennart Myhrberg, Hakan Samuelsson, Bertil Wejrot
  • Publication number: 20080185553
    Abstract: Use of aqueous dispersions of water-soluble and/or water-swellable anionic polymers and water-soluble neutralizing agents as an additive to aqueous extinguishing agents, and method for fighting fires with aqueous extinguishing agents, an aqueous dispersion of water-soluble and/or water-swellable anionic polymers and at least one water-soluble neutralizing agent being mixed with water so that the mixture has a polymer content of not more than 5% by weight and a pH of at least 5.5.
    Type: Application
    Filed: May 17, 2006
    Publication date: August 7, 2008
    Applicant: BASF AKTIENGESELLSCHAFT
    Inventors: Antje Ziemer, Pulakesh Mukherjee
  • Publication number: 20080185554
    Abstract: Magnetizable particles treated with a silane precursor comprising a hydrophobic group.
    Type: Application
    Filed: January 9, 2008
    Publication date: August 7, 2008
    Applicant: GM GLOBAL TECHNOLOGY OPERATIONS, INC.
    Inventors: John C. Ulicny, Tao Xie, Mark A. Golden, Andrew M. Mance, Keith S. Snavely
  • Publication number: 20080185555
    Abstract: Acene-based compounds that can be used to prepare n-type semiconductor materials are provided with processes for preparing the same. Composites and electronic devices including n-type semiconductor materials prepared from these compounds also are provided.
    Type: Application
    Filed: November 19, 2007
    Publication date: August 7, 2008
    Inventors: Antonio Facchetti, Tobin J. Marks, Zhiming M. Wang
  • Publication number: 20080185556
    Abstract: Provided is an oxygen generating composition comprising a metal powder fuel, a transition metal oxide catalyst, a reaction moderator, a binder, an additive, and an oxygen source. The additives are feldspar or anhydrous aluminum silicate, or both. The oxygen generating composition can be used to generate oxygen on thermal decomposition. The oxygen generating composition is suitable for incorporation into oxygen generating candles. Oxygen generating candles of the present invention have the advantages of lower chlorine concentration, better reaction rate control, and lesser sensitivity to temperature effects on oxygen generation when compared with conventional oxygen generating candles. Additionally, oxygen generating candles comprising the compositions of the present invention can result in candles that do not contain barium compounds, and are non-hazardous, stable to moisture, CO2, and to air, and are suitable for either wet or dry processing methods.
    Type: Application
    Filed: January 28, 2008
    Publication date: August 7, 2008
    Inventor: Matthew J. Noble
  • Publication number: 20080185557
    Abstract: Disclosed are photoluminescent formulations, comprising an effective amount of photoluminescent phosphorescent materials, which exhibit high luminous intensity and persistence. Also disclosed are photoluminescent objects formed by applying at least one photoluminescent layer, formed from photoluminescent formulations, to preformed articles. Further disclosed are methods for creating photoluminescent objects.
    Type: Application
    Filed: December 20, 2005
    Publication date: August 7, 2008
    Inventors: Satish Agrawal, Edward Kingsley
  • Publication number: 20080185558
    Abstract: A Composition comprises a thermally crosslinked reaction product of a polyester and a carboxy-reactive material. Methods for the manufacture of the composition and articles derived from the composition are also disclosed.
    Type: Application
    Filed: February 5, 2007
    Publication date: August 7, 2008
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Christopher Luke Hein, Ganesh Kannan, Sreepadaraj Karanam, Claire Qing Yu
  • Publication number: 20080185559
    Abstract: An anisotropic conductive film (ACF) composition includes a thermoplastic resin having a weight average molecular weight of about 150,000 to about 600,000, a thermosetting curing agent having a weight average molecular weight of about 100 to about 10,000, the thermosetting curing agent including an acrylate functional group or a methacrylate functional group, an organic peroxide, a silane coupling agent, and conductive particles.
    Type: Application
    Filed: December 31, 2007
    Publication date: August 7, 2008
    Inventors: Kang Bae Yoon, Kyoung Soo Park, Cheon Seok Lee
  • Publication number: 20080185560
    Abstract: Alloyed nanophenes comprising carbon, boron, and a Group V element other than nitrogen are provided. The alloyed nanophenes are useful, for example, as miniature electronic components, such as wires, coils, schottky barriers, diodes, inductors, memory elements, and other circuit devices and elements.
    Type: Application
    Filed: December 13, 2006
    Publication date: August 7, 2008
    Applicant: E. I. DUPONT DE NEMOURS AND COMPANY
    Inventor: DAVID HERBERT ROACH
  • Publication number: 20080185561
    Abstract: Resistor compositions are disclosed, made from polymer thick film resistor formulations comprising a polyimide component, a sterically hindered hydrophobic epoxy component and a solvent component having a Hanson polar solubility parameter between 2.1 and 3.0 and having a normal boiling point between 210 and 260° C. The weight ratio of polyimide component (“A”) to epoxy component (“B”) is A:B, where A is between and including 1 to 15 and where B is 1.
    Type: Application
    Filed: November 19, 2007
    Publication date: August 7, 2008
    Inventor: John D. Summers
  • Publication number: 20080185562
    Abstract: An embodiment of an oxalate ester chemiluminescent light system comprises two components. One component is an oxalate ester, containing at least 0.01M oxalate ester and 0.001M fluorescer in a suitable solvent; the other component contains 0.01M to 3M of hydrogen peroxide in a polyethylene glycol mixed solvent, where the amount of polyethylene glycol in the mixture is from 1%-99% and the balance of the mixed solvent may be an ester. In comparison to chemiluminescent light systems comprising tertiary alcohols, the light emitting system with the polyethylene glycol has lower toxicity, higher flash point and lower vapor pressure; the energy of the chemical light produced is about 15% higher; and storage stability is better.
    Type: Application
    Filed: February 1, 2008
    Publication date: August 7, 2008
    Applicant: Tianjin Dragon Chemiluminescent Tubes Co., Ltd.
    Inventors: Yu Chen, Ning On
  • Publication number: 20080185563
    Abstract: A retractable load support system for effectively lifting a load in a controlled manner. The retractable load support system includes a frame, a gerotor attached to a main shaft within said frame, a first spool attached to the gerotor, a biasing device connected to the first spool applying a biasing force to the first spool and an elongated member attached to the first spool. The main shaft is rotatably supported within the frame by a one way bearing allowing the main shaft to rotate when the elongated member is drawn downwardly to reduce the resistance of the gerotor. The main shaft is supported substantially stationary within the frame by the one way bearing preventing the main shaft from rotating when the elongated member is drawn upwardly onto the first spool thereby lifting the load in a controlled manner.
    Type: Application
    Filed: April 9, 2008
    Publication date: August 7, 2008
    Inventor: Raymond Dueck
  • Publication number: 20080185564
    Abstract: A portable hoist assembly having a housing. The housing has a recoil spring secured thereto wherein the recoil spring is secured to a cable spool such that constant tension is provided on the cable spool. The cable spool contains a cable that is secured thereto and has a hook member secured at a first end. An actuating member having a self contained power source and connected to the cable is thus operable to feed and retract the cable.
    Type: Application
    Filed: February 1, 2008
    Publication date: August 7, 2008
    Inventor: Randy A. LaFreniere
  • Publication number: 20080185565
    Abstract: A fence and an installation method for a fence or other laterally extending structure, the installation method comprising in one embodiment: obtaining a trench in ground, the trench extending laterally with a top of the trench having a first opening width, and having a first bottom surface; obtaining a hole in the first bottom surface of the trench with an approximate diameter that is at least fifty percent smaller than the first opening width; installing a support post in the hole to extend up above the top of the trench; disposing laterally extending panels at substantially the first bottom surface of the trench and attaching them to approximately opposing ends of a diameter of the post to thereby create a void volume between the panels at least on one side of the post; installing at least one retainer connecting to the panels across the void volume; and filling the void volume with stones or other fill material.
    Type: Application
    Filed: February 6, 2007
    Publication date: August 7, 2008
    Inventors: Robert W. Major, Gregory Maury Shepherd
  • Publication number: 20080185566
    Abstract: A safety barrier for an inside of a house for partitioning off a portion of the house. The safety barrier includes a number of individual barrier sections where two adjacent barrier sections are engaged via a connector. The connector has an upper connection, a lower connection, and an elongate central member interconnecting the upper and lower connections. Each of the connections has a pair of relatively swingable arms. Each of the arms engages a barrier section. A threaded member draws the upper and lower connections closed simultaneously to fix the arms relative to each other and to thus fix the barrier sections relative to each other. The arms, prior to being fixed, are swingable relative to each other from about zero degrees to about 270 degrees such that a zig-zag, linear, or circular barriers can be made. A gate or door that can be opened and closed for access to the partitioned section of the house is engaged in one of the barrier sections.
    Type: Application
    Filed: February 23, 2007
    Publication date: August 7, 2008
    Inventor: Mark A. Flannery
  • Publication number: 20080185567
    Abstract: Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.
    Type: Application
    Filed: February 5, 2007
    Publication date: August 7, 2008
    Inventors: Nitin Kumar, Chi-I Lang, Tony Chiang, Zhi-wen Sun, Jihhong Tong
  • Publication number: 20080185568
    Abstract: Example embodiments provide a nonvolatile memory device using resistive elements. The nonvolatile memory device may include a semiconductor substrate, a plurality of variable resistance patterns on the semiconductor substrate, and a plurality of heat sink patterns that are level with the variable resistance patterns and coupled to a ground voltage.
    Type: Application
    Filed: January 31, 2008
    Publication date: August 7, 2008
    Inventors: Yong-wook Kwon, Chul-soon Kwon, Young-cheon Jeong
  • Publication number: 20080185569
    Abstract: A phase change memory includes a word line disposed on a semiconductor substrate and a cell diode that physically contacts the semiconductor substrate and a corresponding word line. The word line may be formed of a metal, such as tungsten. Accordingly, no metal contact is included and the word line formed of metal is in contact with the cell diode.
    Type: Application
    Filed: January 31, 2008
    Publication date: August 7, 2008
    Inventors: Myung-jin Park, Young-tae Kim, Keun-ho Lee
  • Publication number: 20080185570
    Abstract: Methods for fabricating highly compact PCM memory devices are described herein. The methods may include forming a bipolar junction transistor (BJT) structure on a substrate including creating a base of the BJT structure on the substrate and creating an emitter of the BJT structure on top of the base opposite of the substrate. A heating element may then be constructed on the emitter of the BJT structure, wherein the heating element includes a material to generate heat when provided with an electrical current from the emitter. A phase change material (PCM) cell may then be built on the heating element opposite of the BJT structure.
    Type: Application
    Filed: February 1, 2008
    Publication date: August 7, 2008
    Inventors: Albert Wu, Chien-Chuan Wei
  • Publication number: 20080185571
    Abstract: An integrated circuit including a memory cell includes a vertical bipolar select device including a base and an emitter. The memory cell includes a resistive memory element coupled to the emitter and a buried metallized word line contacting the base.
    Type: Application
    Filed: February 1, 2007
    Publication date: August 7, 2008
    Inventors: Thomas Happ, Jan Boris Philipp
  • Publication number: 20080185572
    Abstract: Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.
    Type: Application
    Filed: February 5, 2007
    Publication date: August 7, 2008
    Inventors: Tony Chiang, Chi-I Lang, Zhi-wen Sun, Jinhong Tong, Nitin Kumar
  • Publication number: 20080185573
    Abstract: Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.
    Type: Application
    Filed: February 5, 2007
    Publication date: August 7, 2008
    Inventors: Zhi-wen Sun, Nitin Kumar, Jinhong Tong, Chi-l Lang, Tony Chiang
  • Publication number: 20080185574
    Abstract: A method of forming a non-volatile resistance variable device includes forming a first conductive electrode material on a substrate. A metal doped chalcogenide comprising material is formed over the first conductive electrode material. Such comprises the metal and AxBy, where “B” is selected from S, Se and Te and mixtures thereof, and where “A” comprises at least one element which is selected from Group 13, Group 14, Group 15, or Group 17 of the periodic table. In one aspect, the chalcogenide comprising material is exposed to and HNO3 solution. In one aspect the outer surface is oxidized effective to form a layer comprising at least one of an oxide of “A” or an oxide of “B”. In one aspect, a passivating material is formed over the metal doped chalcogenide comprising material. A second conductive electrode material is deposited, and a second conductive electrode material of the device is ultimately formed therefrom.
    Type: Application
    Filed: January 24, 2008
    Publication date: August 7, 2008
    Inventors: Kristy A. Campbell, Terry L. Gilton, John T. Moore, Jiutao Li
  • Publication number: 20080185575
    Abstract: A manufacture method of a multilevel phase-change memory and operating method thereof are provided. The method includes providing a substrate, forming a bottom electrode on the substrate, forming a first heating layer on top of the bottom electrode, forming a second heating layer on top of the first heating layer, forming a first phase-change layer and a second phase-change layer respectively on the first heating layer and the second heating layer, and forming a first top electrode and a second electrode respectively on the first phase-change layer and the second phase-change layer. Hence, the bottom electrode, the first heating layer and the first phase-change layer constitute an electrical current path, the bottom electrode, the first heating layer, the second heating layer and the second phase-change layer constitute another electrical current path, and the resistances of the two electrical current path are different, thereby increasing the memory density.
    Type: Application
    Filed: April 3, 2008
    Publication date: August 7, 2008
    Inventor: Chih-Wen HSIUNG
  • Publication number: 20080185576
    Abstract: This invention concerns quantum error correction, that is the correction of errors in the transport and processing of qubits, by use of logical qubits made up of a plurality of physical qubits. The process takes place on a spatial array of physical qubit sites arranged with a quasi-2-dimensional topology having a first line of physical qubit sites and second line of physical qubit sites, where the first and second lines are arranged in parallel, with the sites of the first line in registration with corresponding sites in the second line. Between the first and second lines of physical qubit sites are a plurality of logic function gates, each comprised of a first physical qubit gate site associated with a first physical qubit site in the first line, and a second physical qubit gate site associated with the physical qubit site in the second line that corresponds to the first physical qubit site.
    Type: Application
    Filed: March 1, 2007
    Publication date: August 7, 2008
    Inventors: Lloyd Hollenberg, Ashley Stephens, Andrew Greentree, Austin Fowler, Cameron Wellard
  • Publication number: 20080185577
    Abstract: Diimide-based semiconductor materials are provided with processes for preparing the same. Composites and electronic devices including the diimide-based semiconductor materials also are provided.
    Type: Application
    Filed: November 19, 2007
    Publication date: August 7, 2008
    Inventors: Antonio Facchetti, Tobin J. Marks, He Yan
  • Publication number: 20080185578
    Abstract: A memory device is provided, which includes a first conductive layer, a second conductive layer, and a memory layer interposed between the first conductive layer and the second conductive layer. The memory layer includes a first portion and a second portion, each of which includes at least a nanoparticle. The nanoparticle includes a conductive material coated with an organic film. The first portion is in contact with the first conductive layer and the second conductive layer, and a side surface of the first portion is surrounded by the second portion.
    Type: Application
    Filed: January 23, 2008
    Publication date: August 7, 2008
    Inventors: Kensuke Yoshizumi, Noriko Harima
  • Publication number: 20080185579
    Abstract: A preferred embodiment microcavity plasma device array of the invention includes a plurality of first metal circumferential metal electrodes that surround microcavities in the device. The first circumferential electrodes are buried in a metal oxide layer and surround the microcavities in a plane transverse to the microcavity axis, while being protected from plasma in the microcavities by the metal oxide. In embodiments of the invention, the circumferential electrodes can be connected in patterns. A second electrode(s) is arranged so as to be isolated from said first electrodes by said first metal oxide layer. In some embodiments, the second electrode(s) is in a second layer, and in other embodiments the second electrode(s) is also within the first metal oxide layer. A containing layer, e.g., a thin layer of glass, quartz, or plastic, seals the discharge medium (plasma) into the microcavities. In a preferred method of formation embodiment, a metal foil or film is obtained or formed with micro-holes.
    Type: Application
    Filed: July 24, 2007
    Publication date: August 7, 2008
    Inventors: J. Gary Eden, Sung-Jin Park, Kwang-Soo Kim
  • Publication number: 20080185580
    Abstract: A ZnO crystal growth method has the steps of (a) preparing a substrate having a surface capable of growing ZnO crystal exposing a Zn polarity plane; (b) supplying Zn and O above the surface of the substrate by alternately repeating a Zn-rich condition period and an O-rich condition period; and (c) supplying conductivity type determining impurities above the surface of the substrate while Zn and O are supplied at the step (b).
    Type: Application
    Filed: February 8, 2008
    Publication date: August 7, 2008
    Inventors: Hiroyuki KATO, Michihiro Sano
  • Publication number: 20080185581
    Abstract: According to one exemplary embodiment, a silicon-on-insulator (SOI) transistor test structure includes a gate situated over a semiconductor body and a doped halo under the gate. The SOI transistor test structure further includes at least two semiconductor body contacts situated on opposing sides of the doped halo, where one or more of the at least two semiconductor body contacts forms a direct electrical contact with the doped halo, thereby increasing current flow to the doped halo to facilitate measuring body-effect in the SOI transistor test structure.
    Type: Application
    Filed: October 5, 2006
    Publication date: August 7, 2008
    Inventors: Qiang Chen, Jung-Suk Goo
  • Publication number: 20080185582
    Abstract: Improved techniques to produce integrated circuit products are disclosed. The improved techniques permit smaller and less costly production of integrated circuit products. One aspect of the invention concerns covering test contacts (e.g., test pins) provided with the integrated circuit products using printed ink. Once covered with the ink, the test contacts are no longer electrically exposed. Hence, the integrated circuit products are not susceptible to accidental access or electrostatic discharge. Moreover, the integrated circuit products can be efficiently produced in a small form factor without any need for additional packaging or labels to electrically isolate the test contacts.
    Type: Application
    Filed: October 20, 2006
    Publication date: August 7, 2008
    Inventors: Warren Middlekauff, Robert Miller, Charlie Centofante
  • Publication number: 20080185583
    Abstract: According to the present invention, there is disclosed a thermal detection device and method of using the device for characterizing and monitoring the dependence of pattern density on thermal absorption of a semiconductor. One or more of the devices can be disposed on a die of a test wafer. The thermal detection device comprises a silicon substrate having a test structure located substantially in the center of the silicon substrate. Frame shaped structures of polysilicon, silicon and oxide, in various configurations, form a collocated arrangement on the silicon substrate. The test wafer is subjected to a rapid thermal process and the resistance of the at least one testing structure is measured and the measured resistance of the at least one test structure is tabulated to a thermal absorption value of the at least one die.
    Type: Application
    Filed: February 7, 2007
    Publication date: August 7, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: ISHTIAQ AHSAN, OLEG GLUSCHENKOV
  • Publication number: 20080185584
    Abstract: Semiconductor device test structures and methods are disclosed. In a preferred embodiment, a test structure includes a feed line disposed in a first conductive material layer, and a stress line disposed in the first conductive material layer proximate the feed line yet spaced apart from the feed line. The stress line is coupled to the feed line by a conductive feature disposed in at least one second conductive material layer proximate the first conductive material layer.
    Type: Application
    Filed: February 6, 2007
    Publication date: August 7, 2008
    Inventors: Wolfgang Walter, Klaus Koller
  • Publication number: 20080185585
    Abstract: A microelectronic device may include a substrate, a plurality of components on the substrate, an insulating layer adjacent the substrate, and a plurality of metallic interconnection levels within the insulating layer and for the plurality of components. The plurality of metallic interconnection levels may include at least one given metallic level including a plurality of conductive lines of a first metallic material, and at least one other metallic level adjacent the at least one given metallic level. The at least one other metallic level may include at least one conductive zone of the first metallic material and coupled to at least one of the plurality of conductive lines of the at least one given metallic level, and at least one other conductive zone of a second metallic material and coupled to at least one other of the plurality of conductive lines of the at least one given metallic level.
    Type: Application
    Filed: December 20, 2007
    Publication date: August 7, 2008
    Applicant: STMicroelectronics SA
    Inventor: Francois Roy
  • Publication number: 20080185586
    Abstract: A multiple integrated circuit chip structure provides interchip communication between integrated circuit chips of the structure with no ESD protection circuits and no input/output circuitry. The interchip communication is between internal circuits of the integrated circuit chips. The multiple integrated circuit chip structure has an interchip interface circuit to selectively connect internal circuits of the integrated circuits to test interface circuits having ESD protection circuits and input/output circuitry designed to communicate with external test systems during test and burn-in procedures. The multiple interconnected integrated circuit chip structure has a first integrated circuit chip mounted to one or more second integrated circuit chips to physically and electrically connect the integrated circuit chips to one another.
    Type: Application
    Filed: April 7, 2008
    Publication date: August 7, 2008
    Applicant: MEGICA CORPORATION
    Inventor: Mou-Shiung Lin
  • Publication number: 20080185587
    Abstract: A display panel and a manufacturing method in which the display panel includes an alkali-containing glass substrate having a surface waviness of less about 0.06 ?m, a gate electrode formed the substrate, a gate insulating layer formed on the gate electrode, a semiconductor formed on the gate insulating layer, a source electrode and a drain electrode contacting the semiconductor, and a pixel electrode electrically connected to the drain electrode.
    Type: Application
    Filed: October 30, 2007
    Publication date: August 7, 2008
    Inventors: Sang-Woo Whangbo, Jun-Hyung Souk, Yong-Suk Jin, Jin-Ho Ju, Min Kang, Myo-Kyong Joo
  • Publication number: 20080185588
    Abstract: A flexible display substrate includes: a thin film transistor on the flexible substrate, the thin film transistor including a gate electrode, a gate insulating layer insulating the gate electrode, a channel layer on the gate insulating layer, a source electrode connected with the channel layer, and a drain electrode connected with the channel layer; a first stress absorbing layer below the thin film transistor; a first protection layer on the first stress absorbing layer; a second stress absorbing layer on the thin film transistor; a second protection layer on the second stress absorbing layer; and a pixel electrode on the second protection layer, the pixel electrode being connected with the drain electrode.
    Type: Application
    Filed: November 2, 2007
    Publication date: August 7, 2008
    Inventors: Yong In Park, Seung Han Paek, Sang Soo Kim
  • Publication number: 20080185589
    Abstract: A display substrate includes a thin-film transistor (TFT) layer, a color filter layer and a pixel electrode formed on a substrate. The TFT layer includes a gate line, a data line electrically insulated from the gate line and extending in a direction different from the gate line, a TFT electrically connected to the gate line and the data line, and a storage electrode formed from the same layer as the gate line in each pixel. The color filter layer includes a storage hole extending to a portion of the TFT layer corresponding to the storage electrode. The storage hole has a horizontal cross-sectional area greater than the storage electrode, wherein the horizontal cross-sectional area is measured in a plane parallel to the substrate. The pixel electrode is formed on the color filter layer and in the storage hole to form a storage capacitor with the storage electrode.
    Type: Application
    Filed: February 6, 2008
    Publication date: August 7, 2008
    Inventors: Kyoung-Ju Shin, Jang-Soo Kim, Chong-Chul Chai
  • Publication number: 20080185590
    Abstract: A manufacturing method of a thin film transistor (TFT) includes forming a gate electrode including a metal that can be combined with silicon to form silicide on a substrate and forming a gate insulation layer by supplying a gas which includes silicon to the gate electrode at a temperature below about 280° C. The method further includes forming a semiconductor on the gate insulation layer, forming a data line and a drain electrode on the semiconductor and forming a pixel electrode connected to the drain electrode.
    Type: Application
    Filed: October 31, 2007
    Publication date: August 7, 2008
    Inventors: Byoung-June Kim, Jae-Ho Choi, Chang-Oh Jeong, Sung-Hoon Yang, Je-Hun Lee, Do-Hyun Kim, Hwa-Yeul Oh, Yong-Mo Choi
  • Publication number: 20080185591
    Abstract: Provided is a thin film device and an associated method of making a thin film device. For example, a thin film transistor with nano-gaps in the gate electrode. The method involves providing a substrate. Upon the substrate are then provided a plurality of parallel spaced electrically conductive strips. A plurality of thin film device layers are then deposited upon the conductive strips. A 3D structure is provided upon the plurality of thin film device layers, the structure having a plurality of different heights. The 3D structure and the plurality of thin film device layers are then etched to define a thin film device, such as for example a thin film transistor that is disposed above at least a portion of the conductive strips.
    Type: Application
    Filed: January 24, 2008
    Publication date: August 7, 2008
    Inventors: Ping Mei, Albert Jeans, Carl Taussig
  • Publication number: 20080185592
    Abstract: A pair of semiconductor structures and a method for fabricating a semiconductor structure each utilize a semiconductor substrate having a first crystallographic orientation, and a dielectric layer located thereupon. The method provides for epitaxially growing a semiconductor layer on the semiconductor substrate to encapsulate the dielectric layer. The method also provides for patterning the semiconductor layer to yield a semiconductor structure that comprises a bulk semiconductor structure and a semiconductor-on-insulator structure, or alternatively a patterned semiconductor layer that straddles the dielectric layer and contacts the semiconductor substrate.
    Type: Application
    Filed: January 9, 2006
    Publication date: August 7, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Byeong Y. Kim, Xiaomeng Chen, Woo-Hyeong Lee, Huilong Zhu
  • Publication number: 20080185593
    Abstract: A method of manufacturing a vertical power MOS transistor on a wide band gap semiconductor substrate having a wide band gap superficial semiconductor layer, including the steps of forming a screening structure on the superficial semiconductor layer that leaves a plurality of areas of the superficial semiconductor layer exposed, carrying out at least a first ion implantation of a first type of dopant in the superficial semiconductor layer for forming at least one deep implanted region, carrying out at least a second ion implantation of the first type of dopant in the superficial semiconductor layer for forming at least one implanted body region of the MOS transistor aligned with the deep implanted region, carrying out at least one ion implantation of a second type of dopant in the superficial semiconductor layer for forming at least an implanted source region of the MOS transistor inside the at least one implanted body region, and a low budget activation thermal process of the first and second dopant types sui
    Type: Application
    Filed: January 8, 2008
    Publication date: August 7, 2008
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Mario Giuseppe Saggio, Ferruccio Frisina
  • Publication number: 20080185594
    Abstract: A method manufactures a vertical power MOS transistor on a semiconductor substrate comprising a first superficial semiconductor layer of a first conductivity type, comprising: forming trench regions in the first semiconductor layer, filling in said trench regions with a second semiconductor layer of a second conductivity type, to form semiconductor portions of the second conductivity type contained in the first semiconductor layer, carrying out an ion implantation of a first dopant type in the semiconductor portions for forming respective implanted body regions of said second conductivity type, carrying out an ion implantation of a second dopant type in one of the implanted body regions for forming an implanted source region of the first conductivity type inside one of the body regions, carrying out an activation thermal process of the first and second dopant types with low thermal budget suitable to complete said formation of the body and source regions.
    Type: Application
    Filed: January 8, 2008
    Publication date: August 7, 2008
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Ferruccio Frisina, Mario Giuseppe Saggio
  • Publication number: 20080185595
    Abstract: There is provided a light emitting device that can reduce the size of a light emitting device module by using a more simplified light emitting device that directly uses an alternating current source, prevent a decrease in luminous efficiency that is caused due to the use of a separate driving device, solve a problem with an ohmic contact of a p-type electrode, reduce the number of electrodes, and secure a larger area of light emission.
    Type: Application
    Filed: February 6, 2008
    Publication date: August 7, 2008
    Inventors: Won Ha Moon, Chang Hwan Choi, Hyun Jun Kim
  • Publication number: 20080185596
    Abstract: Embodiments of a system for displaying images include a light emitting device with a plurality of photo sensors. Each photo sensor includes a PIN diode composed of an N+ doped semiconductor region, a P+ doped semiconductor region, and an intrinsic semiconductor region formed therebetween. An insulated control gate overlaps the intrinsic semiconductor region and is operative to provide the PIN diode with a controllable electric characteristic with respect to a saturation photo current at a saturation voltage.
    Type: Application
    Filed: February 2, 2007
    Publication date: August 7, 2008
    Applicant: TPO DISPLAYS CORP.
    Inventors: Chang-Ho Tseng, Yu-Chun Shih, Hsuan-Chih Huang
  • Publication number: 20080185597
    Abstract: A light-emitting module includes a base, a connecting unit disposed on the base, a light-emitting unit disposed on the base, and a drive unit electrically coupled to and bridging the connecting unit and the light-emitting unit for driving the light-emitting unit. The base includes a plurality of first bonding pads formed thereon. The connecting unit is electrically coupled to the first bonding pads, and the light-emitting unit is electrically coupled to the first bonding pads via the drive unit and the connecting unit. The connecting unit includes a plurality of connectors aligned in a first direction of the base, and the light-emitting unit includes a plurality of light-emitting elements aligned in the first direction and respectively spaced apart from and aligned with the connectors in a second direction perpendicular to the first direction.
    Type: Application
    Filed: February 6, 2007
    Publication date: August 7, 2008
    Inventor: Ming-Che WU
  • Publication number: 20080185598
    Abstract: A light emitting device includes: a heat dissipating seat of a metallic material; a chip-mounting base of a semiconductor material attached to the heat dissipating seat; an insulator layer formed on the chip-mounting base; a bonding layer of a metal formed on the insulator layer; and a light emitting chip bonded to the bonding layer.
    Type: Application
    Filed: February 1, 2008
    Publication date: August 7, 2008
    Inventors: Mei-Yuh LUO, Kuei-Fang CHEN, Han-Yu CHANG
  • Publication number: 20080185599
    Abstract: In order to provide a light emitting device which consistently emits light at the time of continuous driving in addition to obtain light emission having a high color purity in each of red, green and blue, a light emitting element according to the present invention, in which an organic compound film comprising a hole transporting material, an electron transporting material, a first impurity (first doping material), and a second impurity (second doping material) is provided between an anode and a cathode, is characterized in that the organic compound film is laminated with a first mixed region comprising the hole transporting material and the first impurity, a hole transporting region comprising the hole transporting material, a second mixed region comprising the electron transporting material and the second impurity, and an electron transporting region comprising the electron transporting material in order from the side of the anode.
    Type: Application
    Filed: January 8, 2008
    Publication date: August 7, 2008
    Inventors: Shuhei Yoshitomi, Junichiro Sakata, Masahiro Takahashi
  • Publication number: 20080185600
    Abstract: A light emitting semiconductor device including a light emitting diode having a cascading phosphor is improved by the particles of phosphor being coated with a moisture barrier layer and a buffer layer. Either the buffer layer overlies the moisture barrier layer or the moisture barrier layer overlies the buffer layer. In the latter case, the particles can further include a buffer layer over the moisture barrier layer. Preferred materials for the buffer layer are silica or alumina, which can include other oxides in the layer.
    Type: Application
    Filed: February 2, 2007
    Publication date: August 7, 2008
    Applicant: World Properties, Inc.
    Inventor: Alan C. Thomas