Abstract: A process includes the steps of: 1) heating a mold at a temperature ranging from 100° C. to 200° C.; 2) feeding a silicone encapsulant composition including a mold release agent, where the composition has a viscosity ranging from 100 cps to 3,000 cps at operating temperatures of the process, to an assembly for preventing the silicone encapsulant composition from flowing backward out of the assembly; 3) injecting the silicone encapsulant composition from the assembly into a mold having a horizontal orientation and having a mold cavity through a gate, where the mold cavity has a top and a bottom, a vent is located at the top of the mold cavity, the vent comprises a channel 0.1 mm to 1 mm wide by 0.0001 mm to 0.

Abstract: The present invention relates to a method for preparing a white light emitting diode (LED) using phosphors, especially to a white light emitting diode prepared by applying a tri-color phosphor material mixture of red, blue and green on a UV LED chip made of a packaging substrate, where white light is obtained by transmitting light through the tri-color phosphor mixture since the UV LED chip emits purple light. In particular, the present invention relates to a white light emitting diode prepared by laminating green and red or yellow and red phosphor materials on a blue LED chip, where white light is obtained as light is transmitted and absorbed by the phosphors. The method in accordance with the present invention is advantageous in that a white light emitting diode having superior photoluminescence efficiency can be provided using a single chip.

Abstract: An optical device is equipped with a light receiving region 16a and a peripheral circuit region 22 located around the light receiving region 16a on a major surface of an light receiving element 11a; electrodes for external connection 15 electrically connected to the peripheral circuit region 22 formed on a back surface opposite to the major surface of the light receiving element 11a; a transparent member 12 covering the light receiving region 16a adhered on the major surface of the light receiving element 11a with a light-transmitting adhesive 13; and a molding resin 14 for coating side surfaces of the transparent member 12 and the major surface of the light receiving element 11a excluding the region covered with the transparent member 12.

Abstract: Disclosed is a light emitting device employing nanowire phosphors. The light emitting device comprises a light emitting diode for emitting light having a first wavelength with a main peak in an ultraviolet, blue or green wavelength range; and nanowire phosphors for converting at least a portion of light having the first wavelength emitted from the light emitting diode into light with a second wavelength longer than the first wavelength. Accordingly, since the nanowire phosphors are employed, it is possible to reduce manufacturing costs of the light emitting device and to reduce light loss due to non-radiative recombination.

Abstract: An LED includes a circuit board (1), a light emitter (3) mounted on the circuit board (1), and a reflector (4) mounted on the circuit board (1), the light emitter (3) including an LED element mounted on the circuit board (1) and a light-transmitting resin (2) to seal the LED element. The reflector (4) is configured to surround the light emitter (3) and includes an opening (5) which passes through an upper surface and a lower surface is provided at a central position to allow insertion of the light emitter (3), and an inclined inner surface in the opening (6) configured to be upwardly broadened. A reflection film (7) is provided on the inclined inner surface (6) of the opening in the reflector. A outer peripheral edge is a non-reflection film constituted area (8) and, simultaneously, a terminal position identification mark (10) adjacent to the non-reflection film constituted area (8) are provided.

Abstract: The present invention provides a light emitting element capable or realizing at least one of, preferably, most of lower resistance, higher output, higher power efficiency (1 m/W), higher mass productivity and lower cost of the element using a light transmissive electrode for an electrode arranged exterior to the light emitting structure.

Abstract: A light emitting diode (LED) module which includes a light emitting diode which includes a light emitting chip, a first electrode and a second electrode, the first and second electrodes being electrically connected to the light emitting chip. The light-emitting diode is supported on a printed circuit board. The printed circuit board includes a base substrate of an insulating resin material, a first extension electrode that is formed on the base substrate and is connected to the first electrode, and a second extension electrode that is formed on the base substrate and is connected to the second electrode.

Abstract: Contacting materials and methods for forming ohmic contact to the N-face polarity surfaces of Group-III nitride based semiconductor materials, and devices fabricated using the methods. One embodiment of a light emitting diode (LED) a Group-III nitride active epitaxial region between two Group-III nitride oppositely doped epitaxial layers. The oppositely doped layers have alternating face polarities from the Group III and nitrogen (N) materials, and at least one of the oppositely doped layers has an exposed surface with an N-face polarity. A first contact layer is included on and forms an ohmic contact with the exposed N-face polarity surface. In one embodiment, the first contact layer comprises indium nitride.

Abstract: An object of the invention is to prevent migration of silver contained in an electrode of a Group III nitride-based compound semiconductor light-emitting device. An n-type AlxGayIn1-x-yN layer, a light-emitting layer, and a p-type AlxGayIn1-x-yN layer are formed on a dielectric substrate such as a sapphire substrate. After formation of these layers, the n-type AlxGayIn1-x-yN layer is exposed through etching or a similar technique, and an n-electrode is formed on the exposed area. A positive electrode is formed on the p-type layer. In the positive electrode, an ITO light-transmitting electrode layer, a silver alloy reflecting electrode layer, a diffusion-preventing layer in which a Ti layer and a Pt layer are stacked, and a gold thick-film electrode are sequentially stacked on the p-type layer. The reflecting electrode layer made of a silver alloy contains palladium (Pd) and copper (Cu) as additives and also contains oxygen (O).

Abstract: A resin-sealed semiconductor light receiving element in which a light receiving element mounted on a circuit board is sealed with a transparent resin. A mounting face of the circuit board on which the light receiving element is mounted is sealed with a transparent epoxy resin so that a light receiving surface of the light receiving element is exposed, and at least the light receiving surface of the light receiving element is sealed with a transparent silicone resin.

Abstract: The invention concerns a monocrystalline coating crack-free coating of gallium nitride or mixed gallium nitride and another metal, on a substrate likely to cause extensive stresses in the coating, said substrate being coated with a buffer layer, wherein: at least a monocrystalline layer of a material having a thickness ranging between 100 and 300 nm, preferably between 200 and 250 nm, and whereof crystal lattice parameter is less than the crystal lattice parameter of the gallium nitride or of the mixed gallium nitride with another metal, is inserted in the coating of gallium nitride or mixed gallium nitride with another metal. The invention also concerns the method for preparing said coating. The invention further concerns electronic and optoelectronic devices comprising said coating.

Abstract: A semiconductor device has a Si substrate, a gate insulating film over the Si substrate, a gate electrode over the gate insulating film, a source region and a drain region in the Si substrate, wherein each of the source region and the drain region includes a first Si layer including Ge, an interlayer over the first Si layer, and a second Si layer including Ge over the interlayer, wherein the interlayer is composed of Si or Si including Ge, and a Ge concentration of the interlayer is less than a Ge concentration of the first Si layer and a Ge concentration of the second Si layer.

Abstract: A III-nitride semiconductor device which includes a barrier body between the gate electrode and the gate dielectric thereof.

Abstract: An integrated circuit assembly (ICA) comprises: a digital and/or analog integrated circuit (S1) having a core with input and/or output pins and at least one power supply connection pad (PP) and one ground connection pad (GP) connected to a chosen one of the input and/or output pins and respectively connected to power supply and ground connection zones (MZ1) of a printed circuit board (PCB), and a passive integration substrate (S2) set on top of the digital and/or analog integrated circuit (S1) and comprising i) at least first and second input zones respectively connected to the ground (GP) and power supply (PP) connection pads to, be fed with input ground and supply voltages, ii) input and/or output zones connected to chosen core input and/or output pins, and Ëi) a passive integrated circuit (PIC) connected to the first and second input zones and arranged to feed the substrate input and/or output zones with chosen ground and supply voltages defined from the input ground and supply voltages.

Abstract: Methods and apparatuses are disclosed for biasing the source-side and the drain-side of a nonvolatile memory to add electrons to the charge trapping structure.

Abstract: Semiconductor device-based chemical sensors and methods associated with the same are provided. The sensors include regions that can interact with chemical species being detected. The chemical species may, for example, be a component of a fluid (e.g., gas or liquid). The interaction between the chemical species and a region of the sensor causes a change in a measurable property (e.g., an electrical property) of the device. These changes may be related to the concentration of the chemical species in the medium being characterized.

Abstract: A semiconductor structure includes a semiconductor substrate having a top surface; a gate stack on the semiconductor substrate; and a stressor in the semiconductor substrate and adjacent the gate stack. The stressor comprises at least a first portion with a first top surface lower than the top surface of the semiconductor substrate.

Abstract: The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer.

Abstract: A multicolor CMOS pixel sensor formed in a p-type semiconductor region includes a first detector formed from an n-type region of semiconductor material located near the surface of the p-type region. A first pinned p-type region is formed at the surface of the p-type region over the first detector, and has a surface portion extending past an edge of the pinned p-type region. A second detector is formed from an n-type region located in the p-type semiconductor region below the first detector. A second-detector n-type deep contact plug is in contact with the second detector and extends to the surface of the p-type semiconductor region. A second pinned p-type region is formed at the surface of the p-type semiconductor region over the top of the second-detector n-type deep contact plug. A surface portion of the second-detector deep contact plug extends past an edge of the second pinned p-type region.

Abstract: The present invention relates to the method of manufacturing an image sensor, the method comprising providing a semiconductor substrate, which comprises a pixel array area and a logic area, a plurality of the photodiodes are formed on the semiconductor substrate of the pixel array area, a multilevel interconnect process is processed on the semiconductor substrate, a passivation is doping on the pixel array area and the logic area, removing the passivation on the pixel array area, and a plurality of the color filter arrays are formed on the pixel array area and correspond to the photodiode individually.

Abstract: A complementary metal-oxide semiconductor (CMOS) image sensor comprises a photodiode region generating electrical charges in response to incident light thereon. The CMOS image sensor further comprises a first floating diffusion layer adapted to receive the electrical charges from the photodiode region in response to a global transfer signal and a second floating diffusion region adapted to receive the electrical charges from the first floating diffusion region in response to a pixel selection signal.

Abstract: A CMOS image sensor and a method for fabricating the same are disclosed, in which light that transmits through a microlens is prevented from being beyond a photodiode region to minimize loss of incident light and to improve low illumination characteristics of the CMOS image sensor. The CMOS image sensor includes a semiconductor substrate including a transistor region and a photodiode region, a gate electrode formed on the semiconductor substrate corresponding to the transistor region, an interlayer dielectric layer formed on an entire surface of the semiconductor substrate including the gate electrode, a microlens formed over the interlayer dielectric layer to condense light, and a metal barrier formed in the interlayer dielectric layer to surround a portion of the interlayer dielectric layer corresponding to the photodiode region and to reflect light in the photodiode region that transmits through the microlens but goes beyond the photodiode region.

Abstract: A method for fabricating a ferroelectric memory device, including terminating a surface of the interlayer insulation film and a surface of the contact plug with an OH group; forming a layer containing Si, oxygen and a CH group on the surface of the interlayer insulation film and the contact hole terminated with the OH group by coating a Si compound containing a Si atom and a CH group in a molecule thereof; converting the layer containing Si, oxygen and the CH group to a layer containing nitrogen at a surface thereof, by substituting the CH group in the layer containing Si, oxygen and the CH group at least at a surface part thereof with nitrogen atoms; and forming a layer showing self-orientation on the surface containing nitrogen.

Abstract: Methods of forming a storage capacitor include forming an interlayer insulation layer having an opening there through on a semiconductor substrate, forming a contact plug in the opening, forming a molding oxide layer on the interlayer insulation layer and the contact plug, selectively removing portions of the molding oxide layer to form a recess above the contact plug, forming a titanium layer on a bottom surface and side surfaces of the recess, forming a titanium nitride layer on the titanium layer, and forming a titanium oxide nitride layer on the titanium nitride layer. A storage capacitor includes a semiconductor substrate, an interlayer insulation layer having a contact plug therein on the substrate, and a storage electrode on the contact plug including a titanium silicide layer, a titanium nitride layer on the titanium silicide layer, and a titanium oxide nitride layer on the titanium nitride layer.

Abstract: A two-terminal capacitive circuit element 100 includes a MOS transistor including a source 126 and drain 127 separated by a body region 131, and a gate 105 separated from the body 129 by a gate insulator layer 110, and a bypass capacitor 125. The gate node (port2; 115) is AC grounded through the bypass capacitor 125 and the source 126 and drain 127 are tied together (port-1; 120). By toggling the transistor on and off using an appropriate gate to body voltage, the capacitance of the capacitive circuit element 100 between port-1 and port-2 significantly changes.

Abstract: A trench capacitor with an isolation collar in a semiconductor substrate where the substrate adjacent to the isolation collar is free of dopants caused by auto-doping. The method of fabricating the trench capacitor includes the steps of forming a trench in the semiconductor substrate; depositing a dielectric layer on a sidewall of the trench; filling the trench with a first layer of undoped polysilicon; etching away the first layer of undoped polysilicon and the dielectric layer from an upper section of the trench whereby the semiconductor substrate is exposed at the sidewall in the upper section of the trench; forming an isolation collar layer on the sidewall in the upper section of the trench; and filling the trench with a second layer of doped polysilicon.

Abstract: Non-volatile memory (NVM) devices are disclosed. In one aspect, a NVM device may include a substrate, and a field-effect transistor (FET). The FET may include a first doped region in the substrate and a second doped region in the substrate. The first and the second doped regions may define a channel region of the substrate between them. An insulating layer may overlie the channel region. A floating gate may overlie the insulating layer. Charge of an amount that encodes a value may be stored on the floating gate. The floating gate and the first and the second doped regions may be shaped such that the floating gate defines with the first doped region a first border of a first length, and the floating gate defines with the second doped region a second border of a second length that is less than 90% of the first length.

Abstract: A semiconductor device in accordance with one embodiment of the invention can include a semiconductor substrate having a groove, a bit line, a pocket implantation region, a bottom insulating membrane, and a charge accumulation region. The bit line is formed on a side of the groove in the semiconductor substrate and acts as a source and a drain. The pocket implantation region is formed to touch (or contact) the bit line, has a similar conductivity type as the semiconductor substrate, and has a dopant concentration higher than that of the semiconductor substrate. The bottom insulating membrane is formed on and touches (or contacts) a side surface of the groove. The charge accumulation layer is formed on and touches (or contacts) a side surface of the bottom insulating membrane.

Abstract: A semiconductor device includes: a semiconductor substrate; multiple MOS type first transistors coupled in parallel with a current path; and a nonvolatile memory for memorizing operating information. Each transistor includes first and second electrodes and a gate electrode for controlling current flowing therebetween. Based on the operating information, each first transistor is selectively set to an active state. When the transistors provide a single transistor, an effective channel width of the single transistor is variable in accordance with the number of the first transistors under the active state.

Abstract: A stacked gate nonvolatile semiconductor memory includes at least a memory cell transistor and a selective gate transistor which are formed on a semiconductor substrate. The memory cell transistor includes a floating gate made of a semiconductor material below an interlayer insulating layer and a control gate made of a silicide above the interlayer insulating layer. The selective gate transistor includes a semiconductor layer made of the semiconductor material, a silicide layer made of the silicide and a conductive layer made of a conductive material not subject to silicide process which is formed through the interlayer insulating film so as to electrically connect the semiconductor layer and the silicide layer.

Abstract: A semiconductor device comprises a silicate interface layer and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises metal alloy oxides.

Abstract: Non-volatile memory devices are disclosed. In a first example non-volatile memory device, programming and erasing of the memory device is performed through the same insulating barrier without the use of a complex symmetrical structure. In the example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to a charge storage region. Further in the example device, erasing is accomplished by tunneling positive carriers from the charge supply region to the charge storage region. In a second example non-volatile memory device, a charge storage region with spatially distributed charge storage region is included. Such a charge storage region may be implemented in the first example memory device or may be implemented in other memory devices. In the second example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to the charge storage region.

Abstract: A charge trap memory device according to example embodiments may include a tunnel insulating layer provided on a substrate. A charge trap layer may be provided on the tunnel insulating layer. A blocking insulating layer may be provided on the charge trap layer, wherein the blocking insulating layer may include a lanthanide (e.g., lanthanum). The blocking insulating layer may further include aluminum and oxygen, wherein the ratio of lanthanide to aluminum may be greater than 1 (e.g., about 1.5 to about 2). The charge trap memory device may further include a buffer layer provided between the charge trap layer and the blocking insulating layer, and a gate electrode provided on the blocking insulating layer.

Abstract: A memory device and peripheral circuitry on a substrate are described, made by a process that includes forming a charge trapping structure having a first thickness over a first area. A first gate dielectric layer having a second thickness is formed for low-voltage transistors. A second gate dielectric layer having a third thickness, greater than the second thickness, is formed for high-voltage transistors. Polysilicon is deposited and patterned to define word lines and transistor gates. The thickness of the second gate dielectric layer in regions adjacent the gates, and over a source and drain regions, is reduced to a thickness that is close to that of the second thickness. Dopants are implanted for formation of source and drain regions in the second and third areas. A silicon nitride spacer material is deposited over the word lines and gates, and etched to form sidewall spacers on the gates. Dopants are implanted aligned with the sidewall spacers in the second and third areas.

Abstract: In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p+-type polysilicon film with a high impurity concentration deposited thereon.

Abstract: A semiconductor structure and related method for fabrication thereof includes a liner layer interposed between: (1) a pedestal shaped channel region within a semiconductor substrate; and (2) a source region and a drain region within a semiconductor material layer located upon the liner layer and further laterally separated from the pedestal shaped channel region within the semiconductor substrate. The liner layer comprises an active doped silicon carbon material. The semiconductor material layer may comprises a semiconductor material other than a silicon carbon semiconductor material. The semiconductor material layer may alternatively comprise a silicon carbon semiconductor material having an opposite dopant polarity and lower carbon content in comparison with the liner layer. Due to presence of the silicon carbon material, the liner layer inhibits dopant diffusion therefrom into the pedestal shaped channel region.

Abstract: Disclosed herein is an insulated gate field effect transistor including: (A) a source/drain region and a channel formation region; (B) a gate electrode formed above the channel formation region; and (C) a gate insulating film; wherein the gate insulating film is composed of a gate insulating film main body portion formed between the gate electrode and the channel formation region, and a gate insulating film extension portion extending from the insulating film main body portion to a middle of a side surface portion of the gate electrode, and when a height of the gate electrode is HGate and a height of the gate insulating film extension portion is HIns with a surface of the channel formation region as a reference, a relationship of HIns<HGate is fulfilled.

Abstract: A semiconductor device capable of inhibiting a fabricating process from complication while inhibiting the dielectric strength voltage of a insulating film from reduction is obtained. This semiconductor device includes a groove portion, an insulating film formed on a surface of the groove portion, a gate electrode and a source impurity region, wherein upper ends of the gate electrode, which are portions in contact with the insulating film, are each located at a position identical with or deeper than the range of an impurity introduced from a surface of a semiconductor substrate with respect to the insulating film in order to form the source impurity region and above a lower surface of the source impurity region.

Abstract: Trench portions (10) are formed in a well (5) in order to provide unevenness in the well (5). A gate electrode (2) is formed via an insulating film (7) on the upper surface and inside of the trench portions (10). A source region (3) is formed on one side of the gate electrode (2) in a gate length direction while a drain region (4) on another side. Both of the source region (3) and the drain region (4) are formed down to near the bottom portion of the gate electrode (2). By deeply forming the source region (3) and the drain region (4), current uniformly flows through the whole trench portions (10), and the unevenness formed in the well (5) increase the effective gate width to decrease the on-resistance of a semiconductor device 1 and to enhance the drivability thereof.

Abstract: A first main electrode is provided on one surface thereof. On the other surface thereof, a second semiconductor layer of the first conduction type and a third semiconductor layer of the second conduction type are arranged alternately along the surface. A fourth semiconductor layer of the second conduction type and a fifth semiconductor layer of the first conduction type are stacked on the surfaces of the second and third semiconductor layers. The semiconductor device further comprises a control electrode formed in a trench with an insulator interposed therebetween. The trench passes through the fourth and fifth semiconductor layers and reaches the second semiconductor layer. A sixth semiconductor layer of the first conduction type is diffused from the bottom of the trench. A second main electrode is connected to the fourth and fifth semiconductor layers.

Abstract: A recessed transistor and a method of manufacturing the same are provided. The recessed transistor may include a substrate, an active pin, a gate pattern and source and drain regions. The substrate may include an isolation layer that establishes an active region and a field region of the substrate. The substrate may include a recessed structure having an upper recess formed in the active region and a lower recess in communication with the upper recess. An active pin may be formed in a region between side surfaces of the isolation layer and the lower recess and an interface between the active region and the field region. The gate pattern may include a gate insulation layer formed on an inner surface of the recessed structure and a gate electrode formed on the gate insulation layer in the recessed structure. The source/drain regions may be formed adjacent to the active region and the gate electrode.

Abstract: A trench type power semiconductor device which includes deposited rather than grown oxide in the trenches for the electrical isolation of electrodes disposed inside the trenches from the semiconductor body.

Abstract: In one embodiment, a device is formed in a region of semiconductor material. The device includes active cell trenches and termination trenches each having doped sidewall surfaces that compensate the region of semiconductor material during reverse bias conditions to form a superjunction structure. The termination trenches include a trench fill material that enhances depletion region spread during reverse bias conditions.

Abstract: A FET has a shallow source/drain region, a deep channel region, a gate stack and a back gate that is surrounded by dielectric. The FET structure also includes halo or pocket implants that extend through the entire depth of the channel region. Because a portion of the halo and well doping of the channel is deeper than the source/drain depth, better threshold voltage and process control is achieved. A back-gated FET structure is also provided having a first dielectric layer in this structure that runs under the shallow source/drain region between the channel region and the back gate. This first dielectric layer extends from under the source/drain regions on either side of the back gate and is in contact with a second dielectric such that the back gate is bounded on each side or isolated by dielectric.

Abstract: A semiconductor structure includes a stepped source and drain region located in part within a semiconductor substrate that preferably has a step in a direction of a gate electrode located over a channel region that adjoins the stepped source and drain region within the semiconductor substrate. A stepped portion of the stepped source and drain region covers an extension region within the stepped source and drain region.

Abstract: A floating body dynamic random access memory (DRAM) structure has a shallow source (first source portion) and a deep source (second source portion), of which the deep source is thicker. A portion of the floating body extends beneath the shallow source to provide extra capacitance. Optionally, the portion of the floating body beneath the shallow source may be more heavily doped than the depletion zone of the body to further enhance the capacitance. Also, by forming a raised portion of the source without raising the drain, the same implantation energy may be used to dope the raised source and the regular drain. The resulting floating body DRAM structure has an enhanced source to floating body capacitance and stores more charges. Operating margins for write and sense operations are increased and the performance and stability of the floating body DRAM are enhanced.

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

Abstract: A one transistor DRAM device includes: a substrate with an insulating layer, a first semiconductor layer provided on the insulating layer and including a first source region and a first region which are in contact with the insulating layer and a first floating body between the first source region and the first drain region, a first gate pattern to cover the first floating body, a first interlayer dielectric to cover the first gate pattern, a second semiconductor layer provided on the first interlayer dielectric and including a second source region and a second drain region which are in contact with the first interlayer dielectric and a second floating body between the second source region and the second drain region, and a second gate pattern to cover the second floating body.

Abstract: Disclosed is a tri-gate field effect transistor with a back gate and the associated methods of forming the transistor. Specifically, a back gate is incorporated into a lower portion of a fin. A tri-gate structure is formed on the fin and is electrically isolated from the back gate. The back gate can be used to control the threshold voltage of the FET. In one embodiment the back gate extends to an n-well in a p-type silicon substrate. A contact to the n-well allows electrical voltage to be applied to the back gate. A diode created between the n-well and p-substrate isolates the current flowing through the n-well from other devices on the substrate so that the back gate can be independently biased. In another embodiment the back gate extends to n-type polysilicon layer on an insulator layer on a p-type silicon substrate. A contact to the n-type polysilicon layer allows electrical voltage to be applied to the back gate.

Abstract: A method and system is disclosed for providing access to the body of a FinFET device. In one embodiment, a FinFET device for characterization comprises an active fin comprising a source fin, a depletion fin, and a drain fin; a side fin extending from the depletion fin and coupled to a body contact for providing access for device characterization; and a gate electrode formed over the depletion fin and separated therefrom by a predetermined dielectric layer, wherein the gate electrode and the dielectric layer thereunder have a predetermined configuration to assure the source and drain fins are not shorted.