Abstract: Hermetically sealed packages having organic electronic devices are presented. A number of sealing mechanisms are provided to hermetically seal the package to protect the organic electronic device from environmental elements. A metal alloy sealant layer is employed proximate to the organic electronic device. Alternatively, a metal alloy sealant layer in combination with primer layer may also be implemented. Further, superstrates and edge wraps may be provided to completely surround the organic electronic device.

Abstract: A multi-chip package system is provided including providing a first carrier having a first integrated circuit die thereover, providing a second carrier, placing the first carrier coplanar with the second carrier, and molding a package encapsulation around and exposing the first carrier.

Abstract: A method of implementing an injection molded soldering process for three-dimensional structures, particularly, such as directed to three-dimensional semiconductor chip stacking. Also provide is an arrangement for implementing the injection molded soldering (IMS) process. Pursuant to an embodiment of the invention, the joining of the semiconductor chip layers with a substrate is implemented, rather than by means of currently known wire bond stacking, through the intermediary of columns of solder material formed by the IMS process, thereby providing electrical advantages imparted by the flip chip interconnect structures. In this connection, various diversely dimensioned solder column interconnects allow for simple and dependable connections to a substrate by a plurality of superimposed layers or stacked arrays of semiconductor components, such as semiconductor chips.

Abstract: A carrier plate structure having a chip embedded therein, comprises an aluminum plate having plural through-holes extending from the upper surface to the lower surface of the aluminum plate, a cavity therein, and an aluminum oxide layer formed on the surface of the aluminum plate; a chip embedded in the cavity with an active surface having plural electrode pads set thereon; and at least one build-up structure mounted on the surface of the aluminum plate and the active surface of the chip, wherein the build-up structure comprises at least one conductive structure to electrically connecting to the electrode pad. Besides, a method of manufacturing a carrier plate structure having a chip embedded therein is disclosed.

Abstract: A microelectronic package includes a microelectronic element having a first face including contacts, and a flexible substrate having a first surface and a second surface, conductive posts projecting from the first surface and conductive terminals accessible at the second surface, at least some of the conductive terminals and the conductive posts being electrically interconnected and at least some of the conductive terminals being offset from the conductive posts. The first surface of the flexible substrate is juxtaposed with the first face of the microelectronic element so that the conductive posts project from the flexible substrate toward the first face of the microelectronic element. The conductive posts are electrically interconnected with the contacts of the microelectronic element and at least some of the conductive terminals are movable relative to the microelectronic element.

Abstract: The present invention relates to a package and a method for making the same. The package includes a substrate, a semiconductor element, and an underfill. The semiconductor element has a first surface. A plurality of bumps and at least one ring structure are disposed on the first surface, in which the bumps are outside the ring structure. The semiconductor element is disposed on the substrate through the bumps and the ring structure. The ring structure of the semiconductor element and the substrate define a closed space. The bumps electrically connect the substrate and the semiconductor element. The underfill is filled between the substrate and the semiconductor element, covering the bumps and out of the ring structure. Since the package of the present invention has the closed space, the package is not only applicable for a common flip chip package, but also for micro electro-mechanical systems (MEMS) having movable elements.

Abstract: A semiconductor package structure comprises a chip, a plurality of pad extension traces, a plurality of via holes, a lid and a plurality of metal traces, wherein the chip has an optical component and a plurality of pads disposed on its active surface; pad extension traces are electrically connected to the pads; the via holes penetrate the chip and are electrically connected to the pad extension traces and exposed out of side surfaces of the semiconductor package structure; the lid is adhered onto the active surface of the chip; and the plurality of metal traces is disposed on the back surface of the chip, electrically connected to the plurality of via holes, and used to define a plurality of solder pads thereon. The present invention also provides a method for manufacturing the semiconductor package structure.

Abstract: The present invention provides a stackable semiconductor having an interconnect board for providing electrical interconnections, the package includes a plurality of solders disposing onto the interconnect board; and a conducting metal pin passing through each solder and the interconnect board, the metal pins having at least one end disposes on the semiconductor package, wherein when a plurality of the stackable semiconductor packages are stacked together, the exposed end of the corresponding conducting pins are bonded together. A method of manufacturing the same is also provided.

Abstract: A semiconductor device including a plurality of semiconductor elements on a substrate, the semiconductor device includes: a plurality of semiconductor elements being provided two-dimensionally on a first surface of the substrate via an adhesive layer; and a hard member on surfaces of the plurality of semiconductor elements, the surfaces being on opposite sides with respect to other surfaces of the plurality of semiconductor elements which other surfaces face the first surface. This makes it possible to realize a thin semiconductor device that can prevent warping of the semiconductor device including a plurality of semiconductor elements.

Abstract: The chip package and the process thereof are disclosed. The chip package comprises a chip and a rigid cover. The chip has a plurality of bond pads formed thereon. The rigid cover is located on the chip and has a plurality of openings formed therein, wherein the openings expose the bond pads on the chip respectively.

Abstract: A semiconductor package substrate structure includes a circuit board with a plurality of first connection pads formed on at least a surface thereof; conductive posts formed on the surfaces of the first connection pads; and an insulative protection layer formed on the surface of the circuit board and having openings formed to completely expose the conductive posts, the conductive posts protruding above the surface of the substrate, thereby the electrical connection between the conductive posts and a semiconductor chip is facilitated, and the quality and the reliability of subsequent packaging process are ensured.

Abstract: A semiconductor device is provided in which the effect of the heat generated by a flip-chip mounted semiconductor on resin is suppressed. The semiconductor device includes: a substrate; a semiconductor chip which is mounted on the substrate with a front surface of the semiconductor chip facing downward; and a molding resin layer provided on a semiconductor chip-mounted surface of the substrate so as to be spaced apart from the semiconductor chip and to surround the semiconductor chip. In addition, the upper surface of the molding resin layer is positioned higher than the rear surface of the semiconductor chip.

Abstract: Embodiments of the invention includes a heat dissipating device. The heat dissipating device includes a main body having a surface, wherein the surface is plated or coated with at least two different metals to form a design effective for bonding to solder and for adhering to polymer in a polymer solder hybrid. The heat dissipating device also includes surface perturbations.

Abstract: A method of forming channels on a die or other substrate. Also disclosed are liquid cooling systems including such channels.

Abstract: A semiconductor device having a topology adjustment and a method for adjusting the topology of a semiconductor device. The semiconductor device includes a semiconductor wafer having first and second opposing sides with an active area formed on a first portion of the first side having a topology extending a first distance above the first side. A support member is attached to a second portion of the first side and extending a second distance above the first side, wherein the first distance is about the same as the second distance. In some exemplary embodiments, the support member is formed by applying adhesive to the second portion. The wafer is then spun to adjust the second distance.

Abstract: A manufacturing method of a bump structure having a reinforcement member is disclosed. First, a substrate including pads and a passivation layer is provided. The passivation layer has first openings, and each first opening exposes a portion of the corresponding pad respectively. Next, an under ball metal (UBM) material layer is formed on the substrate to cover the passivation layer and the pads exposed by the passivation layer. Bumps are formed on the UBM material layer and the lower surface of each bump is smaller than that of the opening. Each reinforcement member formed on the UBM material layer around each bump contacts with each bump, and the material of the reinforcement member is a polymer. The UBM material layer is patterned to form UBM layers and the lower surface of each UBM layer is larger than that of each corresponding opening. Hence, the bump has a planar upper surface.

Abstract: A semiconductor device includes a semiconductor chip mounted on a printed circuit board with a chip electrode being coupled to a board electrode via a bump electrode. An insulating resin layer including therein conductive particles is interposed between the bump electrode and each of the chip electrode and board electrode. The conductive particles couple together the bump electrode and the each of the chip electrode and the board electrode. The conductive particles and the bump electrode are deformed to have a flat shape due the stress applied between the semiconductor chip and the printed circuit board.

Abstract: An embodiment of the present invention is an interconnect technique. A nanostructure bump is formed on a die. The nanostructure bump has a template defining nano-sized openings and metallic nano-wires extending from the nano-sized openings. The die is attached to a substrate via the nanostructure bump.

Abstract: An integrated circuit packaging system is provided including forming an interposer having a coupling slot, securing an upper die on the interposer, mounting the interposer over an integrated circuit, and coupling the integrated circuit to the upper die through the coupling slot.

Abstract: A package structure and method for preventing gold bonding wires from collapsing are disclosed. The structure is especially useful for those chips whose two n×1 arrays of bonding pads are on the chip center to be packaged on a BGA substrate. According to the first preferred embodiment, two dies having a redistribution layer formed thereon are introduced outer the bonding pad array on the chip so that the gold bonding wires can be divided into two sections each to connect the bonding pads with the redistribution layer and the redistribution layer with the gold fingers on the BGA substrate. According to the second embodiment, the gold bonding wires are fixed by the epoxy strips on the chips after bonding the bonding pads to the gold fingers but before pouring liquid encapsulated epoxy into a mold.

Abstract: A semiconductor device of the present invention includes a circuit board having a number of electrode portions on the front side and the underside, an electronic circuit element such as a semiconductor chip bonded to the electrode portions on the front side of the circuit board and composing an electronic circuit; and a plurality of ball electrodes for external connection, the ball electrodes being formed on the electrode portions on the underside of the circuit board. Of the electrode portions on the underside of the circuit board, an electrode portion on the outer periphery is formed larger than an electrode portion on the inner periphery. The plurality of ball electrodes are solder balls heated and melted on the electrode portions on the underside of the board so as to form an alloy on the interfaces, the solder balls containing tin and silver but not containing lead.

Abstract: An integrated circuit structure having air gaps is provided. The integrated circuit includes a conductive line; a sidewall spacer on a sidewall of the conductive line, wherein the sidewall spacer comprises a dielectric material; an air-gap horizontally adjoining the sidewall spacer; and a dielectric layer on the air-gap.

Abstract: An antifuse includes a first conductor pattern, a sidewall insulating film formed on a side of the first conductor pattern, and a second conductor pattern formed so that the sidewall insulating film is interposed between the first and second conductor patterns and so as to face the side of the first conductor pattern. The antifuse utilizes the sidewall insulating film as a capacitor insulating film of a capacitor.

Abstract: A semiconductor metal structure with an efficient usage of the chip area is provided. The structure includes a substrate, a copper-based interconnection structure over the substrate, the copper-based interconnection structure comprising a plurality of metallization layers connected by vias and in first dielectric layers, at least one aluminum-based layer over and connected to the copper-based interconnection structure, wherein a top layer of the at least one aluminum-based layer comprises a bond pad and an interconnect line connecting to two underlying vias, vias/contacts connecting a top layer of the copper-based interconnection structure and a bottom layer of the at least one aluminum-based layer, wherein the vias/contacts are in a second dielectric layer, and a third dielectric layer overlying the at least one aluminum-based layer, wherein the bond pad is exposed through an opening in the third dielectric layer.

Abstract: A semiconductor substrate having a body and a plurality of finger pads formed thereon is disclosed. Each of the finger pads includes two expanding portions respectively and a connecting portion formed therebetween. The finger pads are alternately arranged on the body in a manner that one of the expanding portions of one of the finger pads is disposed in position corresponding to the connecting portion of an adjacent one of the finger pads, so as to reduce pitches between the finger pads horizontally and vertically, provide sufficient spaces for wire bonding, and prevent a wire bonder from mistakenly recognizing a lead trace coupled to the finger pad as another finger pad.

Abstract: A semiconductor package substrate proposed by the invention includes a base body and a plurality of finger pads disposed on surface of the base body, wherein the finger pads are arranged in such a way that an angle is formed between connecting line of centers of two adjacent finger pads and the direction in which the finger pads are arranged. The finger pads are waterdrop shaped finger pads with arc ends and angle ends alternately disposed on surface of the substrate, alternately disposed waterdrop shaped finger pads and arc shaped finger pads, or alternately disposed arc shaped finger pads at a predetermined spacing. According to the present invention, distance between adjacent finger pads is reduced and problem of short circuit as a result of erroneous contact between bonding wire and adjacent finger pad is prevented.

Abstract: In a semiconductor device including an upper-layer wiring and a lower-layer wiring that overlaps the upper-layer wiring, an wiring switching option includes a via extending from the upper-layer wiring toward the lower-layer wiring. The wiring switching option switches a wiring connection state according to whether the via extends from the upper-layer wiring to reach the lower-layer wiring or extends from the upper-layer wiring to terminate in between the upper-layer wiring and the lower-layer wiring.

Abstract: A method for manufacturing a microelectronic circuit includes the steps of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material; forming a plurality of alternating layers of layer dielectric material and sacrificial material over the first wiring level; and forming a plurality of interconnect openings and a plurality of gap openings in the alternating layers of layer dielectric material and sacrificial material. The interconnect openings are formed over the first wiring level conductors. The method further includes forming (i) metallic conductors comprising second wiring level conductors, and (ii) interconnects, at the interconnect openings; and removing the layers of the sacrificial material through the gap openings.

Abstract: A semiconductor device is provided with a film substrate that has through-vias that are formed by filling a conductive material in through-holes that pass through the front and rear of a film-shaped substrate body and wiring or terminals that connect to the through-vias, with a semiconductor element being mounted on the film-shaped substrate body by terminal members thereof being electrically connected to the wiring or terminals of the film substrate.

Abstract: A memory device described herein includes a bit line having a top surface and a plurality of vias. The device includes a plurality of first electrodes each having top surfaces coplanar with the top surface of the bit line, the first electrodes extending through corresponding vias in the bit line. An insulating member is within each via and has an annular shape with a thickness between the corresponding first electrode and a portion of the bit line acting as a second electrode. A layer of memory material extends across the insulating members to contact the top surfaces of the bit line and the first electrodes.

Abstract: A stacked structure of semiconductor chips includes plural stacked semiconductor chips and plural tabular holding members which hold the respective semiconductor chips.

Abstract: This invention provides a semiconductor device. The semiconductor device includes a bonding pad array comprising: a signal bonding pad, a control pin bonding pad and at least one stacking bonding pad on an active surface. At least one stacking bonding pad is adjacent to the control pin bonding pad. This invention also provides a stacked structure of semiconductor devices and/or a semiconductor device package including the semiconductor device.

Abstract: An LSI package encompasses a transmission line header embracing a header-base, a transmission line held by the header-base, and an interface IC chip mounted on the header-base, an interposer substrate having a plurality of board-connecting joints, which facilitate connection with the printed wiring board; an LSI chip mounted on the interposer substrate; and a receptacle having a lead terminal and being mounted on the interposer substrate, configured to accommodate the transmission line header so that the interface IC chip electrically connects to the LSI chip through the lead terminal.

Abstract: A power control method and power control structures are provided for managing a plurality of voltage islands of a functional chip. The power control structure includes a supply control and partition chip positioned between a substrate carrier and a functional chip including a plurality of voltage islands. The supply control and partition chip includes a plurality of first electrical connections to the functional chip including the plurality of voltage islands. The supply control and partition chip includes a plurality of second electrical connections to the substrate carrier. Power applied to predefined ones of the first electrical connections to the functional chip are selectively switched on and off by the supply control and partition chip.

Abstract: A semiconductor device is provided which comprises a substrate (501) having a plurality of bond pads (503) disposed thereon. Each bond pad has a major axis and a minor axis in a direction parallel to the substrate, and the ratio of the major axis to the minor axis increases with the distance of a bond pad from the center of the substrate.

Abstract: An integrated circuit module has a common function known good integrated circuit die with selectable functions. The selectable functions are selected during packaging of the known good integrated circuit die. The known good integrated circuit die is mounted to a second level substrate. The second level substrate has wiring connections to the input/output pads of the known good integrated circuit die that select desired input functions and output functions. Further, the wiring connections on the second level substrate provide signal paths to transfer signals to the desired input function and signals from the desired output function, and signals to and from the common functions. Also, the wiring connections form connections between the input/output pads and external circuitry. To select the desired input functions and the desired output functions, appropriate logic states are applied to input/output pads connected to a function selector to configure a functional operation of the integrated circuit module.

Abstract: An integrated circuit system is provided including forming a wire ball on a bond wire; forming a shaped ball from the wire ball; and attaching the shaped ball on an integrated circuit die.

Abstract: A semiconductor device and a method for fabricating the same are disclosed. According to some embodiments, a semiconductor device comprises a lower structure formed on a semiconductor structure. The lower structure has chip pads. The semiconductor device further comprises a passivation layer located over the chip pads. The passivation layer comprises first openings defined therein to expose at least a portion of the chip pads. The semiconductor device additionally includes at least two adjacent redistribution lines spaced apart from each other and located over the passivation layer. The at least two redistribution lines are respectively coupled to the chip pads through corresponding ones of the first openings. The semiconductor device comprises a first insulation layer located over the passivation layer. The first insulation layer includes a void extending between the at least two adjacent redistribution lines.

Abstract: A semiconductor substrate for having enhanced adhesion to semiconductor device and its manufacturing method are provided. The wire circuit layout on the surface of the semiconductor substrate is of a specialized design and surface treatment for enhanced adhesion between the packaged adhered material and the substrate surface (the bonding pad in particular). In the manufacturing method of the semiconductor substrate, the processing by the passivation treatment or the roughening treatment of the whole or a part of the bonding pad on the substrate, such as the brown-oxide treatment or the black-oxide treatment, etc, and the use of an enlarged contact area act to enhance adhesion to the semiconductor device during the packaging of the semiconductor device.

Abstract: A semiconductor module and a method for producing the same is disclosed. One embodiment provides that an intermediate element has been or is formed, which has been or is formed for making electrical contact materially between a contact region provided and a connection region provided and in direct material and electrical contact with and for area adaptation between these.

Abstract: A memory device having dummy pattern comprises: an alignment mark, provided at a predetermined position on a semiconductor substrate, for aligning position in manufacturing process based on an optical detection signal obtained by scanning in a first direction or in a second direction orthogonal to the first direction in a substrate plane; a real pattern formed in a wiring layer on the semiconductor substrate and used for circuit wiring; and a dummy pattern formed in the wiring layer and used in CMP method. The dummy pattern includes a plurality of basic patterns having a predetermined shape asymmetrical with respect to the first and second directions, and respective pattern portions crossing the basic patterns in the first and second directions in an area in which the dummy pattern is formed are not repeatedly arranged with a constant gap.

Abstract: A twist locking connector for a steam humidifier. The steam humidifier includes a tank for heating water to generate steam and a steam tube receiver structure in fluid communication with the tank. The steam tube receiver structure has an opening configured to receive a steam tube, where the opening has a plurality of ramp structures about the opening on a side facing the tank. The steam humidifier also includes a steam tube for transmitting steam from the tank to a duct, the steam tube having a plurality of locking tabs adjacent to an end and a flange adjacent to, but separated by a distance from, the locking tabs. The steam tube is assembled to the steam tube receiver by inserting the steam tube through the opening in the steam tube receiver structure and rotating the steam tube to cause the locking tabs to engage with the ramp structures.

Abstract: There is provided a method of producing U3O8 powder having large surface area and small particle size by oxidizing defective UO2 pellets and manufacturing nuclear fuel pellets which are stable in a pore structure and high in density through the use of a mixture comprising UO2 powder and U3O8 powder. The method includes producing an U308 powder having a surface area of at least 1 m2/g by oxidizing defective UO2 pellets at a temperature of 300 to 370? in such a way that a maximum weight increase rate per 1 g of the UO2 pellets is up to 0.06 wt %/min; producing a mixed powder by mixing the U3O8 powder with an UO2 powder by 2 to 15 wt %; producing a compact by compression molding the mixed powder; and sintering the compact in a reducing gas atmosphere at a temperature of 1600 to 1800?. In addition, a small amount of an Al-compound may be added to the oxidized U3O8 powder before the U3O8 powder is mixed with the UO2 powder.

Abstract: A thermal conductive system for curing ophthalmic devices within molds includes pairs of lower and upper heating units that are relatively displaceable for both clamping anterior and posterior mold parts together and conducting heat through the mold parts for curing the ophthalmic devices. The molds can be mounted in thermal engagement with the lower heating units, and the molds can be moved together with the lower heating units into thermal engagement with the upper heating units. Control systems individually regulate the temperatures of the heating units.

Abstract: A molded panel for buildings is manufactured in a manner that permits the blocking tab along the upper edge of the panel to be molded in a position that is close to its final desired position. Pressure is applied to the locking tab as it cools, thereby bringing the locking tab into its final position.

Abstract: A molded animal chew toy including a resin, a fluid such as water, and meat jerky, particularly chicken jerky, is provided. Processes for forming such resin/water/jerky composition into shapes by direct injection molding, including a desired screw design, are also disclosed.

Abstract: In an injection mold, a compression pin is placed at a cavity surface by the pressing force of a biasing member, and is moved rearward by the pressure of filled resin so as to form a compression boss. After the completion of filling, the compression boss is compressed by the compression pin.

Abstract: A roofing panel, a roof, an array of roofing panels, and a method of manufacturing a roofing panel by transporting a capstock layer of the roofing panel through a moving belt mold, and forming a polymeric material in situ against the outer layer while in a mold cavity of the moving belt mold. The capstock layer is vacuum formed to shape and form a plurality of roofing shingles and to impress the shingles with surface topography features simulating natural materials.

Abstract: A lightweight composite panel exhibiting a high degree of stiffness and strength includes a non-woven fibrous batt comprising more than 50% by weight synthetic fibers, and a geopolymer disposed on and/or within the fibrous batt to impart rigidity to the composite panel. The composite panel may include additional functional and/or aesthetic layers, and may be either flat or contoured. The resulting panels have various architectural, automotive and furniture applications.

Abstract: A composition is provided that, in one aspect, may be used in the production of sealing materials, such as gaskets. The composition includes a polytetraflouroethylene matrix and a Boron Nitride filler. In one aspect, the Boron Nitride filler may be provided as a hexagonal, close-packed, Boron Nitride filler that is homogeneously dispersed within the polytetraflouroethylene matrix. In at least one embodiment, the composition is formed by combining quantities of polytetraflouroethylene, Boron Nitride filler, hydrocarbon liquid, and solvent. The liquid and solvent may be removed through various processes prior to sintering the composition to form a full-density, Boron Nitride filled, polytetraflouroethylene matrix that exhibits improved sealability, greater resistance to permeation, and less color contamination.