Abstract: A novel amino acid transporter molecule mediating transportation of amino acids, which are nutrients essentially required in the survival and proliferation of various normal cells constituting a living body and various pathology-associated abnormal cells such as tumor cells, into cells and being expressed specifically in tumor cells compared with normal cells; and drugs for treating various pathogenic conditions such as tumor (cancer) which are obtained by identifying and isolating the above amino acid transporter molecule and identifying a substance capable of inhibiting the biological activity and/or expression of this molecule. Intensive studies were made to identify a tumor cell membrane surface molecule associating or interacting with a cell membrane surface 4F2hc molecule seemingly playing an important role in the activation of an unknown amino acid transporter.

Abstract: The present invention relates to the production of proteins in a cell or host cell. The invention uses a TRAnscription Pause (TRAP) sequence to enhance a protein expression characteristic of a protein expression unit. The TRAP sequence is thought to prevent, at least in part, formation of antisense RNA or to, at least in part, prevent transcription to enter the protein expression unit. In one embodiment, the invention provides a method for expression of at least one protein of interest in a cell comprising providing the cell with at least one protein expression unit that comprises a promoter functionally linked to an open reading frame encoding at least one protein of interest, characterized in that the protein expression unit further comprises at least one TRAP sequence and wherein the TRAP sequence is functionally located downstream of the open reading frame and at least in part prevents formation of antisense RNA.

Abstract: Hepatic progenitors comprise two populations of human hepatic stem cells, primitive and proximal hepatic stem cells, and two populations of committed progenitors, one for biliary cells and one for hepatocytes. Human primitive hepatic stem cells are a very small fraction of the liver cell population and give rise to proximal hepatic stem cells constituting a much larger fraction of the liver. Human proximal hepatic stem cells give rise to biliary and hepatocyte committed progenitors. Primitive and proximal stem cells are the primary stem cells for the human liver. Human primitive hepatic stem cells may be isolated by immunoselection from human livers or culturing human liver cells under conditions which select for a human primitive hepatic stem cell. Proximal hepatic stem cells may be isolated by immunoselection, or by culturing human liver cells under conditions which include a developmental factor.

Abstract: The invention provides neuron-derived cells obtained by transfecting a receptor-expressing nucleic acid having an aryl hydrocarbon receptor gene, wherein outgrowth of neurites is not observed without adding a substance for the aryl hydrocarbon receptor, and outgrowth of neurites is observed by adding the substance for the aryl hydrocarbon receptor. The invention also provides a method for determining the presence of neurotoxicity of a test substance, a method for acquiring a marker for determining the presence of neurotoxicity of the test substance, a method for acquiring a marker for neurological dysfunction, and a method for determining the effect of the test substance on neurological dysfunction using such cells.

Abstract: The present invention relates to cDNA sequences from a region of amplification on chromosome 20 associated with disease. The sequences can be used in hybridization methods for the identification of chromosomal abnormalities associated with various diseases. The sequences can also be used for treatment of diseases.

Abstract: Aspects of the invention provide an immortalized fibroblast cell line capable of the growth and maintenance of human embryonic stem cells. An immortalized fibroblast cell line derived from an early stage mouse embryo is provided. Methods of preparing an immortalized fibroblast cell line from an early stage mouse embryo are also provided.

Abstract: The present invention provides a pancreas induced in vitro that is useful for developmental engineering and organ engineering, and a method wherein a pancreas induced in vitro which contributes to the development of diagnosis and treatment of pancreatic disorders for higher animals, can artificially and efficiently be induced from a gastrula apart from the presumptive region of pancreas. An explant which has a secretory gland-like structure wherein several cells are gathered and which expresses insulin is formed in vitro by treating the blastopore upper lip of an early gastrula of a vertebrate such as Xenopus with retinoic acid in vitro, and then culturing. The treatment with retinoic acid can be carried out, for example, by treating with retinoic acid at a concentration of 10?5 M or above for three hours.

Abstract: Methods and materials for culturing primate-derived primordial stem cells are described. In one embodiment, a cell culture medium for growing primate-derived primordial stem cells in a substantially undifferentiated state is provided which includes a low osmotic pressure, low endotoxin basic medium that is effective to support the growth of primate-derived primordial stem cells. The basic medium is combined with a nutrient serum effective to support the growth of primate-derived primordial stem cells and a substrate selected from feeder cells and an extracellular matrix component derived from feeder cells. The medium further includes non-essential amino acids, an anti-oxidant, and a first growth factor selected from nucleosides and a pyruvate salt.

Abstract: The present invention provides methods, media and compositions capable of modulating the differentiation of stem cells. Applicants have discovered that agonists of lysophospholipid receptors and ligands of class III tyrosine kinase receptors are useful in preventing the spontaneous differentiation of stem cells. The ligands and agonists may be used alone, or in combination where they have a synergistic effect. Also provided are cells produced using the methods and media, and methods of treating stem cell related diseases using the compositions described herein. Methods of identifying compounds useful in finding other agents useful in the modulation of stem cell differentiation are also disclosed.

Abstract: This disclosure provides a system for obtaining genetically altered primate pluripotent stem (pPS) cells. The role of the feeder cells is replaced by supporting the culture on an extracellular matrix, and culturing the cells in a conditioned medium. The cells can be genetically altered with a viral vector or DNA/lipid complex, and then selected for successful transfection by drug-resistant phenotype in the transfected cells. The system allows for bulk proliferation of genetically altered pPS cells as important products for use in human therapy or drug screening.

Abstract: The present invention relates to a reagent for classifying leukocytes including (a) at least one surfactant capable of lysing erythrocytes and partly damaging the cell membrane of leukocytes, (b) at least one organic compound bearing an anionic group capable of binding to the cationic component present in the leukocytes to provide morphological differences between the leukocytes, and (c) a buffer for adjusting pH to 2˜8. Also disclosed is a method for classifying leukocytes into four groups.

Abstract: In proteomic research, it is often necessary to screen a large number of polypeptides for the presence of stable structure. Described herein are methods (referred to as MALDI MS-HX and SUPREX) for measuring the stability of proteins in a rapid, high-throughput fashion. The method employs hydrogen exchange to estimate the stability of quantities of unpurified protein extracts, using matrix-assisted laser desorption/ionization (MALDI) mass spectrometry. A method of quantitatively determining the stability of a test protein under native conditions is disclosed.

Abstract: The present invention is directed toward novel matrix elements, generally comprising functionalized carbon nanotubes, for matrix-assisted laser desorption ionization (MALDI)-mass spectroscopy (MS), methods of making such matrix elements, and to methods of using such matrix elements in MALDI-MS applications, particularly for the analysis of biological molecules. In some embodiments, by carefully tuning the absorption characteristics of the matrix element, biomolecular analytes can be sequenced.

Abstract: A gel extraction device comprising a hollow cutting member having a cutting edge at one end and a squeeze bulb at the other end. In a further embodiment, the air passage between the cutting edge and the bulb has a constriction zone to prevent any extracted gel from being drawn too deeply into the extractor. In a further embodiment, a blow-hole in the hollow cutting member or in the squeeze bulb provides for the passage of air displaced by gel through the extractor. The blow-hole may be covered to secure the gel in the receptacle for transfer from the matrix to a sample container.

Abstract: This invention relates generally to methods and apparatus for desorption and ionization of analytes for the purpose of subsequent scientific analysis by such methods, for example, as mass spectrometry or biosensors. More specifically, this invention relates to the field of mass spectrometry, especially to the type of matrix-assisted laser desorption/ionization, time-of-flight mass spectrometry used to analyze macromolecules, such as proteins or biomolecules. Most specifically, this invention relates the sample probe geometry, sample probe composition, and sample probe surface chemistries that enable the selective capture and desorption of analytes, including intact macromolecules, directly from the probe surface into the gas (vapor) phase without added chemical matrix.

Abstract: A multi-well assembly (10) comprises a multi-well block (12) and a guide plate (14). The multi-well block (12) has a plurality of wells (18) each with a fluid-impermeable bottom surface (22). The guide plate (14) has a plurality of fluid passageways (34) corresponding to the wells (18) of the multi-well block (12). The guide plate (14) is configured to establish fluid communication between each well (18) and an associated fluid passageway (34) when the guide plate (14) is aligned with the multi-well block (12).

Abstract: An object of the present invention is to provide a method for measuring a rate coefficient by surface plasmon resonance analysis with excellent accuracy, reliability, and cost performance that can improve the assay accuracy and simplify the apparatus.

Abstract: A microsensor fabricated with a ferroelectric material and a fabrication method therefor are provided. The microsensor includes a support, an insulating layer on the support, a first electrode on the insulating layer, a ferroelectric layer having at least a metal on the insulating layer and the first electrode, and at least a second electrode on the ferroelectric layer.

Abstract: Two ferroelectric capacitors including a PZT film are connected to one MOS transistor. Electrodes of the ferroelectric capacitor are arranged above a main plane of a substrate parallel to the main plane. Therefore, high capacity can be obtained easily. Furthermore, a (001) direction of the PZT film is parallel to the virtual straight line linking between the two electrodes. Therefore, a direction in which an electric field is applied coincides with a direction of a polarization axis, so that high electric charge amount of remanent polarization can be obtained.

Abstract: A process of manufacturing a semiconductor device utilizing a thermo-chemical reaction is started based on preset initial settings, a state function of an atmosphere associated with the thermo-chemical reaction is measured, a state of the atmosphere and a change thereof are analyzed based on measurement data obtained by the measurement, and then, analysis data obtained by the analysis is fed back to a manufacturing process.

Abstract: Methods of micro-machining a semiconductor substrate to form through fluid feed slots therein. One method includes providing a semiconductor substrate wafer having a thickness greater than about 500 microns and having a device side and a back side opposite the device side. The back side of the wafer is mechanically ground to provide a wafer having a thickness ranging from about 100 up to about 500 microns. Dry etching is conducted on the wafer from a device side thereof to form a plurality of reentrant fluid feed slots in the wafer from the device side to the back side of the wafer.

Abstract: A light emitting element having a superior light emitting characteristic is provided by forming a region partly including a phosphor (light emitting region) in manufacturing of a light emitting element having an organic compound layer using a high molecular weight material. A solution in which a high polymer having a degree of polymerization of 50 or more is dissolved in a solvent is applied by a spin coating method, and then a low polymer which is composed of the same repetition units as the high polymer and has a degree of polymerization of 2 to 5 and a phosphor are coevaporated to form a light emitting region (105) and only a low polymer is vapor-deposited on the light emitting region to form an organic compound layer (103). Thus, the light emitting region (105) can be partly formed.

Abstract: An optoelectronic device includes a submount and a lid. The submount includes a substrate and a lens and a laser above the substrate. The lid defines a cavity having a surface coated with a reflective material to form a 45 degree mirror. The mirror reflects a light from the laser to the lens and the light exits the optoelectronic device through the submount.

Abstract: Methods are disclosed for forming a vertical semiconductor light emitting diode (VLED) device having an active layer between an n-doped layer and a p-doped layer; and securing a plurality of balls on a surface of the n-doped layer of the VLED device.

Abstract: Methods of manufacturing a diagnostic layer containing an array of sensing elements. The sensing elements, associated wires, and any accompanying circuit elements, are incorporated various layers of a thin, flexible substrate. This substrate can then be affixed to a structure so that the array of sensing elements can analyze the structure in accordance with structural health monitoring techniques. The substrate can also be designed to be incorporated into the body of the structure itself, such as in the case of composite structures.

Abstract: A double-sided etching method using an embedded alignment mark includes: preparing a substrate having first and second alignment marks embedded in an intermediate portion thereof; etching an upper portion of the substrate so as to expose the first alignment mark from a first surface of the substrate; etching the upper portion of the substrate using the exposed first alignment mark; etching a lower portion of the substrate so as to expose the second alignment mark from a second surface of the substrate; and etching the lower portion of the substrate using the exposed second alignment mark.

Abstract: A method of manufacturing an image sensor comprises forming an isolation layer defining an active region in a semiconductor substrate using a first mask pattern formed on the semiconductor substrate, forming a first ion implantation mask pattern by reducing a width of the first mask pattern to expose an edge portion of the active region around the isolation layer, forming a first hole accumulation region by implanting a first conductive type of impurity ions into the edge portion of the active region using the first ion implantation mask pattern, forming a second ion implantation mask pattern covering the isolation layer and the first hole accumulation region, and forming a photodiode by implanting a second conductive type of impurity ions into a region of the semiconductor substrate using the second ion implantation mask pattern, wherein at least a portion of the region is surrounded by the first hole accumulation region in the active region.

Abstract: A method of fabricating a pixel structure is disclosed. A substrate having a color filter layer thereon and a leveling layer further covers the color filter layer is provided. A first metal layer is formed over the leveling layer. The first metal layer is patterned to define a source/drain. A channel material layer, a gate insulating layer and a second metal layer are formed over the substrate to cover the source/drain. The second metal layer, the gate insulating layer and the channel material layer are patterned to define a gate and a channel layer. A passivation layer is formed over the substrate to cover the gate. The passivation layer is patterned to expose a portion of the drain. A transparent conductive layer is formed over the substrate, and is electrically connected to the exposed drain. Thereafter, the transparent conductive layer is patterned to form a pixel electrode.

Abstract: Provided is a manufacturing method of a CMOS image sensor. The method includes forming an interlayer insulating layer, a color filter layer, and a planarizing layer. A first photoresist is applied on the planarizing layer, and patterning of the first photoresist is performed using a first mask to form a microlens pattern corresponding to photodiodes on a semiconductor substrate. The microlens pattern is reflowed to form dome-shaped microlenses. A second photoresist is applied on the resulting substrate, and patterning of the second photoresist is preformed using a second mask to retain the second photoresist on top portions of the microlenses. Edge portions of the microlenses are selectively removed using the patterned second photoresist as a mask to make CD (critical dimension) spaces between the microlenses uniform.

Abstract: A process for forming a catalyst layer for carbon nanotube growth comprising forming a catalyst layer having a first and second portion over one of a cathode metal layer or a ballast resistor layer; patterning a photoresist over the first portion; etching the second portion with a chlorine/argon plasma; removing the photoresist with an ash process; and removing the veils and preparing the surface for carbon nanotube growth with a semi-aqueous hydroxylamine solution.

Abstract: According to this invention, a method for fabricating a semiconductor package, in which a plurality of semiconductor chips having a through electrode is layered on a semiconductor interposer, comprising: mounting and layering a plurality of semiconductor chips on a first surface of a semiconductor wafer, which is to be used for a semiconductor interposer; forming a mold resin over the semiconductor chips to cover the semiconductor chips entirely; and dicing the semiconductor wafer to form a plurality of individual semiconductor packages.

Abstract: A method of making a microelectronic package includes providing a first substrate having a top surface, providing a second substrate having a top surface including a plurality of conductive pads, a bottom surface remote therefrom and an opening extending between the top and bottom surfaces, and securing the second substrate over the first substrate so that the bottom surface of the second substrate confronts the top surface of the first substrate, wherein the first and second substrates have coefficients of thermal expansion that are substantially similar to one another.

Abstract: An apparatus and method for enhancing the formation of fillets around the periphery of assembled wafer-level chip scale packages when mounted onto substrates. The method includes fabricating a plurality of integrated circuit die on a first surface of a semiconductor wafer, each of the integrated circuit die being separated by scribe lines on the wafer. Once the circuitry has been fabricated, grooves are formed along the scribe lines on the first surface of the semiconductor wafer. The first surface of the semiconductor wafer is then covered with a layer of underfill material, including within the grooves formed along the scribe lines on the first surface of the semiconductor wafer. After the wafer is singulated, the resulting die includes a first top surface and a second bottom surface and four side surfaces. Integrated circuitry is formed on the first surface of the die. Recess regions created by cutting the grooves are formed on all four side surfaces of the die and filled with the underfill material.

Abstract: A die-wafer package includes a singulated semiconductor die having a first plurality of bond pads on a first surface and a second plurality of bond pads on a second opposing surface thereof. Each of the first and second pluralities of bond pads includes an under-bump metallization (UBM) layer. The singulated semiconductor die is disposed on a semiconductor die site of a semiconductor wafer and a first plurality of conductive bumps electrically couples the first plurality of bond pads of the singulated semiconductor die with a first set of bond pads formed on the semiconductor die site. A second plurality of conductive bumps is disposed on a second set of bond pads of the semiconductor die site. A third plurality of conductive bumps is disposed on the singulated semiconductor die's second plurality of bond pads. The second and third pluralities of conductive bumps are configured for electrical interconnection with an external device.

Abstract: An integrated chip package structure and method of manufacturing the same is by adhering dies on an organic substrate and forming a thin-film circuit layer on top of the dies and the organic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.

Abstract: A plurality of inner leads, a plurality of outer leads formed in one with each of the inner lead, a bar lead of the square ring shape arranged inside a plurality of inner leads, a corner part lead which has been arranged between the inner leads of the end portion of the inner lead groups which adjoin among four inner lead groups corresponding to each side of the bar lead, and was connected with the bar lead, and a tape member joined to the tip part of each inner lead, a bar lead, and a corner part lead are included. Since the corner part lead is formed as an object for reinforcement of a frame body between adjoining inner lead groups, the rigidity of the lead frame can be increased.

Abstract: The invention is directed to improvement of reliability of a chip size package type semiconductor device in a manufacturing method thereof. A support body is formed on a front surface of a semiconductor substrate with a first insulation film therebetween. Then, a part of the semiconductor substrate is selectively etched from its back surface to form an opening, and then a second insulation film is formed on the back surface. Next, the first insulation film and the second insulation film at a bottom of the opening are selectively etched, to expose pad electrodes at the bottom of the opening. Then, a third resist layer is selectively formed on a second insulation film at boundaries between sidewalls and the bottom of the opening on the back surface of the semiconductor substrate. Furthermore, a wiring layer electrically connected with the pad electrodes at the bottom of the opening and extending onto the back surface of the semiconductor substrate is selectively formed corresponding to a predetermined pattern.

Abstract: A power amplifier includes a substrate, a heat sink for dissipating heat, and a heterojunction bipolar transistor (HBT) disposed on the substrate. The HBT includes a collector, a base, and at least an emitter. The power amplifier further includes an emitter electrode directly connecting the heat sink and the emitter of the HBT. The emitter electrode is a flip-chip bump, and the heat sink is a metal layer that sandwiches the HBT with the substrate. Alternatively, the emitter electrode is a backside via that penetrates the substrate, and the heat sink is a metal layer, disposed on the substrate opposite the HBT.

Abstract: A semiconductor including a leadframe having a die attach paddle and a number of leads is provided. The die attach paddle has a recess to provide a number of mold dams around the periphery of the die attach paddle. An integrated circuit is positioned in the recess. Electrical connections between the integrated circuit and the number of leads are made, and an encapsulant is formed over the integrated circuit and around the number of mold dams.

Abstract: A semiconductor device has a leadframe with a structure made of a base metal (105), wherein the structure consists of a chip mount pad (302) and a plurality of lead segments (303). Covering the base metal are, consecutively, a continuous nickel layer (201) on the base metal, a layer of palladium on the nickel, wherein the palladium layer (203) on the chip side of the structure is thicker than the palladium layer (202) opposite the chip, and a gold layer (204) on the palladium layer (202) opposite the chip. A semiconductor chip (310) is attached to the chip mount pad and conductive connections (312) span from the chip to the lead segments. Polymeric encapsulation compound (320) covers the chip, the connections, and portions of the lead segments, but leaves other segment portions available for solder reflow attachment to external parts.

Abstract: A method of fabricating a semiconductor device includes hardening resin at a temperature that is less than or equal to the boiling point of the resin and until the hardening reaction ratio of the resin has reached at least 80%, the resin being disposed between a wiring board which has an interconnecting pattern and a semiconductor chip which has a plurality of electrodes and which is mounted on the wiring board in such a manner that the electrodes are in contact with the interconnecting pattern. A eutectic alloy joint is then formed between the electrodes and the interconnecting pattern.

Abstract: A programmable package with a fuse embedded therein, and fabrication method are provided. The fuse has first and second terminal ends joined by a central portion defining a fusible link. The ends include a portion of the first and second conductive layers, the central portion including a portion of the first conductive layer. The first layer may be electroless copper and the second layer may be electrolytic copper. The fuse may have a dog-bone or a bow tie shape. The method includes providing a substrate with a dielectric layer, and forming the fuse by depositing first conductive layer, forming and patterning second conductive layer over a portion of the first layer, and patterning first layer to form interconnects between areas of the second layer.

Abstract: A resin material having low dielectric constant is used as an inter-layer insulating film and its bottom surface is contacted with a silicon oxide film across the whole surface thereof. Thereby, the surface may be flattened and capacity produced between a thin film transistor and an pixel electrode may be reduced. Further, it allows to avoid a problem that impurity ions and moisture infiltrate into the lower surface of the resin material, thus degrading the reliability of whole semiconductor device.

Abstract: A thin film transistor array substrate includes a gate pattern on a substrate. The gate pattern includes a gate electrode, a gate line connected to the gate electrode, and a lower gate pad electrode connected to the gate line. A source/drain pattern includes a source electrode and a drain electrode, a data line connected to the source electrode, and a lower data pad electrode connected to the data line. A semiconductor pattern is formed beneath the source/drain pattern. A transparent electrode pattern includes a pixel electrode connected to the drain electrode, an upper gate pad electrode connected to the lower gate pad electrode, and an upper data pad electrode connected to the lower data pad electrode. The thin film array substrate further includes a gate insulating pattern and a passivation film pattern stacked at remaining areas excluding areas within which the transparent electrode pattern is formed.

Abstract: A method of fabricating a silicon-germanium CMOS includes preparing a silicon substrate wafer; depositing an insulating layer on the silicon substrate wafer; patterning and etching the insulating layer; depositing a layer of polycrystalline germanium on the insulating layer and on at least a portion of the silicon substrate wafer; patterning and etching the polycrystalline germanium; encapsulating the polycrystalline germanium with an insulating material; rapidly thermally annealing the wafer at a temperature sufficient to melt the polycrystalline germanium; cooling the wafer to promote liquid phase epitaxy of the polycrystalline germanium, thereby forming a single crystal germanium layer; and completing the CMOS device.

Abstract: A fabrication method of a TFT includes successively forming four thin films containing a first conductive layer, an insulation layer, a semiconductor layer, and a second conductive layer on a substrate, performing a first PEP process to pattern the four thin films for forming a semiconductor island and a gate electrode with the semiconductor layer and the first conductive layer respectively. Then, a laser ablation process is performed to define a channel pattern in the four thin films and remove a portion of the second conductive layer so that unconnected source electrode and drain electrode are formed with the second conductive layer.

Abstract: A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a formation of the device in masking insulators, and then transferring this formation through several etching steps into the SOI layer. The segmented field effect device combines FinFET, or fully depleted silicon-on-insulator FETs, type devices with fully depleted planar devices. This combination allows device width control with FinFET type devices. The segmented field effect device gives high current drive for a given layout area. The segmented field effect devices allow for the fabrication of high performance processors.

Abstract: Methods of forming T-gate structures on a substrate are provided that use only UV-sensitive photoresists. Such methods provide T-gate structures using two lithographic steps using a single wavelength of radiation.

Abstract: A method of fabricating a gate of a fin type transistor includes forming hard masks to define active regions of a substrate. A shallow trench isolation method is performed to form a first device separation layer, and then an etch-back process is performed such that the active regions protrude. Sidewall protection layers are formed on sidewalls of the active region, and a second device separation layer is formed thereon, thereby obtaining a device isolation region. The sidewall protection layers include an insulation material with an etch selectivity with respect to an insulation material composing the device isolation region. The device isolation region is selectively etched to form recesses for a fin type active region. Dry etching and wet etching are performed on the silicon nitride to remove the hard masks and the sidewall protection layers, respectively. Gates are formed to fill the recesses.

Abstract: In a CMOS image sensor manufacturing process, heavily doped p type impurity ions (for example, B) are implanted in a dummy moat region when the heavily doped p type impurity ions is implanted in a PMOS transistor region, so that metal ion contamination is removed. Accordingly, a CMOS image sensor capable of reducing a leakage current by gettering metal ion contamination is provided.