Abstract: Apparatus and assemblies for a borehole survey instrument are provided. A radiation detector includes a photo-detector, and a scintillator optically coupled to the photo-detector wherein the scintillator is formed in at least one of a cylindrical segment shape and a truncated frustocylindrical shape.

Abstract: Systems, methods and apparatus including an electrical penetration assembly for coupling a plurality of photo-multiplier tubes (PMTs) inside of a tub enclosure of a nuclear detector with an acquisition electronics system (AES) outside of the tub enclosure. The electrical penetration assembly may include at least one flex circuit, a plurality of flex circuit-PMT connectors, at least one flex circuit-AES connector, a flex circuit guide, a tub-penetration mechanical support, a support-to-tub retention mechanism, and a light seal.

Abstract: A method and apparatus satisfying growing demands for improving the intensity of implanting ions that impact a semiconductor wafer as it passes under an ion beam. The method and apparatus are directed to the design and combination together of novel magnetic ion-optical transport elements for implantation purposes for combating the disruptive effects of ion-beam induced space-charge forces. The design of the novel optical elements makes possible: (1) Focusing of a ribbon ion beam as the beam passes through uniform or non-uniform magnetic fields; (2) Reduction of the losses of ions comprising a d.c. ribbon beam to the magnetic poles when a ribbon beam is deflected by a magnetic field.

Abstract: A cryogenic variable temperature scanning tunneling microscope of novel design and component configuration, for use in conjunction with a variety of low temperature methodologies.

Abstract: A method for providing an operable filter system for filtering particles out of a beam of radiation in lithography is disclosed. The method includes providing a slack foil or wire for intercepting the particles, mounting at least a first point or side of the foil or wire to a first position of a mounting assembly, and substantially stretching the slack foil or wire at least within the beam of radiation, substantially parallel to a direction in which the radiation propagates.

Abstract: An apparatus for performing automated in-situ lift-out of a sample from a specimen includes a computer having a memory with computer-readable instructions, a stage for a specimen and a nano-manipulator. The stage and the nano-manipulator are controlled by motion controllers connected to the computer. The nano-manipulator has a probe tip for attachment to samples excised from the specimen. The computer-readable instructions include instructions to cause the stage motion controllers and the nano-manipulator motion controllers, as well as an ion-beam source, to automatically perform in-situ lift-out of a sample from the specimen.

Abstract: The invention is directed to an arrangement for generating EUV radiation based on a gas discharge plasma with high radiation emission in the range between 12 nm and 14 nm. It is the object of the invention to find a novel possibility for plasma-based radiation generation with high radiation output in the EUV spectral region (between 12 nm and 14 nm) which makes it possible to use tin as a work medium in EUV gas discharge sources for industrial applications. This object is met, according to the invention, in that a gas preparation unit is provided for defined control of the temperature and pressure of a tin-containing work medium and the flow thereof into the vacuum chamber in gaseous state. At least one thermally insulated reservoir vessel and a thermally insulated supply line are provided for transferring the gaseous tin-containing work medium from the gas preparation unit to the pre-ionization unit located inside the electrode housing.

Abstract: A radio-pharmaceutical transport system includes a pig and a disposable plastic insert. Together, the pig and the disposable plastic insert provide a mechanism for transporting a syringe containing a dose of a radio-pharmaceutical composition. The pig includes a tungsten cylinder that defines an elongated cavity therein that is substantially coaxial with the tungsten cylinder. The cavity is of sufficient size to receive therein a syringe. The tungsten cylinder has a thickness sufficient to shield users from a PET radio-pharmaceutical without requiring additional shielding. The disposable plastic insert is disposed within the cavity and includes an elongated plastic envelope.

Abstract: The present invention relates to a Drop Counter for counting a succession of falling liquid drops. The Drop Counter includes a light emitting diode for providing a light beam directed to a falling liquid drop. A photo diode sensor is positioned in side-by-side relation with the light emitting diode and detects reflected light from the falling liquid drop. The photo diode sensor provides an output signal when reflected light is detected and further includes a counter for receiving the output signal and counting the number of times the output signals are received.

Abstract: An image detection and readout apparatus constituted by a solid state detector constructed to generate electrical currents according to the electrostatic latent image when scanned by readout light, a surface light source for scanning the solid state radiation detector by the readout light, and a light source control means for controlling the surface light source. The stripe electrode of the solid state detector is divided into two sections at the center in the length direction of the elements of the stripe electrode to form two readout regions in order to reduce the capacitance component between the adjacent elements, as well as the resistance component of the elements. In addition, the light source control means is configured to control the surface light source to cause the scanning to be performed by the surface light source in parallel simultaneously for the readout regions.

Abstract: The present invention relates to a switching device to be irreversibly switched from an electrically isolating off-state into an electrically conducting on-state for use in a configurable interconnect, comprising two separate electrodes, at least one of which being a reactive metal electrode, and a solid state electrolyte arranged between said electrodes and being capable of electrolyte isolating said electrodes to define said off-state, said electrodes and said solid state electrolyte forming a redox-system having a mini-mum voltage (“turn-on voltage”) to start a redox reaction, the redox reaction resulting in the generation of metal ions to be released into said solid state electrolyte, the metal ions being reduced to increase a metal concentration within said solid state electrolyte, wherein an increase of said metal concentration results in a conductive metallic connection bridging the electrodes to define the on-state.

Abstract: A memory device comprising a first pan-shaped electrode having a side wall with a top side, a second pan-shaped electrode having a side wall with a top side and an insulating wall between the first side wall and the second side wall. The insulating wall has a thickness between the first and second side walls near the respective top sides. A bridge of memory material crosses the insulating wall, and defines an inter-electrode path between the first and second electrodes across the insulating wall. An array of such memory cells is provided. The bridges of memory material have sub-lithographic dimensions.

Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

Abstract: The disclosed embodiments relate to a vertical tunneling transistor that may include a channel disposed on a substrate. A quantum dot may be disposed so that an axis through the channel and the quantum dot is substantially perpendicular to the substrate. A gate may be disposed so that an axis through the channel, the quantum dot and the gate is substantially perpendicular to the substrate.

Abstract: A ballistic semiconductor device of the present invention comprises a n-type emitter layer (102), a base layer (305) made of n-type InGaN, a n-type collector layer (307), an emitter barrier layer (103) interposed between the emitter layer (102) and the base layer (305) and having a band gap larger than that of the base layer (305), and a collector barrier layer (306) interposed between the base layer (305) and the collector layer (307) and having a band gap larger than that of the base layer (305), and operates at 10 GHz or higher.

Abstract: Electronic devices, such as those having a flexible substrate and printed material on the flexible substrate. In one embodiment, the printed material and substrate are part of an electronic device having at least three terminals, wherein the electronic device has a charge carrier mobility of at least 10 cm2/V-s. Multi-terminal devices can have a substrate including a doped semiconductor layer and at least two doped regions formed upon the substrate. The doped regions can be doped oppositely from the semiconductor layer and exhibit a charge carrier mobility of greater than 10 cm2/V-s. Methods for making the same are also disclosed.

Abstract: The present invention provides a transparent substance formed with a plurality of continuous half-spherical convexes having a diameter of 25˜1,000 nm on its first main surface; an organic light-emitting device comprising a substrate, a first electrode, an organic material layer(s) and a second electrode, sequentially, characterized by having a plurality of continuous half-spherical convexes having a diameter of 25˜1,000 nm on the underside of the substrate that does not contact the first electrode and/or the upside of the second electrode that does not contact the organic material layer; and a method for preparing same using a porous aluminum oxide layer forming process.

Abstract: Provided are a poly crystalline silicon semiconductor device and a method of fabricating the same. Portions of a silicon layer except for gates are removed to reduce a parasitic capacitance caused from the silicon layer existing on gate bus lines. The silicon layer exists under the gates only, thus the parasitic capacitance is reduced and the deterioration and the delay of signals are prevented. Accordingly, the poly crystalline silicon semiconductor device, such as a thin film transistor, has excellent electric characteristics.

Abstract: A TFT is manufactured using at least five photomasks in a conventional liquid crystal display device, and therefore the manufacturing cost is high. By performing the formation of the pixel electrode 127, the source region 123 and the drain region 124 by using three photomasks in three photolithography steps, a liquid crystal display device prepared with a pixel TFT portion, having a reverse stagger type n-channel TFT, and a storage capacitor can be realized.

Abstract: Disclosed herein is a semiconductor device with high reliability which has TFT of adequate structure arranged according to the circuit performance required. The semiconductor has the driving circuit and the pixel portion on the same substrate. It is characterized in that the storage capacitance is formed between the first electrode formed on the same layer as the light blocking film and the second electrode formed from a semiconductor film of the same composition as the drain region, and the first base insulating film is removed at the part of the storage capacitance so that the second base insulating film is used as the dielectric of the storage capacitance. This structure provides a large storage capacitance in a small area.

Abstract: Silicon carbide high voltage semiconductor devices and methods of fabricating such devices are provided. The devices include a voltage blocking substrate. Insulated gate bipolar transistors are provided that have a voltage blocking substrate. Planar and beveled edge termination may be provided.

Abstract: The invention proposes a housing for at least two radiation-emitting components, particularly LEDs, comprising a system carrier (1) and a reflector arrangement (2) disposed on said system carrier (1), the reflector arrangement comprising a number of reflectors each of which serves to receive at least one radiation-emitting component and which are fastened to one another by means of a holding device (4).

Abstract: The invention provides an LED package and a backlight device incorporating the LED lens. The LED package has a bottom surface and a light exiting surface cylindrically extended around a central axis of the package from the bottom surface. Also, a reflecting surface is positioned on an opposite side of the bottom surface and symmetrical around the central axis such that light incident from the bottom surface is reflected toward the light exiting surface. Further, a scattering area is formed on the reflecting surface. According to the invention, by applying scattering materials on the reflecting surface of the LED package, a reflecting paper does not need to be attached, thereby simplifying a process and reducing the manufacture time and cost.

Abstract: A method of fabricating a light emitting diode (LED) includes providing an LED chip that emits light having a first wavelength where the LED chip includes a first electrical contact and a second electrical contact. The method further includes forming a tinted thin film layer over the LED chip where the tinted thin film layer interacts with the first wavelength light to produce a light having a second wavelength.

Abstract: Disclosed is a method for manufacturing a nitrogen-containing fluorescent substance comprising accommodating an oxide fluorescent substance containing two or more elements in a receptacle made of a material containing carbon, and sintering the oxide fluorescent substance in a mixed gas atmosphere containing nitrogen gas.

Abstract: A two-dimensional silicon controlled rectifier (2DSCR) having the anode and cathode forming a checkerboard pattern. Such a pattern maximizes the anode to cathode contact length (the active area) within a given SCR area, i.e., effectively increasing the SCR width. Increasing the physical SCR area, increases the current handling capabilities of the SCR.

Abstract: The present invention relates to use of selective oxidation to oxidize silicon in the presence of tungsten and/or tungsten nitride in memory cells and memory arrays. This technique is especially useful in monolithic three dimensional memory arrays. In one aspect of the invention, the silicon of a diode-antifuse memory cell is selectively oxidized to repair etch damage and reduce leakage, while exposed tungsten of adjacent conductors and tungsten nitride of a barrier layer are not oxidized. In some embodiments, selective oxidation may be useful for gap fill. In another aspect of the invention, TFT arrays made up of charge storage memory cells comprising a polysilicon/tungsten nitride/tungsten gate can be subjected to selective oxidation to passivate the gate polysilicon and reduce leakage.

Abstract: Multilevel metallization layouts for an integrated circuit chip including transistors having first, second and third elements to which metallization layouts connect. The layouts minimize current limiting mechanism including electromigration by positioning the connection for the second contact vertically from the chip, overlapping the planes and fingers of the metallization layouts to the first and second elements and forming a pyramid or staircase of multilevel metallization layers to smooth diagonal current flow.

Abstract: A solid-state image pickup device includes a semiconductor substrate, a photosensitive pixel which converts incident light on the semiconductor substrate into a signal charge, and a charge detection section which converts the converted signal charge into an output signal. The device further includes a charge transfer section which is disposed between the photosensitive pixel and the charge detection section and which temporarily stores the signal charge and which transfers the stored signal charge to the charge detection section by application of sequential pulses.

Abstract: A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of raised bitlines, where the bitlines have a lower portion formed by a first process and an upper portion formed by a second process.

Abstract: The semiconductor device comprises a semiconductor substrate 10 with a trench 16a and a trench 16b formed in; a device isolation film 32a buried in the trench 16a and including a liner film including a silicon nitride film 20 and an insulating film 28 of a silicon oxide-based insulating material; a device isolation film 32b buried in the bottom of the trench 16b; and a capacitor formed on a side wall of an upper part of the second trench 16b and including an impurity diffused region 40 as a first electrode, a capacitor dielectric film 43 of a silicon oxide-based insulating film and a second electrode 46.

Abstract: Semiconductor devices with an improved overlay margin and methods of manufacturing the same are provided. In one aspect, a method includes forming a buried bit line in a substrate; forming an isolation layer in the substrate to define an active region, the isolation layer being parallel to the bit line without overlapping the bit line; and forming a gate line including a gate pattern and a conductive line by forming the gate pattern in the active region and forming a conductive line that extends at a right angle to the bit line across the active region and is electrically connected to the gate pattern disposed thereunder. The gate pattern and the conductive line can be integrally formed.

Abstract: A memory structure that combines multiple embedded flash memory. The flash memory can be used, e.g., as air replacement cells or back up memory, or additional memory cells. In one aspect, the flash memory cells are stacked on top of the flash memory cells and the flash memory cells share a gate layer. In another aspect, pairs of stacked flash memory cells are stacked on top of each other with each pair isolated by an isolation oxide. In another aspect, pairs of stacked flash memory cells are stacked on top of each other in an un-isolated configuration.

Abstract: A flash memory cell and a method of forming the same are described. The flash memory cell may include a substrate having a source and a drain, a gate element, and a dielectric layer between the substrate and the gate element. The dielectric layer includes a dielectric material having a dielectric constant that is greater than that of silicon dioxide.

Abstract: A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion layer that serves as a bit-line, so that no implantation is required to form the bit-line.

Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.

Abstract: A nonvolatile semiconductor memory includes a trench isolation provided in a semiconductor substrate and an interlayer insulator provided on the semiconductor substrate. The trench isolation defines an active area extending in a first direction at the semiconductor substrate. The interlayer insulator has a wiring trench extending in a second direction intersecting the first direction. A first conductive material layer is provided at the cross-point of the active area and the wiring trench so that it is insulated from the active area. A second conductive material layer is provided in the wiring trench so that it is insulated from the first conductive material layer. A metal layer is provided in the wiring trench so that it is electrically in contact the second conductive material layer.

Abstract: A nonvolatile semiconductor memory device includes a first insulating film provided on a surface of a semiconductor substrate, a charge accumulation layer provided on the first insulating film, a second insulating film provided above the charge accumulation layer and contains silicon and nitrogen, a third insulating film provided on the second insulating film, and composed of a single-layer insulating film containing oxygen or a plural-layer stacked insulating film at least whose films on a top layer and a bottom layer contain oxygen, relative dielectric constant thereof being larger than it of a silicon oxide film, a fourth insulating film provided on the third insulating film and contains silicon and nitrogen, a control gate provided above the fourth insulating film, and a fifth insulating film provided between the charge accumulation layer and the second insulating film or between the fourth insulating film and the control gate, and contains silicon and oxygen.

Abstract: A trench transistor having a semiconductor body, in which a trench structure and an electrode structure embedded in the trench structure is disclosed. The electrode structure is electrically insulated from the semiconductor body by an insulation structure. The electrode structure has a gate electrode structure and a field electrode structure arranged below the gate electrode structure and electrically insulated from the latter. There is provided between the gate electrode structure and the field electrode structure a shielding structure for reducing the capacitive coupling between the gate electrode structure and the field electrode structure.

Abstract: A semiconductor device includes one or more LDMOS transistors and one of more SCR-LDMOS transistors. Each LDMOS transistor includes a LDMOS well of a first conductivity type, a LDMOS source region of a second conductivity type formed in the LDMOS well, and a LDMOS drain region of a second conductivity type separated from the LDMOS well by a LDMOS drift region of the second conductivity type. Each SCR-LDMOS transistor comprising a SCR-LDMOS well of the first conductivity type, a SCR-LDMOS source region of the second conductivity type formed in the SCR-LDMOS well, a SCR-LDMOS drain region of a second conductivity type, and a anode region of the first conductivity type between the SCR-LDMOS drain region and the SCR-LDMOS drift region. The anode region is separated from the SCR-LDMOS well by a SCR-LDMOS drift region of the second conductivity type.

Abstract: A semiconductor integrated circuit having a high withstand voltage TFT and a TFT which is capable of operating at high speed in a circuit of thin film transistors (TFT) and methods for fabricating such circuit will be provided. A gate insulating film of the TFT required to operate at high speed (e.g., TFT used for a logic circuit) is relatively thinned less than a gate insulating film of the TFT which is required to have high withstand voltage (e.g., TFT used for switching high voltage signals).

Abstract: The present invention is directed to an SOI device with charging protection and methods of making the same. In one illustrative embodiment, a device is formed on an SOI substrate including a bulk substrate, a buried insulation layer and an active layer. The device includes a transistor formed in an isolated portion of the active layer, the transistor including a gate electrode and a source region. The device further includes a first conductive bulk substrate contact extending through the active layer and the buried insulation layer, the first conductive bulk substrate contact being conductively coupled to the source region and the bulk substrate, and a second conductive bulk substrate contact extending through the active layer and the buried insulation layer, the second conductive bulk substrate being conductively coupled to the gate electrode and the bulk substrate.

Abstract: A double gate transistor comprises a substrate (105, 905) and first and second electrically insulating layers (110, 910), (120, 920). The first and second electrically insulating layers form a fin (130, 930). A first gate dielectric (140,940) is at a first side (131, 931) of the fin and a second gate dielectric (150, 950) is at a second side (132, 932) of the fin. A first metal region (160, 960) is adjacent to the first gate dielectric and has a first surface (161, 961), and a second metal region (170, 970) is adjacent to the second gate dielectric and has a second surface (171, 971). The first electrically insulating layer has a third surface (111, 911), the second electrically insulating layer has a fourth surface (121, 921), and the first surface and the second surface lie between the third and fourth surfaces.

Abstract: A method includes the steps of: implanting boron into a surface region of a silicon substrate to form a p+ diffused region; implanting indium into the surface of the p+ diffused region, to form an indium-implanted layer; forming a contact metal layer on the indium-implanted layer; and reacting silicon in the silicon substrate including the indium-implanted layer with metal in the contact metal layer to form a titanium silicide layer.

Abstract: A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall spacers on the gate electrode, heavily doping a first active region with phosphorus and a second active region and the resistive element with p-type impurities by ion implantation, forming salicide block at 500° C. or lower, depositing a metal layer covering the salicide block, and selectively forming metal silicide layers. The method may further includes, forming a thick and a thin gate insulating films, and performing implantation of ions of a first conductivity type not penetrating the thick gate insulating film and oblique implantation of ions of the opposite conductivity type penetrating also the thick gate insulating film before the formation of side wall spacers.

Abstract: A semiconductor device has an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p channel conductivity type field effect transistor having a channel formation region formed in a second region on the main surface of the semiconductor substrate, which second region is different from the first region. An internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is different from an internal stress generated in the channel formation region of the p channel conductivity type field effect transistor. The internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is a tensile stress, while the internal stress generated in the channel formation region of the p channel conductivity type field effect transistor is a compressive stress.

Abstract: A plurality of quantum dots each have a shell. The quantum dots are embedded in an organic matrix. At least the quantum dots and the organic matrix are photoconductive semiconductors. The shell of each quantum dot is arranged as a tunneling barrier to require a charge carrier (an electron or a hole) at a base of the tunneling barrier in the organic matrix to perform quantum mechanical tunneling to reach the respective quantum dot. A first quantum state in each quantum dot is between a lowest unoccupied molecular orbital (LUMO) and a highest occupied molecular orbital (HOMO) of the organic matrix. Wave functions of the first quantum state of the plurality of quantum dots may overlap to form an intermediate band.

Abstract: A transistor in which a physical property of its channel is changed according to an applied voltage, and methods of manufacturing and operating the same are provided. The transistor may include a first conductive layer on a substrate, a phase change layer and a second conductive layer which are sequentially stacked on the first conductive layer, a first current direction limiting unit and a second current direction limiting unit formed on the second conductive layer by being separated within a space, a third conductive layer and a fourth conductive layer formed on the first current direction limiting unit and the second current direction limiting unit, respectively, a word line connected to the third conductive layer, a bit line connected to the fourth conductive layer, and a voltage lowering unit connected to the word line.

Abstract: The present invention provides method of manufacturing a metal-insulator-metal capacitor (100). A method of manufacturing includes depositing a first refractory metal layer (105) over a semiconductor substrate (110). The first refractory metal layer (105) over a capacitor region (200) of the semiconductor substrate (110) is removed and a second refractory metal (300) is deposited over the capacitor region (200). Other aspects of the present invention include a metal-insulator-metal capacitor (900) and a method of manufacturing an integrated circuit (1000).

Abstract: The invention includes methods of forming rugged electrically conductive surfaces. In one method, a layer is formed across a substrate and subsequently at least partially dissociated to form gaps extending to the substrate. An electrically conductive surface is formed to extend across the at least partially dissociated layer and within the gaps. The electrically conductive surface has a rugged topography imparted by the at least partially dissociated layer and the gaps. The topographically rugged surface can be incorporated into capacitor constructions. The capacitor constructions can be incorporated into DRAM cells, and such DRAM cells can be incorporated into electrical systems.