Abstract: A power distribution module for a personal recreational vehicle includes a housing and a cover. The housing defines an interior and includes a wall having an array of receptacle openings. The receptacle openings are adapted to receive and secure electrical components inside the housing. A distribution harness includes a plurality of electrical conductors and is coupled to the housing wherein the electrical conductors are in electrical communication with the electrical components inside the housing. The power distribution module can optionally include a decal to assist quick and accurate placement of the electrical components during the manufacturing process. A method for producing a personal recreational vehicle having a standardized housing over a range of models. The housing includes a component arrangement guide for locating and installing electrical components.

Abstract: A bi-directional boost circuit for power factor correction includes a power factor control circuit and a pair of diodes, a pair of inductors, and a pair of switches. A first diode, a second diode, a first inductor, a second inductor, a first switch, and a second switch convert the AC input voltage, rectify the AC input voltage, and output an intermediate DC voltage. The power factor control circuit receives the AC input voltage and receives the intermediate DC voltage. The power factor control circuit regulates the DC output voltage. Based on the AC input voltage and the intermediate DC output voltage, the power factor control circuit controls an inductor current waveform by driving the first switch and the second switch to create a substantially sinusoidal current as seen by the power source that is in phase with the AC input voltage.

Abstract: A method of designing a random pulse width modulation (RPWM) inverter with unwanted harmonic elimination, which first uses a Fourier analysis and a numerical analysis to eliminate the unwanted harmonic components, next uses the equal area approach to produce switching angles to be used as start values for solving non-linear equations, next selects low-order harmonics to be eliminated and randomly sampled harmonics to solve the equations and obtain pluralities of switching angles for eliminating different harmonics, next applies pluralities of harmonics to a random probability function to thereby obtain a harmonic distribution, and finally uses a random sampling to evenly disperse the higher side-band harmonic components and effectively suppress the low-order harmonic components.

Abstract: A method and apparatus for adaptively configuring an array of voltage transformation modules is disclosed. The aggregate voltage transformation ratio of the adaptive array is adjusted to digitally regulate the output voltage for a wide range of input voltages. An integrated adaptive array having a plurality of input cells, a plurality of output cells, or a plurality of both is also disclosed. The input and output cells may be adaptively configured to provide an adjustable transformer turns ratio for the adaptive array or in the case of an integrated VTM, an adjustable voltage transformation ratio for the integrated VTM. A controller is used to configure the cells and provide digital regulation of the output. A converter having input cells configured as a complementary pair, which are switched out of phase, reduces common mode current and noise. Series connected input cells are used for reducing primary switch voltage ratings in a converter and enabling increased operating frequency or efficiency.

Abstract: Parallel inverters without any communication buses and the controlling method thereof are provided. The parallel inverters are controlled by an instant voltage. Each inverter includes an output voltage waveform controller and a load-sharing controller. The output voltage waveform controller is connected to an output terminal of the inverter to control the waveform of an output voltage of the inverter. The load-sharing controller is connected to the output voltage waveform controller to control the load-sharing of the inverter and to make each inverter have the same phase, active power and reactive power without communications.

Abstract: There is disclosed a power converter having limited inrush current and an inrush current limiter circuit. The inrush limiting circuit may be a self-oscillating switching-mode average current regulator tp provide a relatively constant average charging current to a bulk capacitor until the bulk capacitor is fully charged. A bypass switch may be used to route current around the inrush current limiter circuit once the bulk capacitor is fully charged.

Abstract: The present invention provides an induction heating apparatus that can detect that a power factor correction circuit is in operation or in non-operation. The induction heating apparatus includes a power factor correction circuit that corrects a power factor of an inputted direct-current power supply by turning on and off a switching element connected to a choke coil, a booster circuit that boosts an output voltage of the power factor correction circuit by turning on and off a switching element connected to a choke coil, an inverter circuit that inputs the output voltage of the booster circuit to generate a high-frequency current in a heating coil by turning on and off a switching element, and an inverter circuit drive control unit that, in driving the power factor correction circuit, controls output of the inverter circuit such that an input current reaches a target value and detects the voltage in the booster circuit.

Abstract: Control methods and apparatus are disclosed for operating an inverter at resonant mode, where the inverter adapts its frequency to the resonant tank characteristics before a lamp is struck, and operates at fixed frequency after the lamp is struck. Disclosed embodiments combine the advantages of operation in fixed mode as well as the variable mode.

Abstract: A memory card module includes a first circuit board, and a second circuit board. On one surface of the first circuit board, there are flash memories and a controller. The second circuit board is installed at one end of the first circuit board and is electrically connected with the first circuit board so as to form a transmitting interface port. On a first surface of the second circuit board, there are a plurality of interface connecting points. On a second surface of the second circuit board, part of the second surface is hollowed out. A space formed between the hollowed out area and the corresponding first circuit board increases the area for circuit layouts and the mounting components for the first circuit board. Therefore, quantity of accommodated memory components may be increased so as to increase the total storage capacity of the memory card under limitation of small dimensions.

Abstract: Embodiments of the invention provide a semiconductor chip and a semiconductor chip package comprising a semiconductor chip. In one embodiment, the invention provides a semiconductor chip comprising a memory cell array, a control circuit, and a chip selection signal generating circuit electrically connected to first and second option pads. In the semiconductor chip, the chip selection signal generating circuit is enabled in accordance with a dual chip enable signal, and the control circuit is enabled and disabled in accordance with the chip selection signal received from the chip selection signal generating circuit. In addition, the chip selection signal generating circuit is adapted to generate a chip selection signal in accordance with signals received through the first and second option pads, respectively.

Abstract: A semiconductor storage array has a first array portion on a first plane of circuitry and a second array portion on a second plane of circuitry. A composite bit line and/or a composite word line is divided and arranged to have a first portion on the first array portion and a second portion on the second array portion. The two portions of the composite word line or the composite bit line are on different planes of circuitry, and three-dimensional interconnections connect proximal ends of the word line portions, or proximal ends of the bit line portions. A word line driver drives the word line portions in parallel. A bit line driver drives the bit line portions in parallel. Signal propagation times down the composite word or bit lines are significantly less than signal propagation times down corresponding undivided word or bit lines.

Abstract: A memory capable of suppressing disturbance causing disappearance of data in a nonselected memory cell is provided. This memory comprises a memory cell array including a bit line, a word line arranged to intersect with the bit line and memory cells connected between the bit line and the word line, for accessing a selected memory cell thereby deteriorating a remanent polarization in an arbitrary memory cell and thereafter performing recovery for recovering all memory cells to remanent polarizations immediately after a write operation or remanent polarizations subjected to single application of a voltage applied to a nonselected memory cell in the access.

Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

Abstract: The present invention relates generally to an integrated circuit (IC) design, and more particularly to a method and apparatus for providing an SRAM cell with improved read and write margins. The method includes providing a first negative voltage to a bit-line and a supply voltage to an inverse bit-line to increase a first potential difference between the bit-line and the inverse bit-line during a write operation of a logic “0.” The method also includes providing the first negative voltage to the inverse bit-line and the supply voltage to the bit-line to increase the first potential difference during a write operation of a data “1.

Abstract: A memory cell for interconnection with READ and WRITE word lines and READ and WRITE bit lines includes a logical storage element such as a flip-flop formed by a first inverter and a second inverter cross-coupled to the first inverter. The storage element has first and second terminals and a storage element supply voltage terminal configured for interconnection with a first supply voltage. A WRITE access device is configured to selectively interconnect the first terminal to the WRITE bit line under control of the WRITE word line, and a pair of series READ access devices are configured to ground the READ bit line when the READ word line is active and the second terminal is at a high logical level. A logical “one” can be written to the storage element when a second supply voltage, greater than the first supply voltage, is applied to the WRITE word line, substantially without the use of a complementary WRITE bit line.

Abstract: A method for writing a memory cell of a magnetoresistive random access memory (MRAM) device includes, sequentially, providing a first magnetic field in a first direction, providing a second magnetic field in a second direction substantially perpendicular to the first direction, turning off the first magnetic field, providing a third magnetic field in a third direction opposite to the first direction, turning off the second magnetic field, and turning off the third magnetic field. A method for switching magnetic moments in an MRAM memory cell includes providing a magnetic field in a direction forming a blunt angle with a direction of a bias magnetic field. A method for reading an MRAM device includes partially switching magnetic moments in a reference memory cell to generate a reference current; measuring a read current through a memory cell to be read; and comparing the read current with the reference current.

Abstract: To improve the reliability of the phase change element, unwanted current should not be flown into the element. Therefore, an object of the present invention is to provide a memory cell that stores information depending on a change in its state caused by applied heat, as well as an input/output circuit, and to turn off the word line until the power supply circuit is activated. According to the present invention, unwanted current flow to the element can be prevented and thereby data destruction can be prevented.

Abstract: A magnetization reversal method is disclosed in which an external magnetic field is applied to a magnetoresistive film requiring a strong magnetic film for reversal. A weak magnetic field is applied when magnetically coupled perpendicular magnetic films are used in which the magnetoresistive film has a structure wherein a nonmagnetic film is placed between magnetic films with an easy axis of magnetization along a perpendicular direction to a film plane, and in which said external magnetic field is comprised of magnetic fields from a plurality of directions including a direction of easy magnetization of the magnetic films.

Abstract: A semiconductor device comprises an N-type insulated-gate field-effect transistor including a first insulating layer that is provided along side walls of a gate electrode, has a negative thermal expansion coefficient, and applies a tensile stress to a channel region of the N-type insulated-gate field-effect transistor. The device also comprises a P-type insulated-gate field-effect transistor including a second insulating layer that is provided along side walls of a gate electrode, has a positive thermal expansion coefficient, and applies a compression stress to a channel region of the P-type insulated-gate field-effect transistor.

Abstract: A memory device and a method of operating a memory device is disclosed. In one embodiment of the invention, the memory device includes a plurality of multi-level memory cells each having a number m of levels not matching 2n with n being a non-zero integer, and a circuit or device for combining the levels of at least two of the memory cells for write and read operations into a set of combined states and for transforming at least a subset of 2n combinations of the set of combined states into n two-level data bits.

Abstract: A storage transistor is programmed as a non-volatile memory element by biasing the source and drain while a programming voltage is applied to the gate. The substrate is held at a different potential than the source/drain to insure that the greatest difference in voltage during the programming step occurs between the channel region and the gate, rather than the gate and the source/drain. The programming voltage heats the channel region to form a non-volatile low-resistance connection between the source and drain, which is read to determine the programmed state.

Abstract: A non-volatile semiconductor memory device including a NAND cell unit with a plurality of electrically rewritable and non-volatile memory cells connected in series, a source line coupled to one end of the NAND cell unit, and a bit line coupled to the other end of the NAND cell unit, wherein the NAND cell unit is biased in a data write mode as follows: a write voltage Vpgm is applied to a control gate of a selected memory cell in the NAND cell unit; a channel-isolating voltage is applied to control gates of non-selected memory cells disposed on the source line side of the selected memory cell at intervals of a certain number of memory cells; and a write medium voltage Vm lower than Vpgm is applied to control gates of the remaining non-selected memory cells.

Abstract: A memory cell array with a group of memory cells capable of retaining two-bit information. Each memory cell has a pair of transistors having charge storage regions, mutually connected gates, and mutually connected sources. Word lines are provided to the gates of the transistors. Bit lines are provided to the sources and drains of the transistors. A pair of the bit lines respectively connected to the drains of a pair of transistors included in a memory cell are connected to a comparison input terminal of the differential detector. An information retained in the memory cell is read based on a comparison result of current amounts inputted to the differential detector via the pair of bit lines obtained by the differential detector in a state where memory cell currents are simultaneously and independently supplied to the pair of transistors.

Abstract: A memory device includes a set of memory cells, each of which is capable of being selected to generate a sensing current depending on a logic state thereof, and a set of reference cells, each of which is capable of being selected to generate a reference current. A sense amplifier is coupled to the memory cells and the reference cells for comparing the sensing current with the reference current to generate a signal representing the logic state of the selected memory cell. The memory cells and the reference cells are subject to the same operation cycles, such that a difference between the sensing current and the reference current remains a constant.

Abstract: In a non-volatile memory, the read parameter used to distinguish the data states characterized by a negative threshold voltage from the data states characterized by a positive threshold voltage is compensated for the memory's operating conditions, rather than being hardwired to ground. In an exemplary embodiment, the read parameter for the data state with the lowest threshold value above ground is temperature compensated to reflect the shifts of the storage element populations on either side of the read parameter. According to another aspect, an erase process is presented that can take advantage the operating condition compensated sensing parameter. As the sensing parameter is no longer fixed at a value corresponding to 0 volts, instead shifting according to operating conditions, a sufficient margin is provided for the various erase verify levels even at lowered operating voltages.

Abstract: A non-volatile memory device includes the ability to recover data in event of a program failure without having to maintain a copy of the data until the write is completed. As the integrity of the data can thus be maintained with having to save a copy, buffers can be freed up for other data or even eliminated, reducing the amount of controller space that needs to devoted data buffering. In exemplary embodiments, the data is recovered by logically combining the verify data for the (failed) write process maintained in data latches with the results of one or more read operations to reconstitute the data. The exemplary embodiments are for memory cells storing multi-state data, both in the format of independent upper page, lower page form, as well as in 2-bit form. This can be accomplished by a state machine and data latches in the sense amp area on the memory, without use of the controller.

Abstract: A method and a system for operating bits of memory cells in a memory array, the method including applying a first operating pulse to a terminal of a first cell, the first operating pulse is intended to place the first cell into a predefined state; and applying a second operating pulse to a terminal of a second cell in the set, the second operating pulse is intended to place the second cell to the predefined state, and the pulse characteristics of the second operating pulse are a function of the response of the first cell to the first operating pulse.

Abstract: A memory device distributed controller circuit distributes memory control functions amongst a plurality of memory controllers. A master controller receives an interpreted command and activates the appropriate slave controllers depending on the command. The slave controllers can include a data cache controller that is coupled to and controls the data cache and an analog controller that is coupled to and controls the analog voltage generation circuit. The respective controllers have appropriate software/firmware instructions that determine the response the respective controllers take in response to the received command.

Abstract: Improved circuitry and methods for programming memory cells of a memory device are disclosed. The improved circuitry and methods operate to isolate the memory cells from potentially damaging electrical energy that can be imposed during a precharge phase that precedes programming of the memory cells. Additionally, the improved circuitry and methods can operate to ensure that programming of the memory cells is performed in a controlled manner using only a program current. The improved circuitry and methods are particularly useful for programming non-volatile memory cells. In one embodiment, the memory device pertains to a semiconductor memory product, such as a semiconductor memory chip or a portable memory card.

Abstract: Improved circuitry and methods for programming memory cells of a memory device are disclosed. The improved circuitry and methods operate to isolate the memory cells from potentially damaging electrical energy that can be imposed during a precharge phase that precedes programming of the memory cells. Additionally, the improved circuitry and methods can operate to ensure that programming of the memory cells is performed in a controlled manner using only a program current. The improved circuitry and methods are particularly useful for programming non-volatile memory cells. In one embodiment, the memory device pertains to a semiconductor memory product, such as a semiconductor memory chip or a portable memory card.

Abstract: Disclosed is a non-volatile memory device and a method of programming the same. The non-volatile memory device comprises a plurality of memory cells that are programmed by supplying first and second program voltages thereto. In cases where the second program voltage rises above a predetermined detection voltage, the first program voltage is prevented from being supplied to the memory cell until the second program voltage falls below the detection voltage.

Abstract: A semiconductor storage device comprises a semiconductor layer; a plurality of memory cells formed on the semiconductor layer, data writing, erasing or reading with respect to each of the memory cells being possible based on a voltage applied to a control electrode and a voltage applied to the semiconductor layer; a first booster circuit supplying a voltage to control electrodes of selected memory cells into which data is to be written; and a second booster circuit supplying a voltage to control electrodes of inhibited memory cells into which data is not to be written, wherein when erasing data in the memory cells, a potential at the semiconductor layer is boosted in a first boosting mode in which a boosting capability of the first booster circuit is low and a boosting capability of the second booster circuit is high, and then the potential at the semiconductor layer is boosted in a second boosting mode in which the boosting capability of the second booster circuit is low and the boosting capability of the fi

Abstract: An improved SRAM cell and its operating method are disclosed. The SRAM cell comprises at least four original transistors, e.g., a pair of pass-gate transistors and a pair of pull-up transistors. The SRAM cell also comprises a pair of parasitic transistors formed by making contacts to a Pwell underneath a buried insulation layer to make the Pwell a gate terminal; hence the buried insulation layer serves as a gate insulation for the parasitic transistor.

Abstract: Reducing power consumption of a semiconductor memory device having a serial interface is disclosed. After parallel read-out data from a memory-cell matrix 14 are held in a data latch 17, the parallel read-out data are selected sequentially by a serial output selector 18 according to timing signals SL0-SL15 from a controller 20 and are outputted serially from an output buffer 19 as an output data DO. In an activating control unit 23, outputting an operation control signal AC to a gate-voltage generating unit 21, a drain-voltage generating unit 22, and a sense amplifier 16 is being halted during from when a timing signal SL0 is finished to when a timing SL10 is finished. Consequently, during the above mentioned period, the unnecessary operations of the gate-voltage generating unit 21, the drain-voltage generating unit 22, and the sense amplifier 16 are being halted and then the power consumption thereof can be reduced.

Abstract: Methods of generating a program voltage for programming a non-volatile memory device include generating an initial voltage and generating a first ramping voltage in response to the initial voltage. The first ramping voltage has a ramping speed slower than the ramping speed of the initial voltage. A second ramping voltage is generated in response to the first ramping voltage. The second ramping voltage has a lower ripple than the first ramping voltage. The second ramping voltage is output as a program voltage for programming a non-volatile memory device. A program voltage generating circuit includes a program voltage generating unit configured to generate an initial voltage, a ramping circuit configured to generate a first ramping voltage responsive to the initial voltage, and a voltage controlling unit configured to generate a second ramping voltage having relatively low ripple and to output the first ramping voltage or the second ramping voltage responsive to a voltage level of the first ramping voltage.

Abstract: The present invention provides a semiconductor integrated circuit device which includes at least an SRAM memory cell array comprising a plurality of memory cells each constituted of a circuit including load MOS transistors, drive MOS transistors and transfer MOS transistors, a substrate bias generating circuit which is electrically connected to the load MOS transistors and supplies a substrate potential to the load MOS transistors during at least operation and standby, and a source bias generating circuit which is electrically connected to the drive MOS transistors and supplies a source potential to the drive MOS transistors at standby. It is possible to reduce a leak current in an SRAM memory cell during both operation and standby and reduce current consumption.

Abstract: Methods and apparatus are provided for read/write control and bit selection with false read suppression in an SRAM. According to one aspect of the invention, a bit select circuit is provided for an SRAM. The disclosed bit select circuit includes one or more transistors controlled by a write control gate signal to prevent data from being read from one or more data cells during a write operation. The transistors can include, for example, a pair of gated transistors controlled by the write control gate signal. The write control gate signal prevents data from being read from one or more data cells while the write control gate signal is in a predefined state.

Abstract: The present invention provides a memory device comprising a memory array having a plurality of memory regions, and a plurality of data path access units, each data path access unit being associated with at least one memory region. Each memory region has at least one associated memory region selected such that the data path access unit used for that memory region is different to the data path access unit used for the at least one associated memory region. For each memory region, any redundant row used in place of a faulty row in that memory region is provided in the at least one associated memory region, and a storage is provided for maintaining a record identifying each faulty row and the redundant row to be used in place of that faulty row. On receipt of a read access request specifying a read address, a lookup operation is performed in both the memory region identified by that read address and the at least one associated memory region.

Abstract: First dummy memory cells connected to a first dummy signal line have the same shape and characteristics as those of a real memory cell. The first dummy memory cells are arranged to be adjacent to outermost real memory cells. A voltage setting circuit changes the voltage of the first dummy signal line from a first voltage to a second voltage in order to write test data onto the first dummy memory cell during a test mode. By writing data of a logic opposite to that of the test data onto the real memory cell adjacent to the first dummy memory cell by means of an operation control circuit, a leak failure that may occur between the first dummy memory cell and the real memory cell adjacent thereto can be checked.

Abstract: A semiconductor memory device includes first and second global data line pairs connected to a local data line pair, allowing a reduced pre-charge voltage that lowers current consumption and increases operating speed. Also included are a sense amplifier for amplifying data of the second global data line pair and outputting the amplified data to a data line, and a write driver for outputting data of the data line to the first global data line pair during a write operation. Switching circuits are connected between the first and second global data line pairs, and the local data line and the first global data line pairs. The memory device further includes a first global data line pre-charge circuit for pre-charging the first global data line pair to a first voltage level, and a second global data line pre-charge circuit for pre-charging the second global data line pair to a second voltage level.

Abstract: An inversion device includes a differential amplifier having first and second input lines, and a controller coupled to the first and second input lines to selectively and individually decouple the first and second input lines from the differential amplifier.

Abstract: A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating circuit. A control section is supplied with an output signal of the sense amplifier. When verifying the threshold voltage of the memory cell, the control section causes the voltage generating circuit to generate verify voltage which is the same as readout voltage generated at the time of data readout from the memory cell.

Abstract: Embodiments of the invention generally provide methods and apparatuses for updating a temperature measurement. In one embodiment, the temperature measurement is performed by a temperature sensor using one or more reference signals. A signal to update the temperature measurement is received. A determination is made of whether the clocked standby mode signal has changed within a period of time prior to receiving the signal to update the temperature measurement. If the clocked standby mode signal has changed within the period of time, the signal to update the temperature sensor is masked. If the clocked standby mode signal has not changed within the period of time, the temperature measurement is updated using the signal to update the temperature measurement.

Abstract: A pipe latch circuit for increasing data output speed, a semiconductor memory device with the pipe latch circuit and data output operation method of the same. The pipe latch circuit includes a selection signal generator and a pipe latch unit. The selection signal generator generates input selection signals in response to an input control signal and a first selection control signal. The pipe latch unit inverts pre-fetch data received in parallel through a plurality of GIO (Global Input and Output) lines into serial pipe output data in response to input selection signals, a second selection control signal and output control signals and then outputs them at an output node. The pipe latch unit includes an input selection unit for selectively changing a parallel order of pre-fetch data respectively received through a plurality of GIO lines in response to an input selection signals and then respectively outputting input selection data at a plurality of internal data lines in accordance with the change result.

Abstract: A system and method of providing a voltage to a non-volatile memory is disclosed. The system includes an output pin to provide an output voltage to a non-volatile memory. The system also includes a memory to store a table. The table includes a plurality of operating voltage levels. The system further includes a voltage mode module to apply a first voltage at a first of the plurality of operating voltage levels at the output pin.

Abstract: A method for operating a semiconductor memory device is disclosed. In one embodiment, the method includes activating a first memory cell sub-array or memory cells of the first memory cell sub-array that are contained in a first set of memory cells, in particular of memory cells positioned in one and the same row or column of the first memory cell sub-array, if one or a plurality of memory cells contained in the first memory cell sub-array or in the first set of memory cells is/are to be accessed. The corresponding memory cell or memory cells are accessed; including leaving the first memory cell sub-array or the memory cells of the first memory cell sub-array that are contained in the first set of memory cells in the activated state if one or a plurality of further memory cells is/are to be accessed which are contained in a second memory cell sub-array of the same memory cell array that comprises the first memory cell sub-array.

Abstract: Subarrays, which constitute a memory cell array, each include a bit line driving transistor having a drain connected to a bit line, a source is connected to an interconnection having a power supply potential, and a gate is connected to a sub-bit line. The plurality of memory cells are each provided in such away that a gate is connected to a word line, a source is grounded, and whether a drain is connected to the sub-bit line or not is selected in correspondence to data to be stored. Transmission transistors each have a gate connected to the bit line, a source connected to a loading transistor section, and a drain connected to the sub-bit line.

Abstract: The invention includes a memory device with a register device to which an output of a multiplexer is connected. The input of the multiplexer is connected to a buffer store. In addition, the memory device includes a synchronization circuit having a control output connected to a control input of the multiplexer. A clock signal output of the synchronization circuit is connected to the clock input of the register device. The synchronization circuit generates and outputs a clock signal to the clock signal output derived from a time profile for a signal on a state input and from a signal on a second clock input. In this way, a data word to be stored in the register device is synchronized to a clock signal on the second clock input, so that data errors are avoided during transfer.

Abstract: A phase locked loop circuit and method of locking a phase. The phased locked loop circuit may include a phase detector receiving an external clock signal and a feedback clock signal and outputting an up signal when a phase of the external clock signal leads a phase of the feedback clock signal and outputting a down signal when the phase of the external clock signal lags the phase of the feedback clock signal, a loop filter circuit increasing a control voltage in response to the up signal and decreasing the control voltage in response to the down signal, and a voltage controlled oscillator circuit receiving the control voltage and directly generating at least n (where n is an integer ?4) internal clock signals. The phased locked loop circuit may also include a voltage controlled oscillator circuit, including at least four loops, receiving the control voltage and generating multiple internal clock signals.

Abstract: Provided is a synchronous semiconductor memory device with improved latency control. In one embodiment, the synchronous semiconductor memory device may include a clock synchronizing circuit, a latency circuit, and a latency control circuit. The clock synchronizing circuit may receive an external clock signal and output a data output clock signal. The latency circuit may store a read signal in response to at least one sampling clock signal, generate a plurality of clock control signals in a sequential manner, generate a plurality of transfer clock signals synchronized with the plurality of clock control signals, and supply a latency signal in response to the transfer clock signals. The latency control circuit may delay the plurality of clock control signals by the sum of output delay time and the read command delay time so as to generate a plurality of sampling clock signals synchronized with the plurality of delayed clock control signals.