Abstract: A support jack, in particular for supporting semitrailers, includes a vertically telescopically displaceable supporting element having an outer sleeve and an inner sleeve, each sleeve having a rectangular cross-section with four sidewalls in each case. At least one sidewall at least of the inner sleeve has an additional wall plate. Another alternative proposes that at least one sidewall at least of the inner sleeve consists of a wall plate which the two adjacent sidewalls are fixed. An arrangement of such a support jack on the lower side of a vehicle is also described.

Abstract: A protecting fence and its positioning member include a protecting fence, a positioning block and a positioning base. The protecting fence is made of foamed engineering plastics by extrusion, with reflective bands. The positioning block has a through hole and an inner surface shaped to match with the protecting fence. The positioning base has a fence combining surface plural holes for being inserted by a bolt to keep the protecting fence and the positioning block fixed together with the positioning base. The fence combining surface has two edge surfaces respectively formed a groove to engage with two edges of the protecting fence. A rear fixing member has a post combining surface employed together with that of the positioning base to wrap the fence post to tightly fix the protecting fence with the fence post by bolts.

Abstract: The method of fabricating a set of semiconducting nanowires (10) having a desired wire diameter (d) comprises the steps of providing a set of pre-fabricated semiconducting nanowires (10?), at least one pre-fabricated semiconducting nanowire having a wire diameter (d?) larger than the desired wire diameter (d), and reducing the wire diameter of the at least one pre-fabricated nanowire (10?) by etching, the etching being induced by light which is absorbed by the at least one pre-fabricated nanowire (10?), a spectrum of the light being chosen such that the absorption of the at least one pre-fabricated nanowire being significantly reduced when the at least one pre-fabricated nanowire reaches the desired wire diameter (d). The electric device (100) may comprise a set of nanowires (10) having the desired wire diameter (d). The apparatus (29) may be used to execute the method according to the invention.

Abstract: An intermediate electrode between an ovonic threshold switch and a memory element may be formed in the same pore with the memory element. This may have many advantages including, in some embodiments, reducing leakage.

Abstract: A semiconductor memory device includes a first resistance change element having a first portion and a second portion, the first portion and the second portion having a first space in a first direction, and a second resistance change element formed to have a distance to the first resistance change element in the first direction, and having a third portion and a fourth portion, the third portion and the fourth portion having a second space in the first direction, and the first space and the second space being shorter than the distance.

Abstract: An electrically re-programmable fuse (eFUSE) device for use in integrated circuit devices includes an elongated heater element, an electrically insulating liner surrounding an outer surface of the elongated heater element, corresponding to a longitudinal axis thereof, leaving opposing ends of the elongated heater element in electrical contact with first and second heater electrodes. A phase change material (PCM) surrounds a portion of an outer surface of the electrically insulating liner, a thermally and electrically insulating layer surrounds an outer surface of the PCM, with first and second fuse electrodes in electrical contact with opposing ends of the PCM. The PCM is encapsulated within the electrically insulating liner, the thermally and electrically insulating layer, and the first and second fuse electrodes.

Abstract: Thin-film phase-change memories having small phase-change switching volume formed by overlapping thin films. Exemplary embodiments include a phase-change memory element, including a first phase change layer having a resistance, a second phase change layer having a resistance, an insulating layer disposed between the first and second phase change layers; and a third phase change layer having a resistance, and coupled to each of the first and second phase change layers, bridging the insulating layer and electrically coupling the first and second phase change layers, wherein the resistance of the third phase change layer is greater than both the resistance of the first phase change layer and the second phase change layer.

Abstract: A programmable resistance memory combines multiple cells into a block that includes one or more shared electrodes. The shared electrode configuration provides additional thermal isolation for the active region of each memory cell, thereby reducing the current required to program each memory cell.

Abstract: Systems and methods for devices that include a structure having at least one resonant cavity and at least one emitter having an emission frequency that is substantially in the telecommunication wavelengths are provided. The emission frequency can be coupled to the resonant frequency of resonant cavity so that emitted wavelengths corresponding to the resonant wavelengths of the resonant cavity are enhanced. Moreover, the devices of the present invention may be capable of operating at room temperatures.

Abstract: A nanowire (100) according to the present invention includes a plurality of contact regions (10a, 10b) and at least one channel region (12), which is connected to the contact regions (10a, 10b). The channel region (12) is made of a first semiconductor material and the surface of the channel region (12) is covered with an insulating layer that has been formed selectively on the channel region (12). The contact regions (10a, 10b) are made of a second semiconductor material, which is different from the first semiconductor material for the channel region (12), and at least the surface of the contact regions (10a, 10b) includes a conductive portion.

Abstract: The present invention provides methods and systems for nanowire alignment and deposition. Energizing (e.g., an alternating current electric field) is used to align and associate nanowires with electrodes. By modulating the energizing, the nanowires are coupled to the electrodes such that they remain in place during subsequent wash and drying steps. The invention also provides methods for transferring nanowires from one substrate to another in order to prepare various device substrates. The present invention also provides methods for monitoring and controlling the number of nanowires deposited at a particular electrode pair, as well as methods for manipulating nanowires in solution.

Abstract: A quantum interference transistor comprising a thin metal film having a protrusion and a thin insulating layer between the metal film and protrusion. A potential barrier is formed in the region beneath the protrusion as a result of quantum interference caused by the geometry of the film and protrusion. A voltage applied between the electrically isolated protrusion (“island”) and the thin film leads to a change in the electron wave function of the island which in turn leads to a change in the Fermi level of the metal film in the entire region beneath the protrusion. Consequently, a potential barrier may or may not exist depending on the applied voltage, thus providing the present invention with the transistor-like property of switching between open and closed states.

Abstract: The disclosed is a semiconductor device which comprises a circuit which is formed on a substrate and which includes an insulated gate type semiconductor field-effect transistor element or an TFT element, wherein as compared with the electrostatic capacitance per a unit area of a gate insulating film at a channel part of the transistor element, the electrostatic capacitance per a unit area of a insulating film at the other portion of overlap part between electrodes or wiring lines is small. In the semiconductor device which has an insulated gate type semiconductor field-effect transistor element or a TFT element, a high mutual conductance is obtained and the absolute value of gate threshold voltage is repressed while the adverse influence to the circuit operation by means of the parasitic capacity is repressed.

Abstract: Certain spin-coatable liquids and application techniques are described, which can be used to form nanotube films or fabrics of controlled properties. A spin-coatable liquid for formation of a nanotube film includes a liquid medium containing a controlled concentration of purified nanotubes, wherein the controlled concentration is sufficient to form a nanotube fabric or film of preselected density and uniformity, and wherein the spin-coatable liquid comprises less than 1×1018 atoms/cm3 of metal impurities. The spin-coatable liquid is substantially free of particle impurities having a diameter of greater than about 500 nm.

Abstract: Gate dielectric structures comprising an organic polymeric component, and organic semiconductor components, as can be used to fabricate thin film transistor devices.

Abstract: Provided are a thin film transistor for display devices and a manufacturing method of the thin film transistor. The thin film transistor for display devices includes: a flexible substrate; a gate electrode layer formed on the flexible substrate; a first insulating layer formed on the flexible substrate and the gate electrode; a source and a drain formed on the first insulating layer; an active layer formed on the first insulating layer between the source and the drain; a second insulating layer formed on the first insulating layer, the source, the drain, and the active layer; and a drain electrode that opens the second insulating layer to be connected to the drain and is formed of a CNT dispersed conductive polymer.

Abstract: A flat panel display device, more particularly, an Organic Light Emitting Diode (OLED) display device having uniform electrical characteristics and a method of fabricating the same include: a thin film transistor of which a semiconductor layer including a source, a drain, and a channel region formed in a super grain silicon (SGS) crystallization growth region; a capacitor formed in an SGS crystallization seed region; and an OLED electrically connected to the thin film transistor. Further, a length of the channel region of the silicon layer is parallel with the growth direction in the SGS growth region to improve the electrical properties thereof.

Abstract: An exemplary organic semiconductor copolymer includes a polymeric repeat structure having a polythiophene structure and an electron accepting unit. The electron accepting unit has at least one electron-accepting heteroaromatic structure with at least one electron-withdrawing imine nitrogen in the heteroaromatic structure or a thiophene-arylene comprising a C2-30 heteroaromatic structure. Methods of synthesis and electronic devices incorporating the disclosed organic semiconductors, e.g., as a channel layer, are also disclosed.

Abstract: Classes of molecules are disclosed which can, for example, be used in molecular switches. The classes of molecules include at least three segments—an electronic donor (“D”), a switchable bridge (“B”), and an electronic acceptor (“A”)—chemically connected and linearly arranged (e.g., D-B-A). The electronic donor can be an aromatic ring system with at least one electron donating group covalently attached; an aromatic ring system with an electron withdrawing group covalently attached is usually employed as the electronic acceptor; and the switchable bridge can be a pi system that can be switched on or off using an external electric field.

Abstract: A device is provided having a first electrode, a second electrode, a first photoactive region having a characteristic absorption wavelength ?1 and a second photoactive region having a characteristic absorption wavelength ?2. The photoactive regions are disposed between the first and second electrodes, and further positioned on the same side of a reflective layer, such that the first photoactive region is closer to the reflective layer than the second photoactive region. The materials comprising the photoactive regions may be selected such that ?1 is at least about 10% different from ?2. The device may further comprise an exciton blocking layer disposed adjacent to and in direct contact with the organic acceptor material of each photoactive region, wherein the LUMO of each exciton blocking layer other than that closest to the cathode is not more than about 0.3 eV greater than the LUMO of the acceptor material.

Abstract: Disclosed is a thin film transistor including a P-type semiconductor layer, and an organic light-emitting display device having the thin film transistor. The present invention provides a thin film transistor including a substrate, a semiconductor layer, and a gate electrode and a source/drain electrode formed on the substrate, wherein the semiconductor layer is composed of P-type ZnO:N layers through a reaction of a mono-nitrogen gas with a zinc precursor, and the ZnO:N layer includes an un-reacted impurity element at a content of 3 at % or less.

Abstract: A test structure for inspecting an allowable process margin in a manufacturing process for a semiconductor device is provided. The test structure includes a plurality of grounded conductive lines on a substrate and electrically grounded to the substrate. A plurality of floating conductive lines are provided, each of the plurality of conductive lines being spaced apart from the grounded conductive lines and electrically separated from the grounded conductive lines on the substrate. A plurality of supplementary patterns are provided for measuring the allowable process margin by a voltage contrast between the grounded conductive lines and the floating conductive lines. Related methods of testing are also provided.

Abstract: A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.

Abstract: An image sensor contains a semiconductor substrate, a plurality of pixels defined on the semiconductor substrate, a photo conductive layer and a transparent conductive layer formed on the pixel electrodes of the pixels in order, and a shield device positioned between any two adjacent pixel electrodes. The shield device has a shield electrode and an isolation structure surrounding the shield electrode so that the shield electrode is isolated from the pixel electrodes and the photo conductive layer by the isolation structure.

Abstract: An image sensor and a method of manufacturing the same are provided. A metal wiring layer is formed on a semiconductor substrate including a circuit region, and first conductive layers are formed on the metal layer separated by a pixel isolation layer. An intrinsic layer is formed on the first conductive layers, and a second conductive layer is formed on the intrinsic layer.

Abstract: Disclosed is an image sensor, which includes a substrate having a transistor circuit and lower interconnections. First interconnections are formed separated from each other on the substrate and electrically connected to the CMOS circuitry through the lower interconnections. Planarized insulating layers are formed between the first interconnections to isolate unit pixels. An intrinsic layer is formed on the substrate including the insulating layers, and a second conductive layer is formed on the intrinsic layer. The first interconnections, the intrinsic layer and the second conductive layer provide a photodiode structure for the image sensor.

Abstract: A thin film transistor including a substrate, a gate, a gate insulator layer, a semiconductor layer, an ohmic contact layer, a source and a drain is provided. The gate is disposed on the substrate while the gate insulator layer is disposed on the substrate and covers the gate. The semiconductor layer is disposed on the gate insulator layer above the gate. The semiconductor layer includes an undoped amorphous silicon layer and a first undoped microcrystalline silicon (?c-Si) layer, wherein the first undoped ?c-Si layer is disposed on the undoped amorphous silicon layer. The ohmic contact layer is disposed on part of the semiconductor layer and the source and the drain are disposed on the ohmic contact layer. Therefore, the thin film transistor has better quality control and electrical characteristics.

Abstract: It is an object of the present invention to provide a semiconductor device mounted with a memory which can be driven in the ranges of a current value and a voltage value which can be generated from a wireless signal. It is another object to provide a write-once read-many memory into which data can be written anytime after manufacture of a semiconductor device. An antenna, an antifuse-type ROM, and a driver circuit are formed over a substrate having an insulating surface. A stacked layer of a silicon film and a germanium film is interposed between a pair of electrodes included in the antifuse-type ROM. The antifuse-type ROM having this stacked layer can reduce fluctuation in writing voltage.

Abstract: A method for fabricating an LCD includes: providing a substrate with a thin film transistor (ITT) part defined thereon; forming a metallic film for a gate electrode on the substrate; etching the metallic film through a first printing process to form a gate electrode; sequentially forming a gate insulating layer, a semiconductor layer, and a metallic film for source and drain electrodes on the substrate; selectively etching the metallic film for source and drain electrodes, the semiconductor layer and the gate insulating layer through a second printing process to form a gate insulating layer pattern, a preliminary active pattern and a metallic film pattern which are sequentially stacked such that the gate insulating layer pattern is over-etched from the side of the preliminary active pattern; forming an insulating layer on the substrate with the metallic film pattern; etching the insulating layer to expose the metallic film pattern; forming a transparent conductive film on the metallic film pattern and a remai

Abstract: A semiconductor structure of a liquid crystal display and the manufacturing method thereof are described. The manufacturing method includes the following steps. A patterned polysilicon layer and a first dielectric layer are formed on a substrate. A first patterned metal layer is formed to construct a gate electrode and a capacitor electrode. An ion implantation is conducted on the polysilicon layer to form drain and source electrodes. A second dielectric layer and a second patterned metal layer are formed thereon. Sequentially, a third dielectric layer is formed thereon. A plurality of via openings are formed by a patterned photoresist layer, and a third metal layer is formed thereon and filled into the via openings. The patterned photoresist layer and the redundant third metal layer are stripped from the substrate to form via plugs in the via openings. A patterned transparent conductive layer is formed thereon to connect the via plugs.

Abstract: A thin film transistor and a method of fabricating the same include: a semiconductor layer having a grain boundary disposed in a crystal growth direction and having a variation in height of a top surface of 15 nm or less formed by a thin beam directional crystallization method. Also, an organic light emitting diode (OLED) display device comprising the thin film transistor is provided and has excellent characteristics fabricated by a simple process. Also, a flat panel display device and a method of fabricating the same are provided and include: a polycrystalline silicon layer in a pixel region; and a polycrystalline silicon layer in a peripheral region formed by the thin beam directional crystallization method. Also, a semiconductor device and a method of fabricating the same include: an intrinsic region of a semiconductor layer in the photodiode region formed by the thin beam directional crystallization method.

Abstract: A method of fabricating a thin film transistor is disclosed. First, a substrate is provided and a patterned polysilicon layer is formed on the substrate. A metal layer is formed on the patterned polysilicon layer. Then, a portion of the metal layer is removed so that the remaining metal layer beside the patterned polysilicon layer forms a source and a drain. A gate insulation layer is formed on the substrate to cover the source, the drain and the patterned polysilicon layer. A gate is formed on the gate insulation layer over the patterned polysilicon layer.

Abstract: A semiconductor device includes a Si crystal having a crystal surface in the vicinity of a (111) surface, and an insulation film formed on said crystal surface, at least a part of said insulation film comprising a Si oxide film containing Kr or a Si nitride film containing Ar or Kr.

Abstract: The invention provides a semiconductor apparatus provided with at least one set of buried channel type first conductive type MOS transistor and surface channel type first conductive type MOS transistor on the same substrate, in which a first conductive type impurity region is provided below a gate electrode of the buried channel type and surface channel type MOS transistors and between source drain regions. Further, the invention provides a solid state image pickup device having a photoelectric conversion portion and a pixel including a plurality of transistors formed in correspondence to the photoelectric conversion portion, in a substrate, wherein the plurality of transistors includes a buried channel type first conductive type MOS transistor and a surface channel type first conductive type MOS transistor, and a first conductive type impurity region is provided below a gate electrode of the buried channel type and surface channel type MOS transistors and between source drain regions.

Abstract: A thin film transistor includes a gate electrode, a gate insulating film formed to cover the gate electrode, a semiconductor layer including a channel region formed over the gate electrode, a source electrode and a drain electrode including a region connected to the semiconductor layer, where at least a part of the region is overlapped with the gate electrode, an upper insulating film formed to cover the semiconductor layer, the source electrode and the drain electrode, where the upper insulating film is directly in contact with the channel region of the semiconductor layer and discharges moisture by a heat treatment and a second upper insulating film formed to cover the first protective film and suppress moisture out-diffusion.

Abstract: A semiconductor sensing device in which a sensing layer is exposed to a medium being tested in an area below and/or adjacent to a contact. In one embodiment, the device comprises a field effect transistor in which the sensing layer is disposed below a gate contact. The sensing layer is exposed to the medium by one or more perforations that are included in the gate contact and/or one or more layers disposed above the sensing layer. The sensing layer can comprise a dielectric layer, a semiconductor layer, or the like.

Abstract: The present invention provides a silicon carbide semiconductor device comprising a semiconductor substrate comprising silicon carbide, which contains a first conductivity type impurity diffused therein in a high concentration, a semiconductor layer formed over the semiconductor substrate and containing the first conductivity type impurity diffused therein in a low concentration, a plurality of well regions formed on a front surface side of a cell forming area set to the semiconductor layer and in which a second conductivity type impurity corresponding to a type opposite to the first conductivity type impurity is diffused, source layers formed on the front surface side lying within the well regions and each containing the first conductivity type impurity diffused therein in a high concentration, an outer peripheral insulating film thick in thickness, which is formed over the semiconductor layer in an outer peripheral area that surrounds the cell forming area, a gate oxide film formed over the front surface of

Abstract: The SiC semiconductor device includes a substrate of a first conduction type made of silicon carbide, a drift layer of the first conduction type made of silicon carbide, the drift layer being less doped than the substrate, a cell portion constituted by a part of the substrate and a part of the drift layer, a circumferential portion constituted by another part of the substrate and another part of the drift layer, the circumferential portion being formed so as to surround the cell portion, and a RESURF layer of a second conduction type formed in a surface portion of the drift layer so as to be located in the circumferential portion. The RESURF layer is constituted by first and second RESURF layers having different impurity concentrations, the second RESURF layer being in contact with an outer circumference of the first RESURF layer and extending to a circumference of the cell portion.

Abstract: A nitride-based semiconductor element having superior mass productivity and excellent element characteristics is obtained. This nitride-based semiconductor element comprises a substrate comprising a surface having projection portions, a mask layer formed to be in contact with only the projection portions of the surface of the substrate, a first nitride-based semiconductor layer formed on recess portions of the substrate and the mask layer and a nitride-based semiconductor element layer, formed on the first nitride-based semiconductor layer, having an element region. Thus, the first nitride-based semiconductor layer having low dislocation density is readily formed on the projection portions of the substrate and the mask layer through the mask layer serving for selective growth.

Abstract: A method for providing a flat panel display comprising the steps of: providing an anode assembly containing a plurality of pixels; applying a photoresist to a surface of the anode assembly; applying a mask that defines a control frame top surface; exposing the mask to UV radiation and causing the photoresist to cross link at the exposed areas of the photoresist such that the exposed photoresist is inert and does not outgas in a vacuum; removing the unexposed areas of the photoresist to define a pedestal; forming a planarizing layer over the exposed photoresist pedestal; applying a metal layer over the planarizing layer; applying a second photoresist over the metal layer; exposing portions of the second photoresist and removing excess of the metal layer and the planarizing layer to form the metal layer only on top of the exposed photoresist pedestal; and applying nanotube emitters on the metal layer.

Abstract: An electronic device includes a base having a first wiring thereon; a flexible film having a second wiring thereon; a plurality of elements each including a first connecting portion and a second connecting portion; and an adhesive agent layer, wherein each of the elements is sandwiched between the base and the film in a state in which the first connecting portion is in contact with the first wiring, the second connecting portion is in contact with the second wiring, and a tensile force is applied to the film, and, in this state, the base and the film are bonded with the adhesive agent layer.

Abstract: One embodiment of the present invention provides a semiconductor light-emitting device which includes a multi-layer structure. The multilayer structure comprises a first doped layer, an active layer, and a second doped layer. The semiconductor light-emitting device further includes a first Ohmic-contact layer configured to form a conductive path to the first doped layer, a second Ohmic-contact layer configured to form a conductive path to the second doped layer, and a support substrate comprising not less than 15% chromium (Cr) measured in weight percentage.

Abstract: An LED unit including a frame (17) and a plurality of LED elements (11, 12, 13) which emit three primary colors of light and are sealed in the frame (17), readable characteristic data such as drive conditions, characteristics of each of the plurality of LED elements (11, 12, 13) being displayed on a surface of the frame.

Abstract: A luminescence diode (1) having an active zone (7) which emits electromagnetic radiation in a main radiating direction (15). A reflection-reducing layer sequence (16) is arranged downstream of the active zone (7) in the main radiating direction (15). The reflection-reducing layer sequence includes a DBR mirror (13), which is formed by at least one layer pair (11, 12), an antireflective layer (9) downstream of the DBR mirror (13) in the main radiating direction (15) and an intermediate layer (14) arranged between the DBR mirror (13) and the antireflective layer (9).

Abstract: An optoelectronic device includes a passivation layer of a dielectric material having a graded composition that varies with depth, whether continuous or stepwise, to provide a first index of refraction proximate to a semiconductor or conductor material and provide a second index of refraction adjacent to a surrounding material, such as an encapsulant. The resulting graded dielectric layer reduces Fresnel losses by reducing index of refraction mismatches between the adjacent semiconductor or conductor layer and the surrounding medium. Methods for forming graded dielectric layers include supplying a nitrogen-containing source gas at a declining flow rate or concentration, while supplying an oxygen-containing source gas an rising flow rate or concentration, to a deposition chamber.

Abstract: A light emitting device having a stack of layers bonded to an undoped substrate with a doped layer between the stack of layers and the undoped substrate. The stack of layers include a layer of first conductivity type over the doped layer, an overlying light emitting layer and a layer of second conductivity type. In one embodiment, the doped substrate is grown on a sacrificial substrate along with the remaining stack of layers prior to bonding to the undoped substrate. Electrical contacts are coupled to device on a side opposite the undoped substrate. In one embodiment, the layers of first conductivity, the light emitting layer, and the layer of second conductivity are removed to expose the doped layer and a first electrical contact is coupled to the layer of first conductivity through the doped substrate, while a second electrical contact is coupled to the layer of second conductivity.

Abstract: The invention relates to an optical element (1, 25) having a defined shape and comprising a thermoplastic material that has been further cross-linked during or following the shaping thereof. Such thermoplastic materials have an increased heat deflection temperature, distortion, but can be easily and economically shaped before the additional cross-linking as a result of the thermoplastic properties thereof.

Abstract: Provided is a method of manufacturing a high-power LED package, the method including the steps of: preparing a mold having an irregularity pattern; providing a transparent resin solid having an irregularity pattern provided on the surface thereof by using the mold; preparing an irregularity film with the irregularity pattern by cutting a portion of the transparent resin solid; preparing an LED package structure having a cavity in which an LED chip is mounted; filling transparent liquid resin into the cavity having the LED chip mounted therein; mounting the irregularity film on the transparent liquid resin such that the irregularity film projects from the cavity at a predetermined height; and curing the transparent liquid resin having the irregularity film mounted thereon. The irregularity pattern of the irregularity film projects from the cavity at a predetermined height.

Abstract: A semiconductor light emitting device that is excellent in radiating heat and that can be molded into a sealing shape having intended optical characteristics by die molding is provided. The semiconductor light emitting device includes: a lead frame including a plate-like semiconductor light emitting element mounting portion having an LED chip mounted on a main surface, and a plate-like metal wire connecting portion extending over a same plane as the semiconductor light emitting element mounting portion; a metal wire electrically connecting the LED chip and the metal wire connecting portion; a thermosetting resin molded by die molding or dam-sheet molding so as to completely cover the LED chip and the metal wire; and a resin portion provided to surround the lead frame and having the thickness not greater than the thickness of the lead frame.

Abstract: A light emitting diode (LED) package including: an LED chip; a first lead frame having a heat transfer unit with a top where a groove for stably mounting the LED chip is formed; a second lead frame disposed separately from the first lead frame; a package body having a concave portion encapsulating a portion of the heat transfer unit and the second lead frame but exposing a portion of the top of the heat transfer unit and a portion of the lead frame, and a ring-shaped portion extended in a ring shape along an inner wall of the groove of the heat transfer unit and forming an aperture in a center thereof; and a phosphor layer formed on the aperture of the ring-shaped portion and applied to the LED chip, wherein the LED chip is disposed in the inside of the aperture of the ring-shape portion.