Abstract: A light emitting device can be characterized as including a light emitting diode configured to emit light and a phosphor configured to change a wavelength of the light. The phosphor substantially covers at least a portion of the light emitting diode. The phosphor includes a compound having a host material. Divalent copper ions and oxygen are components of the host material.

Abstract: A light emitting device using a silicon (Si) nanocrystalline Si insulating film is presented with an associated fabrication method. The method provides a doped semiconductor or metal bottom electrode. Using a high density plasma-enhanced chemical vapor deposition (HDPECVD) process, a Si insulator film is deposited overlying the semiconductor electrode, having a thickness in a range of 30 to 200 nanometers (nm). For example, the film may be SiOx, where X is less than 2, Si3Nx, where X is less than 4, or SiCx, where X is less than 1. The Si insulating film is annealed, and as a result, Si nanocrystals are formed in the film. Then, a transparent metal electrode is formed overlying the Si insulator film. An annealed Si nanocrystalline SiOx film has a turn-on voltage of less than 20 volts, as defined with respect to a surface emission power of greater than 0.03 watt per square meter.

Abstract: Provided are a top-emitting nitride-based light emitting device having an n-type clad layer, an active layer and a p-type clad layer sequentially stacked thereon, comprising an interface modification layer formed on the p-type clad layer and a transparent conductive thin film layer made up of a transparent conductive material formed on the interface modification layer; and a process for preparing the same. In accordance with the top-emitting nitride-based light emitting device of the present invention and a process for preparing the same, there are provided advantages such as improved ohmic contact with the p-type clad layer, leading to increased wire bonding efficiency and yield upon packaging the light emitting device, capability to improve luminous efficiency and life span of the device due to low specific contact resistance and excellent current-voltage properties.

Abstract: An LED interconnect spring clip assembly includes a housing having a center cavity and a plurality of contact features. Each contact feature has a portion retained by the housing and another portion that is operable to contact a terminal of an LED package disposed within the center cavity of the housing. The LED interconnect spring clip assembly retains the LED package when mounted to a substrate.

Abstract: A semiconductor device includes a substrate, a semiconductor layer formed on the substrate, and an optically functional portion formed by using at least a portion of the semiconductor layer. The optically functional portion performs light emission or light reception. The semiconductor device further includes a first driving electrode that is electrically connected to a semiconductor layer on a surface of the optically functional portion, and the first driving electrode drives the optically functional portion. The semiconductor device further includes an encapsulating electrode that is formed on the semiconductor layer to surround periphery of the optically functional portion, and electrically connected to the first driving electrode.

Abstract: A nitride-based semiconductor LED includes a substrate; an n-type nitride semiconductor layer formed on the substrate; an active layer and a p-type nitride semiconductor layer that are sequentially formed on a predetermined region of the n-type nitride semiconductor layer; a transparent electrode formed on the p-type nitride semiconductor layer; a p-electrode pad formed on the transparent electrode, the p-electrode pad being spaced from the outer edge line of the p-type nitride semiconductor layer by 50 to 200 ?m; and an n-electrode pad formed on the n-type nitride semiconductor layer.

Abstract: A submount is used to mount a diode between two metal areas on the upper surface of a substrate. One of the areas is connected to a metal plate at the lower surface of the substrate through a via. The submount is clamped between two metal sheets. The top metal sheet has a through-hole for anchoring and self-aligning the diode. The electrodes of the diode are each coupled to one of the clamping metal sheets. Clamping metals provide pressure contact without soldering to the contact. But soldering can be alternatively used to enhance product reliability. Either the top metal sheet or the bottom metal sheet can be fully or selectively coating of solder for batch soldering at the contact point upon heating. The large metal plates and the large metal clamping sheets provide good heat sink and speedy soldering.

Abstract: A nitride semiconductor wafer includes a substrate; a nitride compound semiconductor layer formed on the substrate; and an AlxGa1-xAs layer (x?0.6) formed between the substrate and the nitride semiconductor layer. The nitride compound semiconductor layer is formed of a nitride compound in a group III to a group V.

Abstract: A light emitting device including, between an input mirror and an output mirror forming a cavity, the output mirror having a reflectivity strip, a stack itself including an etch stop layer and an active layer. The stop layer is adapted to filter at least wavelengths lower than the lower limit of the reflectivity strip.

Abstract: A silicon control rectifier and an electrostatic discharge protection device of an integrated circuit including the silicon control rectifier. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.

Abstract: A method for fabricating transistors such as high electron mobility transistors, each transistor comprising a plurality of epitaxial layers on a common substrate, method comprising: (a) forming a plurality of source contacts on a first surface of the plurality of epitaxial layers; (b) forming at least one drain contact on the first surface; (c) forming at least one gate contact on the first surface; (d) forming at least one insulating layer over and between the gate contacts, source contacts and the drain contacts; (e) forming a conductive layer over at least a part of the at least one insulating layer for connecting the source contacts; and (f) forming at least one heat sink layer over the conductive layer.

Abstract: A technology which allows an improvement in the moisture resistance of a semiconductor device is provided. In a GaAs substrate as a semi-insulating substrate, a HBT is formed in an element formation region, while an isolation region is formed in an insulating region. The isolation region formed in the insulating region is formed by introducing helium into the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT. In an outer peripheral region, a conductive layer is formed to be exposed from protective films and coupled to a back surface electrode. Because a GND potential is supplied to the back surface electrode, the conductive layer is fixed to the GND potential. The conductive layer is formed of the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT.

Abstract: Semiconductor device structures for use with bipolar junction transistors and methods of fabricating such semiconductor device structures. The semiconductor device structure includes a semiconductor body having a top surface and sidewalls extending from the top surface to an insulating layer, a first region including a first semiconductor material with a first conductivity type, and a second region including a second semiconductor material with a second conductivity type. The first and second regions each extend across the top surface and the sidewalls of the semiconductor body. The device structure further includes a junction defined between the first and second regions and extending across the top surface and the sidewalls of the semiconductor body.

Abstract: A semiconductor integrated circuit is provided which entails no increase in the correction time of OPC and in which non-uniformity in the gate lengths due to the optical proximity effects is surely suppressed. A plurality of standard cells (C1, C2, C3, . . . ), each including gates G extended in the vertical direction, are aligned in the transverse direction to form a standard cell row. A plurality of the standard cell rows are located side by side in the vertical direction to form a standard cell group. Each of the standard cell rows has a terminal standard cell Ce at least one end of the standard cell row. The terminal standard cell Ce includes two or more supplementary gates, each of which is any of a dummy gate and a gate of an inactive transistor.

Abstract: Repeaters are arranged at arbitrary positions to substantially improve transmission speed of a signal. In the semiconductor integrated circuit device 1, repeater regions 10 where repeaters are provided as relay points for wiring are provided in the central parts of the core power source regions 2, 3 and 5, on the left side of the core power source regions 4 to 8 and at the upper and lower parts of the semiconductor integrated circuit device 1. A power switch region for repeater 11 is formed so as to surround the core power source regions 2 to 8 and the repeater regions 10. The power source lines of the reference potential connected to the repeater regions 10 are laid out at equally spaced intervals throughout the core power source regions 2 to 8, which enables the repeater regions 10 to be flexibly laid out. This permits the repeaters to be more effectively arranged, which improves the performances of semiconductor integrated circuit device 1.

Abstract: A memory device includes a multi gate field effect transistor (MuGFET) having a fin with a contact area. A programmable memory element abuts the fin contact area.

Abstract: A CCD containing circuit and method for making the same. The circuit includes a CCD array and a protection circuit. The CCD array is constructed on an integrated circuit substrate and includes a plurality of gate electrodes that are insulated from the substrate by an insulating layer. The gate electrodes are connected to a conductor bonded to the substrate. The protection circuit is also constructed on the substrate. The protection circuit is connected to the conductor and to the substrate and protects the CCD array from both negative and positive voltage swings generated by electrostatic discharge events and the like. The protection circuit and the CCD can be constructed in the same integrated circuit fabrication process.

Abstract: A radiation detecting system includes at least a carrier collective electrode layer, a radiation-sensitive semiconductor layer, at least one charge transfer layer, and a voltage applying electrode formed on an insulating substrate and wherein at least one of the charge transfer layers includes chalcogenide compounds containing therein chalcogenide elements larger than the stoichiometric value by not smaller than 3% of the stoichiometric value in a composition thereof.

Abstract: A back irradiating type solid state imaging device comprises: a first semiconductor substrate; a plurality of photoelectric converting devices that receives a light incident from a back side of the first semiconductor substrate and are formed in a two-dimensional array on a surface side of the first semiconductor substrate; a CCD type signal reading section that are formed on the surface side of the first semiconductor substrate and reads detection signals of the photoelectric converting devices; and a MOS type signal reading section that are formed on the surface side of the first semiconductor substrate and reads detection signals of the photoelectric converting devices.

Abstract: The present invention discloses the use of edge-angle-optimized solid phase epitaxy for forming hybrid orientation substrates comprising changed-orientation Si device regions free of the trench-edge defects typically seen when trench-isolated regions of Si are recrystallized to the orientation of an underlying single-crystal Si template after an amorphization step. For the case of amorphized Si regions recrystallizing to (100) surface orientation, the trench-edge-defect-free recrystallization of edge-angle-optimized solid phase epitaxy may be achieved in rectilinear Si device regions whose edges align with the (100) crystal's in-plane <100> directions.

Abstract: In another embodiment, the invention provides a compound semiconductor field effect transistor having a fin structure. A first layer is formed on or above a substrate, wherein the first layer contains a first compound semiconductor material. A second layer is formed on the first layer, wherein the second layer comprises a second compound semiconductor material. A third layer is formed on the second layer, wherein the third layer comprises a third compound semiconductor material. A cap layer is formed on at least one partial region of the third layer, wherein the cap layer comprises a fourth compound semiconductor material. The second layer, the third layer and the cap layer are patterned in such a way that a fin structure is formed. A first source/drain region is formed from a first partial region of the cap layer, and a second source/drain region is formed from a second partial region of the cap layer.

Abstract: A method of making a source-gated transistor is described, in which a gate (4) is provided on substrate (2) followed by gate insulator (6) and semiconductor layer (8). The layer is patterned to align the source with the gate (4) using photoresist (12) and back illumination through the substrate (2) with the gate (4) acting as a mask. The distance between source and drain may also be self-aligned using a spacer technique.

Abstract: A semiconductor device structure is formed over a semiconductor substrate and has a gate dielectric over the semiconductor substrate and a gate over the gate dielectric. The gate, at an interface with the gate dielectric, comprises a transition metal, carbon, and an electropositive element. The transition metal comprises one of group consisting of tantalum, titanium, hafnium, zirconium, molybdenum, and tungsten. The electropositive element comprises one of a group consisting of a Group IIA element, a Group IIIB element, and lanthanide series element.

Abstract: A pixel sensor cell of improved dynamic range comprises a coupling transistor that couples a capacitor device to a photosensing region (e.g., photodiode) of the pixel cell, the photodiode being coupled to a transfer gate and one terminal of the coupling transistor. In operation, the additional capacitance is coupled to the pixel cell photodiode when the voltage on the photodiode is drawn down to the substrate potential. Thus, the added capacitance is only connected to the imager cell when the cell is nearing its charge capacity. Otherwise, the cell has a low capacitance and low leakage. In an additional embodiment, a terminal of the capacitor is coupled to a “pulsed” supply voltage signal that enables substantially full depletion of stored charge from the capacitor to the photosensing region during a read out operation of the pixel sensor cell. In various embodiments, the locations of the added capacitance and photodiode may be interchanged with respect to the coupling transistor.

Abstract: A new structure of a photodiode of a pixel in CMOS image sensor and a method of fabricating the same are provided. The photodiode is fabricated by using one photo mask, so that the number of masks decreases and the fabrication processes are simplified. In addition, two conducting layers constituting a photodiode are self-aligned, so that a fabrication process for connecting the photodiode and a transfer transistor is not required. Accordingly, a problem of channeling generated in a lower portion of a gate of the transfer transistor can be solved, so that an improved pixel can be fabricated.

Abstract: An apparatus that can effectively operate in high temperatures including a CMOS image sensor, a thermoelectric semiconductor formed under the CMOS image sensor for selectively cooling the image sensor and a heat sink formed under the thermoelectric semiconductor.

Abstract: An image sensor and a method for manufacturing an image sensor that has an increased aspect ratio. An image sensor and a method for manufacturing an image sensor that have a relatively large process margin (e.g. even in high level pixels), which may reduce and/or eliminate restrictions in downscaling an image sensor. An image sensor may include at least one of a first unit pixel including a first transfer transistor, a second unit pixel including a second drive transistor, and a contact electrically connecting a floating diffusion region of the first unit pixel with the second drive transistor of the second unit pixel. A method of manufacturing an image sensor including at least one of forming a first unit pixel including a first transfer transistor, forming a second unit pixel including a second drive transistor, and forming a contact electrically connecting a floating diffusion region of the first unit pixel with the second drive transistor of the second unit pixel.

Abstract: An image sensor with sufficient photoelectric conversion capacity and enhanced reliability and a method of fabricating the same, in which the image sensor includes a bare substrate; an epitaxial layer disposed on the bare substrate and including a first impurity distribution region of a first conductivity type, which is formed on the bare substrate, and a second impurity distribution region of a second conductivity type, which is formed on the first impurity distribution region; and a charge collection well formed within the epitaxial layer and at least partially doped with third impurities of the second conductivity type, wherein the charge collection well occupies the first impurity distribution region and the second impurity distribution region and represents the second conductivity type as a whole.

Abstract: An image pickup device includes an active pixel sensor (APS), a row driver, and a leakage current breaker. The active pixel sensor includes an array of a plurality of pixels. The row driver selects at least one pixel to be activated to output signals. The leakage current breaker decreases the leakage current through the unselected pixels by applying a leakage current breaker voltage at the bit lines of the APS array.

Abstract: An imager device is disclosed which includes at least one photosensitive element positioned on a front surface of a substrate and a conductive structure extending at least partially through an opening defined in the substrate to conductively couple to an electrical contact or bond pad on the first surface. An insulating material of a conductive laminate film and/or a mold compound material is positioned within the opening between at least a portion of the conductive structure and the substrate. Also disclosed is a device that comprises a substrate and a plurality of openings in the substrate, wherein each of the openings is adapted to be positioned above an imager device when the substrate is positioned above and secured to an imager substrate. A method of forming an imager device is also disclosed.

Abstract: A CMOS image sensor and method for fabricating the same improve image characteristics by eliminating the thickness of a planarization layer.

Abstract: A semiconductor device includes a semiconductor substrate formed with an active element, an oxidation resistant film formed over the semiconductor substrate so as to cover the active element, a ferroelectric capacitor formed over the oxidation resistance film, the ferroelectric capacitor having a construction of consecutively stacking a lower electrode, a ferroelectric film and an upper electrode, and an interlayer insulation film formed over the oxidation resistance film so as to cover the ferroelectric capacitor, wherein there are formed, in the interlayer insulation film, a first via-plug in a first contact hole exposing the first electrode and a second via-plug in a second contact hole exposing the lower electrode, and wherein there is formed another conductive plug in the interlayer insulation film in an opening exposing the oxidation resistant film.

Abstract: A semiconductor device has a ferro-electric capacitor with small leak current and less process deterioration even upon miniaturization.

Abstract: A semiconductor device includes a first inverter, a second inverter, and an inner wiring connecting the inverters, in which the inner wiring forms a capacitor element, and the capacitor element includes an interlayer insulation film having an aperture on a semiconductor substrate, a lower electrode covering a bottom wall and a side wall of the aperture, the bottom wall being the semiconductor substrate and the side wall being a part of the interlayer insulation film, a capacitor insulation film arranged on the lower electrode and a part of the interlayer insulation film, the capacitor insulation film covering corners of the capacitor insulation film, the corners being situated at opposite side of the semiconductor substrate, and an upper electrode on the capacitor insulation film, the upper electrode covering the aperture.

Abstract: It is disclosed a semiconductor device including a silicon substrate, provided with a plurality of cell active regions in a call region, an element isolation groove, formed in a portion, between any two of the plurality of cell active region, of the silicon substrate, a capacitor dielectric film, formed in the element isolation groove, a capacitor upper electrode, formed on the capacitor dielectric film, and configuring a capacitor together with the silicon substrate and the capacitor dielectric film. The semiconductor device is characterized in that a dummy active region is provided next to the cell region in the silicon substrate.

Abstract: The apparatus for working and observing samples comprises a sample plate on which a sample is to be placed; a first ion beam lens barrel capable of irradiating a first ion beam over a whole predetermined irradiation range at one time; a mask that can be arranged between the sample plate and the first ion beam lens barrel, and shields part of the first ion beam; mask-moving means capable of moving the mask; a charged particle beam lens barrel capable of scanning a focused beam of charged particles in the range irradiated with the first ion beam; and detection means capable of detecting a secondarily generated substance.

Abstract: A non-volatile memory module package capability of replacing, it may connected to a solid memory module, which includes a control unit, a system interface, and a first connector, the control unit may obtains external signals by the system interface, and then transmitted to this non-volatile memory module by the control unit to store or use the memory content. The package includes a substrate; a second connector is arranged on the substrate for inserting the first connector of the solid memory module; at least a non-volatile memory chip located on the substrate, and electrically connected the substrate and the second connector; at least a passive component is arranged on the substrate; and a compound resin is covered on the non-volatile memory chip and passive component.

Abstract: Methods are described for fabricating NAND-type EEPROMs without field oxide isolation. P+ implantations are employed to isolate adjacent memory cells.

Abstract: Flash memory devices and methods of fabricating the same are disclosed. A disclosed method comprises doping at least one active region of a substrate, and forming an etching mask layer on the active region. The etching mask layer defines an opening exposing a portion of the active region. The disclosed method further comprises forming an etching groove in the active region. The etching groove separates a source region and a drain region. The disclosed method also comprises growing an epitaxial layer within the etching groove; forming a gate insulating layer on the epitaxial layer; depositing a first polysilicon layer on inner sidewalls of the opening and on the gate insulating layer; forming a dielectric layer on the first polysilicon layer; and depositing a second polysilicon layer on the dielectric layer.

Abstract: A non-volatile memory includes a substrate, a number of isolation layers, a number of active layers, a number of floating gates, a number of control gates and a number of doped regions. The active layers are disposed in the substrate between the isolation layers, and the top surface of the active layer is higher than that of the isolation layer. The active layers and the isolation layers are arranged in parallel to each other and extend in the first direction. The control gates are disposed in the substrate. The control gates are arranged in parallel and extend in the second direction which crosses the first direction. The floating gates are disposed between the active layers and the control gates. The doped regions are disposed in the active layers between the control gates.

Abstract: A semiconductor device includes a semiconductor substrate which includes an active region defined by an isolation film, and a source region and a drain region defined in the active region and spaced apart from each other in the active region. The source region and the drain region each have a first conductivity type. The semiconductor device further includes an island region defined in the active region between the source region and the drain region. The island region has the first conductivity type.

Abstract: A process manufactures a multi-drain power electronic device integrated on a semiconductor substrate of a first type of conductivity whereon a drain semiconductor layer is formed. The process includes: forming a first semiconductor epitaxial layer of the first type of conductivity of a first value of resistivity forming the drain epitaxial layer on the semiconductor substrate, forming first sub-regions of a second type of conductivity by means of a first selective implant step with a first implant dose, forming second sub-regions of the first type of conductivity by means of a second implant step with a second implant dose, forming a surface semiconductor layer wherein body regions of the second type of conductivity are formed being aligned with the first sub-regions, carrying out a thermal diffusion process so that the first sub-regions form a single electrically continuous column region being aligned and in electric contact with the body regions.

Abstract: A method is provided for forming a low-temperature vertical gate insulator in a vertical thin-film transistor (V-TFT) fabrication process. The method comprises: forming a gate, having vertical sidewalls and a top surface, overlying a substrate insulation layer; depositing a silicon oxide thin-film gate insulator overlying the gate; plasma oxidizing the gate insulator at a temperature of less than 400° C., using a high-density plasma source; forming a first source/drain region overlying the gate top surface; forming a second source/drain region overlying the substrate insulation layer, adjacent a first gate sidewall; and, forming a channel region overlying the first gate sidewall, in the gate insulator interposed between the first and second source/drain regions. When the silicon oxide thin-film gate insulator is deposited overlying the gate a Si oxide layer, a low temperature deposition process can be used, so that a step-coverage of greater than 65% can be obtained.

Abstract: Unit cells of metal oxide semiconductor (MOS) transistors are provided having an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is between the source region and the drain region. A channel region is provided between the source and drain regions. The channel region has a recessed region that is lower than bottom surfaces of the source and drain regions. Related methods of fabricating transistors are also provided.

Abstract: A charge storage layer of first conductive type is formed on the first principal surface of a semiconductor substrate. A base layer of second conductive type is formed on the charge storage layer. Each trench formed through the base layer and the charge storage layer is lined with an insulating film and filled with a trench gate electrode. Dummy trenches are formed on both sides of each trench. Source layers of first conductive type are selectively formed in the surface of the base layer and in contact with the sidewalls of the trenches. The source layers are spaced apart from each other and arranged in the longitudinal direction of the trenches. A contact layer of second conductive type is formed in the surface of the base layer and between each two adjacent source layers arranged in the longitudinal direction of the trenches. A collector layer of second conductive type is formed on the second principal surface of the semiconductor substrate.

Abstract: A semiconductor device includes a semiconductor substrate including an NMOS region and a PMOS region, a device isolation structure formed on the semiconductor substrate to define an active region, a recess channel structure formed in the active region, a gate insulating film disposed in the recess channel structure, and a gate including an undoped amorphous silicon layer formed over the gate insulating film, the gate filling the recess channel structure.

Abstract: A semiconductor device includes a semiconductor substrate including an NMOS region and a PMOS region, active regions of the semiconductor substrate defined by a device isolation structure formed in the semiconductor substrate, the active regions including an NMOS active region defined in the NMOS region and a PMOS active region defined in the PMOS region, a gate insulating film disposed over the active regions, and a dual poly gate including an amorphous titanium layer formed over the gate insulating film in the NMOS region and the PMOS region. The dual poly gate includes a stacked structure having a lower gate electrode formed of an impurity doped polysilicon layer, a barrier layer including the amorphous titanium layer, and an upper gate electrode formed of a tungsten layer.

Abstract: Low voltage, middle voltage and high voltage CMOS devices have upper buffer layers of the same conductivity type as the sources and drains that extend under the sources and drains and the gates but not past the middle of the gates, and lower bulk buffer layers of the opposite conductivity type to the upper buffer layers extend from under the upper buffer layers to past the middle of the gates forming an overlap of the two bulk buffer layers under the gates. The upper buffer layers and the lower bulk buffer layers can be implanted for both the NMOS and PMOS FETs using two masking layers. For middle voltage and high voltage devices the upper buffer layers together with the lower bulk buffer layers provide a resurf region.

Abstract: A Schottky diode is integrated into a planar or trench topology MOSFET having parallel spaced source regions diffused into spaced base stripes. The diffusions forming the source and base stripes are interrupted to permit the drift region to extend to the top of the die and receive a Schottky barrier metal and the source contact. The MOSFET and Schottky share the same drift region, and the pitch between base and source stripes is not changed to receive the Schottky structure.

Abstract: A method for fabricating a semiconductor device is provided. A first insulation layer and a second insulation layer are formed over the substrate having a gate. A spacer etching process is performed to form an etched first insulation layer and an etched second insulation layer. The etched first insulation layer partially protrudes from the substrate and contacts sidewalls of the gate. The etched second insulation layer is removed through a selective epitaxial growth (SEG) process that forms an epitaxial layer over the exposed substrate. One of facets of the epitaxial layer is formed on the protruding portion of the etched first insulation layer. A third insulation layer is formed on sidewalls of the etched first insulation layer and the one of the facets of the epitaxial layer is covered by the third insulation layer.