Abstract: A semiconductor device including a capacitor which includes a first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode, the dielectric layer including: a first paraelectric film formed of a material containing a first metal element and at least one kind of second metal element; a second paraelectric film disposed between the first electrode and the first paraelectric film; and a third paraelectric film disposed between the second electrode and the first paraelectric film, wherein the second paraelectric film is formed of a material containing the first metal element but substantially not containing the second metal element, and the third paraelectric film is formed of a material containing the first metal element but substantially not containing the second metal element.

Abstract: A capacitor includes a lower electrode, a first dielectric layer formed over the lower electrode, a second dielectric layer formed over the first dielectric layer, wherein the second dielectric layer includes an amorphous high-k dielectric material, a third dielectric layer formed over the second dielectric layer, and an upper electrode formed over the third dielectric layer.

Abstract: A first insulation film is provided on a semiconductor substrate. A high resistance element formed from polysilicon is provided on the first insulation film. A second insulation film is provided on the high resistance element. A hydrogen diffusion preventing film having a hydrogen diffusion coefficient smaller than that of the second insulation film is provided on the second insulation film. The hydrogen diffusion preventing film covers a part of the high resistance element.

Abstract: A lateral bipolar transistor is described, including a semiconductor substrate, a gate structure on the substrate, an emitter and a collector of a first conductivity type in the substrate, and a base of a second conductivity type in the substrate. The gate structure has a structure enclosing one or more closed areas. The emitter and the collector respectively includes a plurality of electrically connected unit emitters and a plurality of electrically connected unit collectors defined by the gate structure, which are arranged laterally intermixing with each other and separated by the substrate under the gate structure. The base includes a part under the gate structure.

Abstract: Provided are semiconductor devices and methods of forming the same. The semiconductor devices include a substrate further including a hydrogen implantation layer and a gate structure formed on the hydrogen implantation layer to include a first insulating layer, a charge storage layer, a second insulating layer and a conductive layer.

Abstract: To provide a nitride semiconductor single crystal substrate comprising a Si substrate and a nitride semiconductor film which has semi-polar (10-1m) plane (m: natural number) and a thickness of 1 ?m or more, the nitride semiconductor single crystal substrate being suitably used for a light-emitting device, the nitride semiconductor single crystal substrate being suitably used for a light-emitting device, this invention provides a nitride semiconductor single crystal substrate comprising a Si substrate having an off-cut angle of 1 to 35° in the <110> direction from the <100> direction, a buffer layer 2a (2b) made of at least one of SiC or BP formed on the Si substrate, a AlN buffer layer formed on the buffer layers, and a nitride semiconductor single crystal film formed on the AlN buffer layer, the nitride semiconductor single crystal film comprising any one of GaN (10-1m), AlN (10-1m), InN (10-1m) or a GaN (10-1m)/and AlN (10-1m) superlattice film.

Abstract: An embodiment of a semiconductor device includes a semiconductor substrate, a first insulating layer formed over the semiconductor substrate, and a first semiconductor layer formed over the first insulation layer. At least one gettering region is formed in at least one of the first insulating layer and the first semiconductor layer. The gettering region includes a plurality of gettering sites, and at least one gettering site includes one of a precipitate, a dispersoid, an interface with the dispersoid, a stacking fault and a dislocation.

Abstract: A semiconductor wafer for an epitaxial growth is disclosed comprising: a main face on which a vapor phase epitaxial layer grows; a back face provided on an opposite side of the wafer; a main chamfered part along a circumferential edge where the main face and a side face of the wafer meet; and a back chamfered part along a circumferential edge where the back face and the side face meet is provided. After a CVD layer formation process is conducted to form a layer at least on the back face and the back chamfered part, a machining process is conducted on the main face to remove a CVD layer at least partially formed thereon so as to polish the main face to a mirror finished surface with a maximum height of profile (Rz) not exceeding 0.3 ?m.

Abstract: Passivation films 3a, 3b are formed to cover both surfaces of semiconductor substrate 1 which comprises terminal pads 2a, 2b on both surfaces. Openings 3c, 3d are provided at positions on passivation films 3a, 3b which match with terminal pads 2a, 2b. Throughholes 9 are formed inside of openings 3c, 3d to extend through terminal pad 2a, semiconductor substrate 1, and terminal pad 2b. Insulating layer 4 made of SiO2, SiN, SiO, or the like is formed on the inner surfaces of throughholes 9. Buffer layer 5 made of a conductive adhesive is formed to cover insulating layer 4 and terminal pads 2a, 2b in openings 3c, 3d. Further, conductive layer 6 made of a metal film is formed on buffer layer 5 by electrolytic plating, non-electrolytic plating, or the like.

Abstract: An active structure of a semiconductor device. In one aspect, the active structure of the semiconductor device includes first to (n)th field regions, and first to (n+1)th active regions formed alternately with the first to (n)th field regions, wherein one or more of the first to (n+1)th active regions are connected at edge portions thereof to close one or more of the field regions. In another aspect, the active structure of the semiconductor device includes first to (n)th field regions, and first to (n+1)th active regions formed alternately with the first to (n)th field regions, wherein the first and (n+1)th active regions are connected to (n+2)th and (n+3)th active regions at edge portions thereof, closing the field regions.

Abstract: A structure and method for removing damages of a dual damascene structure after plasma etching. The method includes the use of sublimation processes to deposit reactive material onto the damaged regions and conditions to achieve a controlled removal of the damaged region. Furthermore a semiconductor structure includes a dual damascene structure that has been treated by the method.

Abstract: To achieve high performance of a semiconductor integrated circuit depending on not only a microfabrication technique but also another way. In addition, to achieve low power consumption of a semiconductor integrated circuit. A semiconductor device is provided in which crystal faces and/or crystal axes of single-crystalline semiconductor layers of a first conductive MISFET and a second conductive MISFET are different. The crystal faces and/or crystal axes are arranged so that mobility of carriers flowing in channel length directions in the respective MISFETs is increased. Such a structure can increase mobility of carriers flowing through channels of the MISFETs and high speed operation of a semiconductor integrated circuit can be achieved. Further, low voltage driving becomes possible, and low power consumption can be realized.

Abstract: A semiconductor device includes bit lines provided in a semiconductor substrate; an ONO film that is provided along the surface of the semiconductor substrate and is made of a tunnel oxide film, a trap layer, and a top oxide film; and an oxide film that is provided on the surface of the semiconductor substrate in the middle between the bit lines and contacts the side face of the ONO film, in which the film thickness of the oxide film is larger than the sum of the thicknesses of the tunnel oxide film and the top oxide film, and smaller than the thickness of the ONO film.

Abstract: The present invention provides a package structure and a method for forming the same; wherein the structure comprises a substrate with certain open through holes filled with conducting metals for performing electrical connection or heat dissipation, a chip with bonding pads attached on the contacting pad by an adhesive with high thermal conductivity, wire bounded the contacting pad and the chip pad, a protection layer covered on the chip, wire and a portion of pad by molding or dispensing and a solder ball disposed on the pad. The advantages of the present invention are: the structure is reduced; the heat dissipation of the structure is enhanced; the structure can form package on package structure; the pads provides better ground shielding, heat dissipation of the structure.

Abstract: A method of fabricating a chip package is provided. A thin metal plate having a first protrusion part, a second protrusion part and a plurality of third protrusion parts are provided. A chip is disposed on the thin metal plate, and a plurality of bonding wires for electrically connecting the chip to the second protrusion part and the second protrusion part to the third protrusion parts is formed. An upper encapsulant and a lower encapsulant are formed on the upper surface and the lower surface of the thin metal plate respectively. The lower encapsulant has a plurality of recesses for exposing a portion of the thin metal plate at locations where the first protrusion part, the second protrusion part and the third protrusion parts are connected to one another. Finally, the thin metal plate is etched by using the lower encapsulant as an etching mask.

Abstract: An inductor, a semiconductor component including the inductor, and a method of manufacture. A leadframe has a plurality of conductive strips and a flag. A ferrite core is mounted on a die attach material disposed on the conductive strips and a semiconductor die is mounted on a die attach material disposed on the flag. Wire bonds are formed from the conductive strips on one side of the ferrite core to corresponding conductive strips on an opposing side of the ferrite core. The wire bonds and the conductive strips cooperate to form the coil of the inductor. Wire bonds electrically couple one end of the inductor to leadframe leads adjacent the semiconductor die. Wire bonds couple bond pads on the semiconductor die to the leadframe leads coupled to the inductor. An encapsulant is formed around the inductor and the semiconductor die. Alternatively, a stand-alone inductor is manufactured.

Abstract: A die assembly includes a die mounted to a support, in which the support has interconnect pedestals formed at bond pads, and the die has interconnect terminals projecting beyond a die edge into corresponding pedestals. Also, a support has interconnect pedestals. Also, a method for electrically interconnecting a die to a support includes providing a support having interconnect pedestals formed at bond pads on the die mount surface of the support, providing a die having interconnect terminals projecting beyond a die edge, positioning the die in relation to the support such that the terminals are aligned with the corresponding pedestals, and moving the die and the support toward one another so that the terminals contact the respective pedestals.

Abstract: To solve a problem in that a die processing cost increases when employing a method involving providing a suction hole in the die to fix an island onto a bottom surface, provided is a semiconductor device, which includes: a semiconductor chip, an island having a first surface, on which the semiconductor chip is mounted; and a second surface opposing to the first surface, a hanger pin extended from the island, a branch portion extended from one of the island and the hanger pin, and a resin encapsulating the semiconductor chip, the island, the hanger pin and the brunch portion while exposing the second surface of the island.

Abstract: A semiconductor device comprises: a semiconductor chip; a first frame; a solder layer which bonds the solder bonding metal layer of the semiconductor chip and the first frame; and a second frame bonded to the rear face of the semiconductor chip. The semiconductor chip includes: a semiconductor substrate; a first metal layer provided on a major surface of the semiconductor substrate and forming a Schottky junction with the semiconductor substrate; a second metal layer provided on the first metal layer and primarily composed of aluminum; a third metal layer provided on the second metal layer and primarily composed of molybdenum or titanium; and a solder bonding metal layer provided on the third metal layer and including at least a forth metal layer which is primarily composed of nickel, ion or cobalt.

Abstract: A technique for preventing cracks and residual resin on a semiconductor chip in a molding process in the assembly of semiconductor devices is provided. A distance from a bottom surface of a cavity of a lower mold die to a ceiling surface of a cavity of an upper mold die of a resin molding die is made same as or smaller than a distance from a lower surface of a die pad to an upper surface of a plate terminal, and an U-shape elastic body is arranged on semiconductor elements between the plate terminal and the die pad, thereby mitigating a load due to a clamp pressure of mold dies in the molding process by an elastic deformation of the elastic body. Consequently, a load applied on the semiconductor devices is reduced, thereby preventing formation of cracks on the semiconductor elements.

Abstract: A leadframe-based semiconductor package and a fabrication method thereof are provided. The leadframe-based semiconductor package includes a chip implanted with a plurality of first and second conductive bumps thereon, and a leadframe having a plurality of leads. The first conductive bumps are bonded to the leads to electrically connect the chip to the leadframe. The chip, the first and second conductive bumps, and the leadframe are encapsulated by an encapsulant, with bottom ends of the second conductive bumps and bottom surfaces of the leads being exposed from the encapsulant. This allows the second conductive bumps to provide additional input/output electrical connections for the chip besides the leads.

Abstract: A chip package structure mainly including a substrate, a chip and a lead frame is provided. The chip is disposed on the substrate, and is electrically connected to the chip by flip-chip or wire-bonding technique. The chip is electrically connected to the lead frame through a redistribution layer on the substrate. Therefore, a problem that the bonding wires may collapse due to a longer distance between the chip and the lead frame may be resolved, thus improving the yield rate thereof.

Abstract: Provided are a power module having a stacked flip-chip and a method of fabricating the power module. The power module includes a lead frame; a control device part including a control device chip; a power device part including a power device chip and being electrically connected to the lead frame; and an interconnecting substrate of which the control and power device parts are respectively disposed at upper and lower portions, and each of the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method.

Abstract: A semiconductor package that includes a die with electrodes on opposite surfaces thereof and respective conductive clip electrically and mechanically coupled to the electrode and configured for vertical mounting of the package.

Abstract: Using one or more reference indicators in die attaching an optoelectronic device to a lead during the assembly of an optoelectronic package. One example method of assembling an optoelectronic package includes detecting a reference indicator included in a first component of an optoelectronic package. The method also includes die attaching a second component to the optoelectronic package at a die attach location. The die attach location is substantially aligned with the reference indicator along a line that intersects the reference indicator and is parallel to either an x-axis or a y-axis of an x-y coordinate system associated with the optoelectronic package.

Abstract: A portable object connectable package 1, 11, 21, 31, 41, 51, 61, 71, 81 for an electronic device comprises: —a semiconductor die package 2, 12, 22, 32, 42, 52, 62, 72, 82 comprising a top surface 2A, 12A, 22A, 32A, 42A, 52A, 62A, 72A, 82A and an opposite bottom surface 2B, 12B, 22B, 32B, 42B, 52B, 62B, 72B, 82B, the bottom surface comprising a plurality of connection elements 3A, 13A, 23A, 33A, 43A, 53A, 63A, 73A, 83A for connecting to a printed circuit board PCB, and—a connector body 4, 14, 24, 34, 44, 54, 64, 74, 84 mechanically supported by the semiconductor die package and comprising a plurality of resilient electrical connecting elements extending over the top surface for contacting with a portable object PO, said circuit comprising a contacting area PO1.

Abstract: A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires.

Abstract: A leadframe with a structure made of a base metal (105), wherein the structure has a plurality of surfaces. On each of these surfaces are metal layers in a stack adherent to the base metal. The stack comprises a nickel layer (201) in contact with the base metal, a palladium layer (202) in contact with the nickel layer, and an outermost tin layer (203) in contact with the palladium layer. In terms of preferred layer thicknesses, the nickel layer is between about 0.5 and 2.0 ?m thick, the palladium layer between about 5 and 150 nm thick, and the tin layer less than about 5 nm thick, preferably about 3 nm. At this thinness, the tin has no capability of forming whiskers, but offers superb adhesion to polymeric encapsulation materials, improved characteristics for reliable stitch bonding as well as affinity to reflow metals (solders).

Abstract: Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member proximate to the semiconductor die. The support member is at least substantially rigid. The packages can further include an adhesive between the support member and the semiconductor die and adhesively attaching the support member to the semiconductor die. The packages can also include a substrate carrying the semiconductor die and the support member attached to the semiconductor die.

Abstract: A device is disclosed which includes an interposer, at least one capacitor formed at least partially within an opening formed in the interposer and an integrated circuit that is operatively coupled to the interposer. A method is disclosed which includes obtaining an interposer having at least one capacitor formed at least partially within an opening in the interposer and operatively coupling an integrated circuit to the interposer. A method is also disclosed which includes obtaining an interposer comprising a dielectric material, forming an opening in the interposer and forming a capacitor that is positioned at least partially within the opening.

Abstract: A method includes the steps of providing a carrier comprising a plurality of cavities; placing at least one semiconductor element into each of the cavities; filling the plurality of cavities with a packaging material; and removing the carrier.

Abstract: A multi-chip package with a single die pad is provided. The multi-chip package includes a leadframe having a die pad and a plurality of leads surrounding the die pad. Each of the leads includes an upper lead, a lower lead and an intermediate lead substantially perpendicularly connected to the upper and lower leads, wherein the upper and lower leads are substantially parallel to the die pad. The upper and lower surfaces of the die pad are attached with upper and lower chips respectively. The upper chip is electrically connected to the upper surface of one part of the upper leads by a plurality of first bonding wires and the lower chip is electrically connected to the lower surfaces of the other part of the upper leads by a plurality of second bonding wires. A sealant is used to encapsulate the chips and bonding wires to protect these elements from damage.

Abstract: A package structure with chip embedded therein is disclosed, which comprises a circuit board having a first surface, an opposite second surface and a through cavity penetrating the circuit board, wherein the first surface of the circuit board has a plurality of first conductive pads and a plurality of wire bonding pads disposed thereon, and the second surface of the circuit board has a plurality of second conductive pads disposed thereon; and a chip embedded in the through cavity of the circuit board, wherein the gap between the through cavity and the chip is filled with a filling material, the chip has an active surface with a plurality of electrode pads and an inactive surface, and the electrode pads electrically connect to the wire bonding pads of the circuit board by a plurality of metal lines. The present invention further provides a package module using the aforementioned package structure.

Abstract: A panel with a reconfigured wafer including semiconductor chips arranged in rows and columns on semiconductor device positions includes: at least one semiconductor chip having a front, a rear and edge sides provided per semiconductor device position. The reconfigured wafer includes: a front side that forms a coplanar area with the front sides of the at least one semiconductor chip and a plastic housing composition embedding the edge sides and the rear side of the at least one semiconductor chip. The reconfigured wafer includes, on a rear side of the wafer, structures configured to stabilize the panel. The structures are composed of the plastic housing composition and are formed as thickenings of the reconfigured wafer.

Abstract: An apparatus comprises a device layer structure, a device integrated into the device layer structure, an insulating carrier substrate and an insulating layer being continuously positioned between the device layer structure and the insulating carrier substrate, the insulating layer having a thickness which is less than 1/10 of a thickness of the insulating carrier substrate. An apparatus further comprises a device integrated into a device layer structure disposed on an insulating layer, a housing layer disposed on the device layer structure and housing the device, a contact providing an electrical connection between the device and a surface of the housing layer opposed to the device layer structure and a molding material surrounding the housing layer and the insulating layer, the molding material directly abutting on a surface of the insulating layer being opposed to the device layer structure.

Abstract: Packaged semiconductor components, apparatus for packaging semiconductor devices, methods of packaging semiconductor devices, and methods of manufacturing apparatus for packaging semiconductor devices. One embodiment of an apparatus for packaging semiconductor devices comprises a first board having a front side, a backside, arrays of die contacts, arrays of first backside terminals electrically coupled to the die contacts, arrays of second backside terminals, and a plurality of individual package areas that have an array of the die contacts, an array of the first backside terminals, and an array of the second backside terminals.

Abstract: A base substrate for chip scale package includes a carrier member made of electrical conductive metals with a first through opening; an active member laminated by a base layer made of electrical conductive metal and an intermediate layer made of electrical insulating or dielectric material, the active member having a through opening with a diameter larger that the diameter of the through opening of the base metal member; the active member being coupled with the carrier member in such a way that the intermediate layer is adhered to an upper surface of the carrier member, and these through openings are aligned to define a shoulder around the through opening of the base metal plate.

Abstract: A semiconductor module has at least two semiconductor chips (4, 5) with at least one first and one second electrode (12, 13) on their first sides. Each semiconductor chip (4, 5) has a third electrode (14) on its second side (16). A chip arrangement within the semiconductor module (1) is provided such that the electrodes (12, 13) on the first sides of the semiconductor chips (4, 5) are oriented toward a second side of the semiconductor module (1) and the third electrodes (14) on the second sides (16) of the semiconductor chips (4, 5) are oriented toward a first side of the semiconductor module (1). For this purpose, external terminals (19, 20) on the second side of the semiconductor module (1) are directly coupled to the electrodes (12, 13) of the first sides and connecting elements (22) electrically couple the third electrodes (14) to corresponding external terminals (21).

Abstract: A lead structure for a semiconductor component includes: external leads for external connections outside a plastic housing composition, internal leads for electrical connections within the plastic housing composition, and a chip mounting island composed of the lead material. While leaving free contact pads of the internal leads, the top sides of the chip mounting island and the internal leads are equipped with nanotubes as an anchoring layer. The plastic housing composition is arranged in the interspaces between the nanotubes arranged on the internal leads, while an adhesive composition for the semiconductor chip is arranged in the interspaces between the nanotubes arranged on the chip mounting island. The adhesive composition and the plastic housing composition fill the interspaces in a manner free of voids.

Abstract: A module includes a semiconductor chip and a conductive layer arranged over the semiconductor chip. The module also includes a spacer structure arranged to deflect the conductive layer away from the semiconductor chip.

Abstract: A power semiconductor module with its thermal resistance and overall size reduced. Insulating substrates with electrode metal layers disposed thereon are joined to both the surfaces of a power semiconductor chip by using, for example, soldering. Metal layers are disposed also on the reverse surfaces of the insulating substrates and the metal layers are joined to the heat spreaders by using brazing. Heat radiating fins are provided on the heat radiating surface of at least one of the heat spreaders. The heat radiating side of each of the heat spreaders is covered by a casing to form a refrigerant chamber through which refrigerant flows to remove heat transmitted from the semiconductor chip to the heat spreader.

Abstract: A semiconductor device includes: a semiconductor chip; a package for accommodating the chip, wherein the package has a box shape with an opening and a bottom; and a cover for sealing the opening of the package. The semiconductor chip is disposed on the bottom of the package. The cover has a plate shape. The cover includes a protrusion, which is disposed at a center of the plate shape. The protrusion protrudes toward an outside of the package.

Abstract: According to one embodiment, a die assembly is disclosed, comprising a package substrate and a plurality of stacked die on the package substrate, the plurality of stacked die including at least an uppermost die, a lowermost die, and at least one phase change memory die between the uppermost die and the lowermost die, wherein the uppermost die and lowermost die are non-functional spacer die.

Abstract: The present invention provides a structure of multi-chips package comprising: a substrate with a die receiving cavity formed within an upper surface of the substrate and a first through holes structure, wherein terminal pads are formed under the first through holes structure. A first die is disposed within the die receiving cavity and a first dielectric layer is formed on the first die and the substrate. A first re-distribution conductive layer (RDL) is formed on the first dielectric layer. A second dielectric layer is formed over the first RDL. A third dielectric layer is formed under a second die. A second re-distribution conductive layer (RDL) is formed under the third dielectric layer. A fourth dielectric layer is formed under the second RDL. Conductive bumps are coupled to the first RDL and the second RDL. A surrounding material surrounds the second die. The second die is coupled to the first die through the first RDL, second RDL and the conductive bumps.

Abstract: According to one exemplary embodiment, a semiconductor die with on-die preferred interface selection includes at least two groups of pads situated on an active surface of the semiconductor die, where each of the at least two groups of pads is coupled to its associated interface in the die. A set of bumps is mask-programmably routed to one of the at least two groups of pads, thereby selecting the preferred interface for the semiconductor die. A non-preferred interface is not routed to any bumps on the active surface of the semiconductor die, thereby reducing bump count on the die. Each of the at least two groups of pads can be situated in a corresponding pad ring on the active surface of said semiconductor die. The at least two groups of pads can be laid out substantially inline.

Abstract: Provided is a semiconductor device including a substrate, an electrode pad disposed on the substrate, an external terminal disposed on the electrode pad, a container extended from the electrode pad into the external terminal, and a conductive liquid disposed inside the container. The conductive liquid solidifies when exposed to air. When a crack forms in the external terminal, the container suppresses propagation of the crack. Further, if the crack breaches the container, the conductive liquid fills the crack, thereby minimizing further crack propagation and recovering the resistance characteristics of the external terminal prior to the crack formation. A method of forming a semiconductor device including a container having a conductive liquid is also provided.

Abstract: The connection technology is provided in which, at the time of mounting the semiconductor device on the substrate, the thermal load or the stress, which is imposed upon the semiconductor device, is little, a reliability of the semiconductor device is obtained, a stand-off of the semiconductor device mounted on the substrate can be secured appropriately, and moreover the short circuit hardly occurs between the pads of the semiconductor device mounted on the substrate. The semiconductor device mounted on the substrate, in which the substrate includes an electrode pad, the semiconductor device includes an electrode pad, the electrode pad of the semiconductor device and the electrode pad of the substrate are connected with a conductive adhesive, and a spacer is provided between the semiconductor device and the substrate.

Abstract: A method for manufacturing a semiconductor device includes: preparing a wiring board having a base substrate and wiring that is plated on surface with a plating metal; pressing a bump that is formed on the active side of the semiconductor chip against an end part of the wiring of the wiring board, thereby exfoliating the area surrounding the pressed portion of the wiring from the base substrate while keeping the end of the wiring bonded with the base substrate; melting the plating metal that is located on the end part of the wiring, thereby causing the plating metal and the bump to form an alloy that bonds the bump and the wiring and infiltrate the plating metal into a space between the wiring and the base substrate; and judging that the bump and the wiring are well bonded if the plating metal has infiltrated a space between the wiring and the base substrate so as to have an area, width or length of infiltration that exceeds a reference value.

Abstract: A semiconductor device is disclosed including a data family pad layout wherein an effort is made to contrive layouts of a power lead wire and a ground lead wire to minimize effective inductance in priority to a length of a lead wire between a pad and a solder ball land of a semiconductor chip. Pad layouts are arrayed in two rows and one unit of the pad layout is configured such that a data power source and ground are adjacent to each other or one data is inserted between the data power source and the ground. Such configurations decrease mutual inductance between the data power sources and increase mutual inductance between the data power source and the ground causing reduction in effective inductance between the data power source and the ground with the resultant minimization of power and ground noises.

Abstract: A device and a method for bonding elements are described. A first solder ball is produced on a main surface of a first element. A second solder ball is produced on a main surface of a second element. Contact is provided between the first solder ball and the second solder ball. The first and second elements are bonded by applying a reflow act whereby the solder balls melt and form a joined solder ball structure. Prior to the bonding, the first solder ball is laterally embedded in a first layer of non-conductive material and the second solder ball is laterally embedded in a second layer of non-conductive material, such that the upper part of the first solder ball and upper part of the second solder ball are not covered by the non-conductive material. A third solder volume is applied on one or both of the embedded first or second solder balls, prior to the bonding.