Abstract: Provided is an electronic device, a field effect transistor having the electronic device, and a method of manufacturing the electronic device and the field effect transistor. The electronic device includes: a substrate; a first electrode and a second electrode which are formed in parallel to each other on the substrate, each of the first electrode and the second electrode comprising two electrode pads separated from each other and a heating element that connect the two electrode pads; a catalyst metal layer formed on the heating element of the first electrode; and a carbon nanotube connected to the second electrode by horizontally growing from the catalyst metal layer; wherein the heating elements are separated from the substrate by etching the substrate under the heating elements of the first and the second electrodes.

Abstract: An organic light-emitting display panel having a storage capacitor comprised of a storage electrode overlapping a power line with a first gate-insulating layer disposed therebetween, wherein the storage capacitor includes a groove portion formed on a lateral side of the power line overlapping the storage electrode so that the overlapping area of the power line and the storage electrode is kept constant, and a method of manufacturing the same.

Abstract: It is made possible to provide a thin film transistor having transistor characteristics that do not widely vary. A thin film transistor includes: a substrate; a pair of insulating layers formed at a distance from each other on the substrate; a source electrode formed on one of the insulating layers, and a drain electrode formed on the other one of the insulating layers; a semiconductor layer formed to cover the source electrode, the drain electrode, and the substrate; a gate insulating film formed on the semiconductor layer; and a gate electrode formed on the gate insulating film.

Abstract: A method of manufacturing a display device includes a step of forming an island-shaped first electrode, a step of forming a first insulation film, a step of forming a second insulation film, a step of removing the first insulation film, which is exposed from the second insulation film, in a self-alignment manner by using the second insulation film as a mask, a step of coating a liquid-phase material on the first electrode which is exposed from the first insulation film, and then drying the liquid-phase material, thus forming an organic active layer, and a step of forming a second electrode on the organic active layer. The first insulation film has higher lyophilic properties to the liquid-phase material for forming the organic active layer than the second insulation film.

Abstract: The present invention is directed to methods for patterning substrates using contact printing processes and inks comprising an organic semiconductive or semiconductive polymer, inks for use with the processes, and products formed by the processes.

Abstract: An organic thin-film transistor manufacturing method and an organic thin-film transistor manufactured by the method are disclosed, the method comprising the steps of a) forming a gate electrode on a substrate, b) forming a gate insulating layer on the substrate, c) forming an organic semiconductor layer on the substrate, d) forming an organic semiconductor layer protective layer on the organic semiconductor layer, e) removing a part of the organic semiconductor layer protective layer, and f) forming a source electrode and a drain electrode at portions where the organic semiconductor layer protective layer has been removed, so that the source electrode and drain electrode contacts the organic semiconductor layer.

Abstract: An organic light emitting display device and a method for manufacturing the same are disclosed. The method for manufacturing the organic light emitting display device includes forming a switching element and a silicon nitride layer over a substrate, patterning and removing a portion of the silicon nitride layer formed on a light emitting region through which light is transmitted, forming an overcoat layer formed on the silicon nitride layer, wherein a portion of the overcoat layer corresponding to the light emitting region has a thickness of about 1.1 ?m to about 2.1 ?m, forming a first electrode electrically connected to the switching element over the light emitting region, and sequentially forming an organic light emitting layer and a second electrode on the first electrode.

Abstract: The invention relates to an organic semiconductor material with a high carrier mobility, which is capable of obtaining favorable semiconductor characteristics when used in an organic semiconductor device, and an organic transistor using the same. More specifically, the present invention has a following structure including an oligothiophene part and a connecting part G; where, R1 and R2 are a hydrogen, a alkyl group, an alkoxy group, an aryl group, or an alkenyl group, R1 and R2 may be identical or different from each other, and where n is an integer. In the organic semiconductor material, the structure of the connecting part G may be any of the following: where, R3 and R4 are a hydrogen, an alkyl group, an alkoxy group, an aryl group, or a alkenyl group, R3 and R4 may be identical or different from each other, and where n is an integer of 1 to 3.

Abstract: The invention relates to a method of making an organic electronic device and articles.

Abstract: An organic semiconductor device having a gate electrode, a source electrode, a drain electrode, an organic semiconductor layer, a gate insulation layer, and a substrate. The substrate of the semiconductor device having an underlayer including an organic polymer material having a liquid crystal core. The underlayer is oriented in a specific direction formed between the substrate and the organic semiconductor layer so as to orient the organic semiconductor layer along the orientation of the underlayer.

Abstract: Novel articles and methods to fabricate the same resulting in flexible, large-area, [100] or [110] textured, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

Abstract: An object of the present invention is to provide a Group III nitride semiconductor multilayer structure having a smooth surface and exhibiting excellent crystallinity, which multilayer structure employs a low-cost substrate that can be easily processed. Another object is to provide a Group III nitride semiconductor light-emitting device comprising the multilayer structure. The inventive Group III nitride semiconductor multilayer structure comprises a substrate; an AlxGa1-xN (0?x?1) buffer layer which is provided on the substrate and has a columnar or island-like crystal structure; and an AlxInyGa1-x-yN (0?x?1, 0?y?1, 0?x+y?1) single-crystal layer provided on the buffer layer, wherein the substrate has, on its surface, non-periodically distributed grooves having an average depth of 0.01 to 5 ?m.

Abstract: A substrate is set at a predetermined temperature in a plasma treatment chamber, then the inside of the plasma treatment chamber is regulated at a reduced pressure containing at least a silicon hydride gas and a hydrogen gas, a high-frequency electric field is applied to form a silicon film of nanometer scale thickness composed of fine silicon crystals and amorphous silicon on the substrate. Thereafter, application of the high-frequency electric field is terminated, then the inside of the plasma treatment chamber is replaced by an oxidizing or nitriding gas, and a high-frequency electric field is applied again for plasma oxidizing treatment or plasma nitriding treatment of the silicon film formed on the substrate. Thereby, a silicon nanocrystalline structure can be formed on a silicon substrate by using a process of producing silicon integrated circuits with achieving high luminous efficiency, and terminating reliably with oxygen or nitrogen on the surface thereof.

Abstract: A device for generating a plurality of electron-hole pairs from a photon is disclosed. The device includes a substrate, a first electrode formed above the substrate, and a first doped Group IV nanoparticle thin film deposited on the first electrode. The device further includes an intrinsic layer deposited on the first doped Group IV nanoparticle thin film, wherein the intrinsic layer includes a matrix material with a melting temperature T1, wherein T1 is greater than about 300° C., and a set of quantum confined nanoparticles each with a melting temperature T2, wherein T2 is less than about 900° C., wherein the melting temperature T1 is less than the melting temperature T2.

Abstract: An image sensor and a method for manufacturing the same are provided. The image sensor can include: a semiconductor substrate including a circuit area; a metal interconnection layer including a metal interconnection and a an interlayer dielectric layer on the semiconductor substrate; a first conductive-type pattern on the metal interconnection layer; an intrinsic layer pattern having a dome-like shape on the first conductive-type pattern; and a second conductive-type conductive layer on the metal interconnection layer including the intrinsic layer pattern.

Abstract: A circuit includes an input drain, source and gate nodes. The circuit also includes a group III nitride depletion mode FET having a source, drain and gate, wherein the gate of the depletion mode FET is coupled to a potential that maintains the depletion mode FET in its on-state. In addition, the circuit further includes an enhancement mode FET having a source, drain and gate. The source of the depletion mode FET is serially coupled to the drain of the enhancement mode FET. The drain of the depletion mode FET serves as the input drain node, the source of the enhancement mode FET serves as the input source node and the gate of the enhancement mode FET serves as the input gate node.

Abstract: A semiconductor device is provided that includes a substrate, a first active layer disposed over the substrate, and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A termination layer, which is disposed on the second active layer, includes InGaN. Source, gate and drain contacts are disposed on the termination layer.

Abstract: A transistor device capable of high performance at high temperatures. The transistor comprises a gate having a contact layer that contacts the active region. The gate contact layer is made of a material that has a high Schottky barrier when used in conjunction with a particular semiconductor system (e.g., Group-III nitrides) and exhibits decreased degradation when operating at high temperatures. The device may also incorporate a field plate to further increase the operating lifetime of the device.

Abstract: The silicon carbide semiconductor device includes a trench formed from a surface of a drift layer of a first conductivity type formed on a substrate of the first conductivity type, and a deep layer of a second conductivity type located at a position in the drift layer beneath the bottom portion of the trench. The deep layer is formed at a certain distance from base regions of the second conductivity type formed on the drift layer so as to have a width wider than the width of the bottom portion of the trench, and surround both the corner portions of the bottom portion of the trench.

Abstract: A liquid crystal display (LCD) panel is provided. The LCD panel includes an active device array substrate, an opposite substrate, and a liquid crystal layer. The active device array substrate includes a plurality of pixel units, and each of the pixel units has a reflective area and a transmissive area. The opposite substrate is disposed above the active device array substrate and has a plurality of first alignment protrusions corresponding to the reflective area and a plurality of second alignment protrusions corresponding to the transmissive area. The first and the second alignment protrusions are positioned between the opposite substrate and the active device array substrate. Additionally, a height of the first alignment protrusions is greater than a height of the second alignment protrusions. The liquid crystal layer is disposed between the opposite substrate and the active device array substrate. The LCD panel has a high aperture ratio.

Abstract: A light emitting device including: at least one light emitting stack including first and second conductivity type semiconductor layers and an active layer disposed there between, the light emitting stack having first and second surfaces and side surfaces interposed between the first and second surfaces; first and second contacts formed on the first and second surface of the light emitting stack, respectively; a first insulating layer formed on the second surface and the side surfaces of the light emitting stack; a conductive layer connected to the second contact and extended along one of the side surfaces of the light emitting stack to have an extension portion adjacent to the first surface; and a substrate structure formed to surround the side surfaces and the second surface of the light emitting stack.

Abstract: A semiconductor light emitting device has an outer lead disposed along an outer wall of a mold resin portion perpendicular to a light-emitting plane of a light emitting diode. An outer lead is also disposed at an outer wall of the mold resin portion parallel to and opposite to the light-emitting plane. The outer wall of the resin mold where the outer lead is disposed is taken as a mount face. Each outer wall of the mold resin portion constituting a mount face includes at least one outer lead for an anode and a cathode. According to the present configuration, there is provided a semiconductor light emitting device that allows selection of side-emission mounting or top-emission mounting with the same components on a mount substrate.

Abstract: An optoelectronic device such as a light-emitting diode chip is disclosed. It includes a substrate, a multi-layer epitaxial structure, a first metal electrode layer, a second metal electrode layer, a first bonding pad and a second bonding pad. The multi-layer epitaxial structure on the transparent substrate comprises a semiconductor layer of a first conductive type, an active layer, and a semiconductor layer of a second conductive type. The first bonding pad and the second bonding pad are on the same level. Furthermore, the first metal electrode layer can be patterned so the current is spread to the light-emitting diode chip uniformly.

Abstract: One embodiment of the present invention provides a semiconductor light-emitting device, which comprises: an upper cladding layer; a lower cladding layer; an active layer between the upper and lower cladding layers; an upper ohmic-contact layer forming a conductive path to the upper cladding layer; and a lower ohmic-contact layer forming a conductive path the lower cladding layer. The lower ohmic-contact layer has a shape substantially different from the shape of the upper ohmic-contact layer, thereby diverting a carrier flow away from a portion of the active layer which is substantially below the upper ohmic-contact layer when a voltage is applied to the upper and lower ohmic-contact layers.

Abstract: Disclosed herein are a patterned substrate for a light emitting diode and a light emitting diode employing the patterned substrate. The substrate has top and bottom surfaces. Protrusion patterns are arranged on the top surface of the substrate. Furthermore, recessed regions surround the protrusion patterns. The recessed regions have irregular bottoms. Thus, the protrusion patterns and the recessed regions can prevent light emitted from a light emitting diode from being lost due to the total reflection to thereby improve light extraction efficiency.

Abstract: A pn junction type Group III nitride semiconductor light-emitting device 10 (11) of the present invention has a light-emitting layer 2 of multiple quantum well structure in which well layers 22 and barrier layers 21 including Group III nitride semiconductors are alternately stacked periodically between an n-type clad layer 105 and a p-type clad layer 107 which are formed on a crystal substrate and which include Group III nitride semiconductors, in which one end layer 21m of the light-emitting layer 2 is closest to and opposed to the n-type clad layer, and the other end layer 21n of the light-emitting layer 2 is closest to and opposed to the p-type clad layer, both the one and the other end layers are barrier layers, and the other end layer 21n is thicker than the barrier layer of the one end layer.

Abstract: A light emitting diode and a method of producing white light from the light emitting diode with an active region producing an emission falling in a primary wavelength range. A first part of the active region covered with a first conversion element for converting the emission falling in the primary wavelength range to an emission falling in a second wavelength range. A remaining second part of the active region covered with a second conversion element for converting the emission falling in the primary wavelength rage to an emission falling in a third wavelength range. The light emitting diode is configured to control the intensity of the emission falling in the primary wavelength range to control the color point of the white light generated by mixing the emissions falling the second wavelength range and the third wavelength range.

Abstract: The present invention discloses a surface mount type light-emitting diode package device and a light-emitting element package device. In the device, the encapsulation layer comprises an encapsulation material and at least one material having a refraction index different from the encapsulation material distributed therein. The distribution of the material having a refraction index different from the encapsulation material is in a way such that the refraction index of the encapsulation layer is gradually reduced from the bottom portion upward to the top portion or the inner portion outward to the outer portion of the encapsulation layer. Accordingly, a difference between the refraction indexes of two adjoining media can be reduced to eliminate a total reflection and the Fresnel loss and enhance light extraction efficiency.

Abstract: An LED module and a manufacturing method thereof are disclosed. The LED module includes a PCB and an LED chip connected with the PCB and a light congregating cup mounted on the PCB. Two ends of the light congregating cup define two hatches, the two hatches run-through each other and form a chip containing space within the light congregating cup. The LED chip is contained in the chip containing space and packaged therein by a packaging colloid. Because the light congregating cup is assembled with the PCB, the operating time of the production machine can be lowered. The defect rate, caused by traditional methods of setting the LED chip in a slantwise concave, can also be reduced. Moreover, the invention also provides a manufacturing method for the LED module.

Abstract: An active matrix organic electroluminescent substrate includes a substrate having a controlling element region and a luminescent region, a thin film transistor, a first passivation layer, a conductive layer electrically connected to the thin film transistor, and a second passivation layer disposed on the first passivation layer and the conductive layer. The second passivation layer has an opening partially exposing the conductive layer, and a step-shaped structure located between the controlling element region and the luminescent region.

Abstract: One embodiment of the present invention provides a semiconductor light-emitting device. The semiconductor light-emitting device includes a substrate, a p-type doped InGaAIN layer, an n-type doped InGaAIN layer, and an active layer situated between the p-type doped and n-type doped InGaAIN layers. The semiconductor light-emitting device further includes an n-side Ohmic-contact layer coupled to an N-polar surface of the n-type doped InGaAIN layer. The Ohmic-contact layer comprises at least one of Au, Ni, and Pt, and at least one of group IV elements.

Abstract: An object of the present invention is to provide a low-resistance n-type Group III nitride semiconductor layered structure having excellent flatness and few pits. The inventive n-type group III nitride semiconductor layered structure comprises a substrate and, stacked on the substrate, an n-type impurity concentration periodic variation layer comprising an n-type impurity atom higher concentration layer and an n-type impurity atom lower concentration layer, said lower concentration layer being stacked on said higher concentration layer.

Abstract: A method for manufacturing a trench type power semiconductor device is provided. The method includes: forming a first silicon oxide film on a silicon substrate; forming a thermal oxidation-resistant film on the first silicon oxide film; forming an opening in the first silicon oxide film and the thermal oxidation-resistant film; forming a sidewall on an inner side surface of the opening; forming a trench in the silicon substrate by etching the silicon substrate using the first silicon oxide film, the thermal oxidation-resistant film, and the sidewall as a mask; removing the sidewall; forming a second silicon oxide film thicker than the first silicon oxide film on an inner surface of the trench by applying thermal oxidation to the silicon substrate; burying a trench gate electrode in the trench; removing the thermal oxidation-resistant film; and introducing impurities into at least part of a region of the silicon substrate between the trenches.

Abstract: A semiconductor device with a heterojunction. The device comprises a substrate and at least one nanostructure. The substrate and nanostructure is of different materials. The substrate may e.g. be of a group IV semiconductor material, whereas the nanostructure may be of a group III-V semiconductor material. The nanostructure is supported by and in epitaxial relationship with the substrate. A nanostructure may be the functional component of an electronic device such as a gate-around-transistor device. In an embodiment of a gate-around-transistor, a nanowire (51) is supported by a substrate (50), the substrate being the drain, the nanowire the current channel and a top metal contact (59) the source. A thin gate dielectric (54) is separating the nanowire and the gate electrode (55A, 55B).

Abstract: A semiconductor device that is fabricated by metamorphic epitaxial growth processes, and includes a combined graded base and active layer having a thickness less than 5000 ?. In one non-limiting embodiment, the semiconductor device is an HBT device that includes a combined doped graded buffer and sub-collector layer having a thickness less than 5000 ?, and a concentration of indium of about 86% at a top of the combined layer.

Abstract: A semiconductor device having an electrode with reduced electrical contact resistance even where either electrons or holes are majority carriers is disclosed. This device has an n-type diffusion layer and a p-type diffusion layer in a top surface of a semiconductor substrate. The device also has first and second metal wires patterned to overlie the n-type and p-type diffusion layers, respectively, with a dielectric layer interposed therebetween, a first contact electrode for electrical connection between the n-type diffusion layer and the first metal wire, and a second contact electrode for connection between the p-type diffusion layer and the second metal wire. The first contact electrode's portion in contact with the n-type diffusion layer and the second contact electrode's portion contacted with the p-type diffusion layer are each formed of a first conductor that contains a metal and a second conductor containing a rare earth metal.

Abstract: In one aspect of the present invention, a semiconductor device may include a Si substrate, a gate electrode provided on the semiconductor via a gate dielectric layer, a first epitaxially grown layer provided on the Si substrate, a channel region provided in the Si substrate below the gate electrode, a source/drain region provided in the first epitaxially grown layer sandwiching the channel region, and having a first conductivity type impurity, a second epitaxially grown layer provided between the channel region and the first epitaxially grown layer, and provided below the gate electrode, and having a second conductivity type impurity opposite to the first conductivity type.

Abstract: Methods and systems for fabricating an integrated BiFET using two separate growth procedures are disclosed. Performance of the method fabricates the FET portion of the BIFET in a first fabrication environment. Performance of the method fabricates the HBT portion of the BiFET in a second fabrication environment. By separating the fabrication of the FET portion and the HBT portion in two or more separate reactors, the optimum device performance can be achieved for both devices.

Abstract: A semiconductor device having sufficiently high heat dissipation performance while inhibiting an increase in the area of a chip is provided. In semiconductor device 1, a plurality of HBTs 20 and a plurality of diodes 30 are one-dimensionally and alternately arranged on semiconductor substrate 10. Anode electrode 36 of diode 30 is connected to emitter electrode 27 of HBT 20 via common emitter wiring 42. Diode 30 works as heat dissipating elements dissipating to semiconductor substrate 10 the heat transmitted through common emitter wiring 42 from emitter electrode 27, and also works as a protection diode connected in parallel between an emitter and a collector of HBT 20.

Abstract: A base layer made of SiGe mixed crystal includes a spacer layer formed in contact with a collector layer with no base impurities diffused therein and an intrinsic base layer formed in contact with an emitter layer with base impurities diffused therein. The spacer layer contains C at a low concentration. The intrinsic base layer has a first region containing C at a low concentration on the collector side and a second region containing C at a high concentration on the emitter side.

Abstract: A sophisticated semiconductor device capable of being fabricated without introducing a high-precision exposure apparatus is obtained. This semiconductor device includes a conductive layer formed on a first conductivity type collector layer, a first conductivity type emitter electrode formed on the conductive layer and a protruding portion protruding from an outer side toward an inner side of the emitter electrode along an interface between the emitter electrode and the conductive layer. The conductive layer has a first conductivity type emitter diffusion layer in contact with the emitter electrode through the protruding portion and a second conductivity type base layer.

Abstract: An isolation region is provided around a sense part. The isolation region is provided to have a depth that suppresses spread of a region with an uneven current distribution, which occurs at a peripheral edge of the sense part. Thus, in the sense part, an influence of the region with the uneven current distribution can be suppressed. Since the current distribution can be set more even throughout the sense part, the on-resistance in the sense part can be set closer to its designed value. Thus, a current ratio corresponding to a cell ratio can be obtained as designed. Consequently, current detection accuracy is improved.

Abstract: The invention relates to a semiconductor structure, especially for use in a semiconductor detector. The semiconductor structure includes a weakly doped semiconductor substrate (HK) of a first or second doping type, a highly doped drain region (D) of a second doping type, located on a first surface of the semiconductor substrate (HK), a highly doped source region (S) of the second doping type, located on the first surface of the semiconductor substrate (HK), a duct (K) extending between the source region (S) and the drain region (D), a doped inner gate region (IG) of the first doping type, which is at least partially located below the duct (K), and a blow-out contact (CL) for removing charge carriers from the inner gate region (IG). According to the invention, the inner gate region (IG) extends in the semiconductor substrate (HK) at least partially up to the blow-out contact (CL) and the blow-out contact (CL) is located on the drain end relative to the source region (S).

Abstract: Various integrated circuit devices, in particular a junction field-effect transistor (JFET), are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench. Various techniques for terminating the isolation structure by extending the floor isolation region beyond the trench, using a guard ring, and a forming a drift region are described.

Abstract: An MMIC 100 is a semiconductor device which includes an FET formed on a GaAs substrate 10 and an MIM capacitor having a dielectric layer 20b arranged between a lower electrode 18b and an upper electrode 22b. A method for manufacturing the MMIC 100 is provided, in which a source electrode 16a and a drain electrode 16b of the FET are formed and then a gate electrode 18a of the FET and a lower electrode 18b of the MIM capacitor are formed simultaneously by the lift-off method.

Abstract: A method for fabricating a semiconductor device comprises providing a silicon-containing substrate with first, second, and third regions. First, second, and third gate stacks respectively overlie a portion of the silicon-containing substrate in the first, second, and third regions. A spacer is formed on opposing sidewalls of each of the first, second, and third gate stacks, the spacer overlying a portion of the silicon-containing substrate in the first, second, and third regions, respectively. A source/drain region is formed in a portion of the silicon-containing substrate in the first, second, and third regions, with the source/drain region adjacent to the first, second, and third gate stacks, respectively. The first, second, and third gate stacks have first, second, and third gate dielectric layers of various thicknesses and at least one thereof with a relatively thin thickness is treated by NH3-plasma, having a nitrogen-concentration of about 1013˜1021 atoms/cm2 therein.

Abstract: Sidewall spacers that are primarily oxide, instead of nitride, are formed adjacent to a gate stack of a CMOS transistor. Individual sidewall spacers are situated between a conductive gate electrode of the gate stack and a conductive contact of the transistor. As such, a capacitance can develop between the gate electrode and the contact, depending on the dielectric constant of the interposed sidewall spacer. Accordingly, forming sidewall spacers out of oxide, which has a lower dielectric constant than nitride, mitigates capacitance that can otherwise develop between these features. Such capacitance is undesirable, at least, because it can inhibit transistor switching speeds. Accordingly, fashioning sidewall spacers as described herein can mitigate yield loss by reducing the number of devices that have unsatisfactory switching speeds and/or other undesirable performance characteristics.

Abstract: A method of manufacturing a semiconductor device has forming a first silicon film over the first insulating film, forming a second silicon film over the first silicon film, a first etching the second silicon film in a depth, which the first silicon film is not exposed, in first condition, a second etching a remaining portion of the second silicon film and the first silicon film in a depth, which the first insulating film is not exposed, in second condition which gives a higher vertical etching component ratio than the first condition; and a third etching a remaining portion of the first silicon film in third condition which an etching rate for the first silicon film is larger than an etching rate for the first insulating film as compared to the second condition, wherein an impurity concentration of a first conductivity type of the first silicon film is higher than an impurity concentration of first conductivity type of the second silicon film.

Abstract: A semiconductor photodetector device includes a light receiving operation section converting incident light to an electric signal and a current amplifying operation section amplifying the electric signal. The light receiving operation section includes: a first conductivity type semiconductor layer a formed on a first conductivity type semiconductor substrate; a second conductivity type first semiconductor region formed on the semiconductor layer; and a first conductivity type second semiconductor region formed on the semiconductor layer and separated from the first semiconductor region. The current amplifying operation section includes: the second semiconductor region; a second conductivity type third semiconductor region formed in the semiconductor substrate; a second conductivity type fourth semiconductor region formed on the third semiconductor region and separated from the second semiconductor region.

Abstract: According to an aspect of the present invention, there is provided a non-volatile memory including: a transistor formed on a semiconductor substrate, the transistor including: two diffusion layers and a gate therebetween; a first insulating film formed on a top and a side surfaces of the gate; a first and a second contact plugs formed on corresponding one of the diffusion layers to contact the first insulating film; a ferroelectric capacitor formed on the first contact plug and on the first insulating film, the ferroelectric capacitor including: a first and a second electrodes and a ferroelectric film therebetween; a third contact plug formed on the second electrode; and a fourth contact plug formed on the second contact plug.