Patents Issued in September 25, 2008
  • Publication number: 20080230819
    Abstract: A method and system for providing a magnetic element that can be used in a magnetic memory is disclosed. The magnetic element includes pinned, nonmagnetic spacer, and free layers. The spacer layer resides between the pinned and free layers. The free layer can be switched using spin transfer when a write current is passed through the magnetic element. The free layer includes a first ferromagnetic layer and a second ferromagnetic layer. The second ferromagnetic layer has a very high perpendicular anisotropy and an out-of-plane demagnetization energy. The very high perpendicular anisotropy energy is greater than the out-of-plane demagnetization energy of the second layer.
    Type: Application
    Filed: June 5, 2008
    Publication date: September 25, 2008
    Applicant: GRANDIS, INC.
    Inventors: Paul P. Nguyen, Yiming Huai
  • Publication number: 20080230820
    Abstract: Coexistence of the realization of high-capacity of a capacitive element and the area reduction of a semiconductor device is aimed at. A plurality of capacitive elements from which a kind differs mutually are accumulated and arranged on a semiconductor substrate, and they are connected in parallel. These capacitive elements are arranged to the same plane region, and make a plane size almost the same. A lower capacitive element is an MOS type capacitive element which uses as both electrodes the n-type semiconductor region formed in the semiconductor substrate, and the upper electrode formed via the insulation film on the n-type semiconductor region. The MIM type capacitive element formed with the pattern of the comb-type of a wiring is arranged in the upper part of a lower capacitive element, and this is connected with a lower capacitive element in parallel.
    Type: Application
    Filed: January 14, 2008
    Publication date: September 25, 2008
    Inventors: Satoshi Maeda, Hidehiro Harata, Hiroyuki Kono
  • Publication number: 20080230821
    Abstract: In a semiconductor device which can perform data communication through wireless communication, to suppress transmission and the like of an AC signal, the semiconductor device includes an input circuit to which a radio signal is input, a first circuit, which generates a constant voltage, such as a constant voltage circuit or a limiter circuit, a second circuit to which the generated constant voltage is input and which can change impedance of the semiconductor device, and a filter provided between the first circuit and the second circuit. Transmission of an AC signal is suppressed by the filter, and malfunctions or operation defects such as complete inoperative due to variation in the constant voltage is prevented.
    Type: Application
    Filed: March 7, 2008
    Publication date: September 25, 2008
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yutaka Shionoiri
  • Publication number: 20080230822
    Abstract: A method of forming a vertical transistor trench memory cell having an insulating ring is provided. The method includes forming a semiconductor material region in an etched portion of a semiconductor substrate; partially etching the semiconductor material region to form a deep trench, where the deep trench extends beyond the semiconductor material region, and where the remaining of the partially etched semiconductor material region defines an insulating ring. A vertical transistor is then formed in the deep trench, such that the vertical transistor is isolated by the insulating ring. A semiconductor structure is also provided. The semiconductor structure includes a first and a second trench memory cells formed on a semiconductor substrate; and an insulating ring surrounding each of the first and second trench memory cells. The insulating ring is configured for significantly enclosing outdiffusions from the trench memory cells.
    Type: Application
    Filed: March 20, 2007
    Publication date: September 25, 2008
    Applicant: International Business Machines Corporation
    Inventor: Kangguo Cheng
  • Publication number: 20080230823
    Abstract: A semiconductor device having an active element and an MIM capacitor and a structure capable of reducing the number of the manufacturing steps thereof and a manufacturing method therefor are provided. The semiconductor device has a structure that the active element having an ohmic electrode and the MIM capacitor having a dielectric layer arranged between a lower electrode and an upper electrode are formed on a semiconductor substrate, wherein the lower electrode and ohmic electrode have the same structure. In an MMIC 100 in which an FET as an active element and the MIM capacitor are formed on a GaAs substrate 10, for example, a source electrode 16a and a drain electrode 16b, which are ohmic electrodes of the FET, are manufactured simultaneously with a lower electrode 16c of the MIM capacitor. Here the electrodes are formed with the same metal.
    Type: Application
    Filed: March 10, 2008
    Publication date: September 25, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hisao Kawasaki
  • Publication number: 20080230824
    Abstract: The present invention relates to a non-volatile memory device on a substrate layer comprising semiconductor source and drain regions, a semiconductor channel region, a charge storage stack and a control gate; the channel region being fin-shaped having two sidewall portions and a top portion, and extending between the source region and the drain region; the charge storage stack being positioned between the source and drain regions and extending over the fin-shaped channel, substantially perpendicularly to the length direction of the fin-shaped channel; the control gate being in contact with the charge storage stack, wherein—an access gate is provided adjacent to one sidewall portion and separated therefrom by an intermediate gate oxide layer, and—the charge storage stack contacts the fin-shaped channel on the other sidewall portion and is separated from the channel by the intermediate gate oxide layer.
    Type: Application
    Filed: September 26, 2006
    Publication date: September 25, 2008
    Applicant: NXP B.V.
    Inventors: Gerben Doornbos, Pierre Goarin
  • Publication number: 20080230825
    Abstract: The invention relates to a nonvolatile semiconductor memory device including a semiconductor layer which has a source region, a drain region, and a channel forming region which is provided between the source region and the drain region; and a first insulating layer, a first gate electrode, a second insulating layer, and a second gate electrode which are layered over the semiconductor layer in that order. Part or all of the source and drain regions is formed using a metal silicide layer. The first gate electrode contains a noble gas element.
    Type: Application
    Filed: February 26, 2008
    Publication date: September 25, 2008
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Kengo AKIMOTO
  • Publication number: 20080230826
    Abstract: Methods, apparatus and systems form memory structures, such as flash memory structures from nanoparticles by providing a source of nanoparticles as a conductive layer. The particles are moved by application of a field, such as an electrical field, magnetic field and even electromagnetic radiation. The nanoparticles are deposited onto an insulating surface over a transistor in a first distribution of the nanoparticles. A field is applied to the nanoparticles on the surface that applies a force to the particles, rearranging the nanoparticles on the surface by the force from the field to form a second distribution of nanoparticles on the surface. A protective and enclosing insulating layer is deposited on the nanoparticle second distribution. The addition of a top conductive layer completes a basic flash memory structure.
    Type: Application
    Filed: March 12, 2008
    Publication date: September 25, 2008
    Applicants: Nevada
    Inventor: Biswajit Das
  • Publication number: 20080230827
    Abstract: Devices and methods are provided with respect to a gate stack for a nonvolatile structure. According to one aspect, a gate stack is provided. One embodiment of the gate stack includes a tunnel medium, a high K charge blocking and charge storing medium, and an injector medium. The high K charge blocking and charge storing medium is disposed on the tunnel medium. The injector medium is operably disposed with respect to the tunnel medium and the high K charge blocking and charge storing medium to provide charge transport by enhanced tunneling. According to one embodiment, the injector medium is disposed on the high K charge blocking and charge storing medium. According to one embodiment, the tunnel medium is disposed on the injector medium. Other aspects and embodiments are provided herein.
    Type: Application
    Filed: June 4, 2008
    Publication date: September 25, 2008
    Inventor: Arup Bhattacharyya
  • Publication number: 20080230828
    Abstract: A non-volatile memory device includes a substrate that is divided into a field region and an active region by isolation layer patterns. The active region has an active trench for increasing an effective area of the active region. A tunnel oxide layer is formed on the active region. A floating gate pattern is formed on the tunnel oxide layer to fill up the active trench. A dielectric layer pattern is formed on the floating gate pattern. A control gate pattern is formed on the dielectric layer pattern. Thus, the non-volatile memory device has an increased effective area of the active region so that the non-volatile memory device may have improved operational characteristics.
    Type: Application
    Filed: May 1, 2008
    Publication date: September 25, 2008
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Dae-Hyun JANG
  • Publication number: 20080230829
    Abstract: A memory device and a method of fabricating the same. The memory device includes a substrate and a first gate electrode overlying the substrate. Overlying a top surface of the first gate electrode, a second gate electrode comprises end portions extending to spaces adjacent to the substrate and sidewalls of the first gate electrode. Further, a dielectric layer comprises a first portion sandwiched between the first gate electrode and the second gate electrode, and second portions extending from the first portion, sandwiched between the substrate and the end portions of the second gate electrode.
    Type: Application
    Filed: March 15, 2007
    Publication date: September 25, 2008
    Inventor: Tzyh-Cheang Lee
  • Publication number: 20080230830
    Abstract: A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.
    Type: Application
    Filed: March 21, 2008
    Publication date: September 25, 2008
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Se Jun KIM, Eun Seok CHOI, Kyoung Hwan PARK, Hyun Seung YOO, Myung Shik LEE, Young Ok HONG, Jung Ryul AHN, Yong Top KIM, Kyung Pil HWANG, Won Sic WOO, Jae Young PARK, Ki Hong LEE, Ki Seon PARK, Moon Sig JOO
  • Publication number: 20080230831
    Abstract: A charge retention characteristic of a nonvolatile memory transistor is improved. A first insulating film that functions as a tunnel insulating film, a charge storage layer, and a second insulating film are sandwiched between a semiconductor substrate and a conductive film. The charge storage layer is formed of two silicon nitride films. A silicon nitride film which is a lower layer is formed using NH3 as a nitrogen source gas by a CVD method and contains a larger number of N—H bonds than the upper layer. A second silicon nitride film which is an upper layer is formed using N2 as a nitrogen source gas by a CVD method and contains a larger number of Si—H bonds than the lower layer.
    Type: Application
    Filed: March 19, 2008
    Publication date: September 25, 2008
    Inventors: Kosei Noda, Nanae Sato
  • Publication number: 20080230832
    Abstract: A method for fabricating a semiconductor device to enlarge a channel region is provided. The channel region is enlarged due to having pillar shaped sidewalls of a transistor. The transistor includes a fin active region vertically protruding on a substrate, an isolation layer enclosing a lower portion of the fin active region, and a gate electrode crossing the fin active region and covering a portion of the fin active region. An isolation layer is formed enclosing a lower portion of the fin active region and the isolation layer under the spacers is partially removed to expose a portion of the sidewalls of the fin active region. Subsequently, dry etching is performed to form the sidewalls having a pillar/neck.
    Type: Application
    Filed: December 27, 2007
    Publication date: September 25, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventor: Jun-Hee CHO
  • Publication number: 20080230833
    Abstract: A semiconductor component having a semiconductor body having first and second semiconductor regions of a first conduction type, and a third semiconductor region of a second conduction type, which is complementary to the first conduction type. The second semiconductor region is arranged between the first and third semiconductor region and together with the first semiconductor region forms a first junction region and together with the third semiconductor region forms a second junction region. In the second semiconductor region the dopant concentration is lower than the dopant concentration in the first semiconductor region. The dopant concentration in the second semiconductor region along a straight connecting line between the first and third semiconductor regions is inhomogeneous and has at least one minimum between the first and second junction regions, wherein the minimum is at a distance from the first and second junction regions.
    Type: Application
    Filed: March 23, 2007
    Publication date: September 25, 2008
    Applicant: Infineon Technologies Austria AG
    Inventors: Markus Zundel, Franz Hirler, Ralf Siemieniec
  • Publication number: 20080230834
    Abstract: A semiconductor apparatus comprises: a semiconductor substrate; and a lateral type MIS transistor disposed on a surface part of the semiconductor substrate. The lateral type MIS transistor includes: a line coupled with a gate of the lateral type MIS transistor; a polycrystalline silicon resistor that is provided in the line, and that has a conductivity type opposite to a drain of the lateral type MIS transistor; and an insulating layer through which a drain voltage of the lateral type MIS transistor is applied to the polycrystalline silicon resistor.
    Type: Application
    Filed: February 21, 2008
    Publication date: September 25, 2008
    Applicant: DENSO CORPORATION
    Inventors: Nozomu Akagi, Shigeki Takahashi, Takashi Nakano, Yasushi Higuchi, Tetsuo Fujii, Yoshiyuki Hattori, Makoto Kuwahara
  • Publication number: 20080230835
    Abstract: It is an object to provide an element structure of a semiconductor device for having a sufficient contact area between an electrode in contact with a source region or a drain region and the source region or the drain region, and a method for manufacturing the semiconductor device with the element structure. An upper electrode is formed over a high-concentration impurity region (the source region or the drain region). A contact hole passing through an interlayer insulating film is formed overlapping with a region where the upper electrode and the high-concentration impurity region are stacked.
    Type: Application
    Filed: March 19, 2008
    Publication date: September 25, 2008
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Takashi Shingu, Hideki Matsukura
  • Publication number: 20080230836
    Abstract: A semiconductor device includes a transistor that is used for a charge pump circuit, being configured with a fully depleted silicon-on-insulator transistor.
    Type: Application
    Filed: April 18, 2008
    Publication date: September 25, 2008
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Yoshiharu Ajiki
  • Publication number: 20080230837
    Abstract: A silicon-on-insulator metal oxide semiconductor device comprising ultrathin silicon-on-sapphire substrate; at least one P-channel MOS transistor formed in the ultrathin silicon layer; and N-type impurity implanted within the ultrathin silicon layer and the sapphire substrate such that peak N-type impurity concentration in the sapphire layer is greater than peak impurity concentration in the ultrathin silicon layer.
    Type: Application
    Filed: June 6, 2008
    Publication date: September 25, 2008
    Applicant: PEREGRINE SEMICONDUCTOR CORPORATION
    Inventors: Anthony M. MISCIONE, George IMTHURN, Eugene LYON, Michael A. STUBER
  • Publication number: 20080230838
    Abstract: An objective of this invention is to solve the problem caused by a difference in a silicon layer film thickness between a memory cell region and a region other than the memory cell region. For solving the problem, while maintaining a structure where an MOS type transistor in a memory cell region is in a floating state and an MOS type transistor in the region other than the memory cell region is not in a floating state, a film thickness of semiconductor layers having a body regions is made equal in these MOS type transistors.
    Type: Application
    Filed: March 3, 2008
    Publication date: September 25, 2008
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Shinji Ohara
  • Publication number: 20080230839
    Abstract: The invention is related to a method of producing a semiconductor structure comprising the steps of: fabricating a gate stack structure and oxidizing at least a portion of the gate stack structure's sidewalls, wherein the step of oxidizing is carried out at a temperature below 500° C. using a process gas which comprises oxygen radicals.
    Type: Application
    Filed: March 23, 2007
    Publication date: September 25, 2008
    Inventors: Joern Regul, Joerg Radecker, Olaf Storbeck, Kristin Schupke, Tobias Mono
  • Publication number: 20080230840
    Abstract: A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.
    Type: Application
    Filed: June 4, 2008
    Publication date: September 25, 2008
    Applicant: International Business Machines Corporation
    Inventors: Huajie Chen, Omer H. Dokumaci, Oleg G. Gluschenkov, Werner A. Rausch
  • Publication number: 20080230841
    Abstract: An integrated circuit system that includes: providing a gate and a spacer formed over a substrate; performing an implant that amorphizes the gate and a source/drain region defined by the spacer; removing the spacer; depositing a stress memorization layer over the integrated circuit system; and transferring a stress from the stress memorization layer to the gate and the source/drain region.
    Type: Application
    Filed: March 21, 2007
    Publication date: September 25, 2008
    Applicant: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Elgin Kiok Boone Quek, Pradeep Ramachandramurthy Yelehanka
  • Publication number: 20080230842
    Abstract: A semiconductor device having a high-K gate dielectric layer includes a p-type well that is formed in an upper layer of a silicon substrate. Arsenic ions are implanted into an extreme surface layer of the p-type well and a heat treatment is performed to form a p-type low-concentration layer. A HfAlOx film and a polycrystalline silicon layer are laminated on the substrate. A gate electrode is formed by patterning the polycrystalline silicon layer. After a n-type extension region is formed by implanting arsenic ions by using the gate electrode as a mask, sidewall spacers are formed on sides of the gate electrode. Arsenic ions are implanted by using the sidewall spacers and the gate electrode as masks, whereby n-type source/drain regions are formed.
    Type: Application
    Filed: June 20, 2005
    Publication date: September 25, 2008
    Inventor: Hiroshi Oji
  • Publication number: 20080230843
    Abstract: A method for forming isolation structure for MOS transistor is disclosed, which includes forming a first photoresist layer over a sacrificed oxide layer of a semiconductor substrate, patterning the first photoresist layer to define a PMOS active region and a PMOS isolation region; implanting nitrogen ions into the PMOS isolation region through the sacrificed oxide layer by using the first photoresist layer as a mask; removing the first photoresist layer; forming a second photoresist layer over the sacrificed oxide layer, patterning the second photoresist layer to define a NMOS active region and a NMOS isolation region; implanting oxygen ions into the NMOS isolation region through the sacrificed oxide layer by using the second photoresist layer as a mask; removing the second photoresist layer and the sacrificed oxide layer; and annealing the semiconductor substrate to form isolation structures of PMOS and NMOS, respectively.
    Type: Application
    Filed: December 5, 2007
    Publication date: September 25, 2008
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Buxin Zhang, Yuan Wang
  • Publication number: 20080230844
    Abstract: A system and method for forming a semiconductor device with a reduced source/drain extension parasitic resistance is provided. An embodiment comprises implanting two metals (such as ytterbium and nickel for an NMOS transistor or platinum and nickel for a PMOS transistor) into the source/drain extensions after silicide contacts have been formed. An anneal is then performed to create a second silicide region within the source/drain extension. Optionally, a second anneal could be performed on the second silicide region to force a further reaction. This process could be performed to multiple semiconductor devices on the same substrate.
    Type: Application
    Filed: March 20, 2007
    Publication date: September 25, 2008
    Inventors: Chen-Hua Yu, Cheng-Tung Lin, Chen-Nan Yeh
  • Publication number: 20080230845
    Abstract: A semiconductor device may include, but is not limited to, a single crystal silicon diffusion layer, a polycrystal silicon conductor, and a diffusion barrier layer. The diffusion barrier layer separates the polycrystal silicon conductor from the single crystal silicon diffusion layer. The diffusion barrier layer prevents a diffusion of at least one of silicon-interstitial and silicon-vacancy between the single crystal silicon diffusion layer and the polycrystal silicon conductor.
    Type: Application
    Filed: September 21, 2007
    Publication date: September 25, 2008
    Applicant: ELPIDA MEMORY, INC
    Inventors: Kensuke Okonogi, Kiyonori Ohyu
  • Publication number: 20080230846
    Abstract: A method of manufacturing a semiconductor device, comprising forming a metal silicide gate electrode on a semiconductor substrate surface. The method also comprises exposing the metal silicide gate electrode and the substrate surface to a cleaning process. The cleaning process includes a dry plasma etch using an anhydrous fluoride-containing feed gas and a thermal sublimation configured to leave the metal silicide gate electrode substantially unaltered. The method also comprises depositing a metal layer on source and drain regions of the substrate surface and annealing the metal layer and the source and drain regions of the substrate surface to form metal silicide source and drain contacts.
    Type: Application
    Filed: March 23, 2007
    Publication date: September 25, 2008
    Applicant: Texas Instruments Incorporated
    Inventors: Yaw S. Obeng, Juanita DeLoach, Freidoon Mehrad
  • Publication number: 20080230847
    Abstract: The reliability of a semiconductor device having an embedded wire in the lowest layer wire is improved. In a main surface of a semiconductor substrate, MISFETs are formed and over the main surface, insulating films 10, 11 are formed. In the insulating films 10, 11 a contact hole is formed and a plug is embedded therein. Over the insulating film 11 in which the plug is embedded, insulating films 14, 15, 16 are formed and an opening is formed in the insulating films 14, 15, 16 and a wire is embedded therein. The insulating film 15 is an etching stopper film when etching the insulating film 16 in order to form the opening, containing silicon and carbon. The insulating film 11 has a high hygroscopicity and the insulating film 15 has a low moisture resistance, however, by interposing the insulating film 14 therebetween and making the insulating film 14 have a higher density of the number of Si (silicon) atoms than that of the insulating film 11, an electrically weak interface is prevented from being formed.
    Type: Application
    Filed: January 14, 2008
    Publication date: September 25, 2008
    Inventors: Takeshi Furusawa, Takao Kamoshima, Masatsugu Amishiro, Naohito Suzumura, Shoichi Fukui, Masakazu Okada
  • Publication number: 20080230848
    Abstract: A structure including a dual silicide region and a related method are disclosed. The structure may include a doped silicon, and a dual silicide region in the doped silicon, the dual silicide region including a first silicide region including a mid band gap metal, and a second silicide region including a near band gap metal, wherein the second silicide region is immediately adjacent to the doped silicon. The method may include forming a first silicide portion in a doped silicon by depositing a first metal over the doped silicon, annealing and removing unreacted first metal; ion implanting a second metal into the doped silicon; and annealing to form a second silicide portion from the second metal, wherein the first metal is different than the second metal.
    Type: Application
    Filed: March 22, 2007
    Publication date: September 25, 2008
    Inventors: Chih-Chao Yang, Haining S. Yang, Keith Kwong Hon Wong
  • Publication number: 20080230849
    Abstract: A device comprising a doped semiconductor nano-component and a method of forming the device are disclosed. The nano-component is one of a nanotube, nanowire or a nanocrystal film, which may be doped by exposure to an organic amine-containing dopant. Illustrative examples are given for field effect transistors with channels comprising a lead selenide nanowire or nanocrystal film and methods of forming these devices.
    Type: Application
    Filed: May 30, 2008
    Publication date: September 25, 2008
    Applicant: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Cherie R. Kagan, Christopher B. Murray, Robert L. Sandstrom, Dmitri V. Talapin
  • Publication number: 20080230850
    Abstract: A method of manufacturing a semiconductor device has forming a first mask pattern exposing a region for forming a first transistor and a region for forming a second transistor, performing a first ion implantation using the first mask pattern, performing a second ion implantation using the first mask pattern, removing the first mask pattern and forming a second mask pattern in which the first transistor forming region is covered and the second transistor forming region is opened, and performing a third ion implantation using the second mask pattern.
    Type: Application
    Filed: March 20, 2008
    Publication date: September 25, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Yoshihiro TAKAO
  • Publication number: 20080230851
    Abstract: A semiconductor device with a metal oxide semiconductor (MOS) type transistor structure, which is used for, e.g. a static random access memory (SRAM) type memory cell, includes a part that is vulnerable to soft errors. In the semiconductor device with the MOS type transistor structure, an additional load capacitance is formed at the part that is vulnerable to soft errors.
    Type: Application
    Filed: May 31, 2008
    Publication date: September 25, 2008
    Inventor: Hironobu FUKUI
  • Publication number: 20080230852
    Abstract: A semiconductor structure includes a first semiconductor strip extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the first semiconductor strip has a first height. A first insulating region is formed in the semiconductor substrate and surrounding a bottom portion of the first semiconductor strip, wherein the first insulating region has a first top surface lower than a top surface of the first semiconductor strip. A second semiconductor strip extends from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the second semiconductor strip has a second height greater than the first height. A second insulating region is formed in the semiconductor substrate and surrounding a bottom portion of the second semiconductor strip, wherein the second insulating region has a second top surface lower than the first top surface, and wherein the first and the second insulating regions have substantially same thicknesses.
    Type: Application
    Filed: March 6, 2007
    Publication date: September 25, 2008
    Inventors: Chen-Hua Yu, Chen-Nan Yeh, Chu-Yun Fun, Yu-Rung Hsu
  • Publication number: 20080230853
    Abstract: In a transistor and a method of manufacturing the same, the transistor includes a channel layer arranged on a substrate, a source electrode and a drain electrode formed on the substrate so as to contact respective ends of the channel layer, a gate insulating layer surrounding the channel layer between the source electrode and the drain electrode, and a gate electrode surrounding the gate insulating layer.
    Type: Application
    Filed: November 28, 2007
    Publication date: September 25, 2008
    Inventors: Jae-Eun Jang, Seung-Nam Cha, Jae-Eun Jung, Yong-Wan Jin
  • Publication number: 20080230854
    Abstract: A semiconductor device, such as a transistor or capacitor is provided. The device includes a substrate, a gate dielectric over the substrate, and a conductive gate dielectric film over the gate dielectric. The gate dielectric includes a doped hafnium zirconium oxide containing one or more dopant elements selected from Group II, Group XIII, silicon, and rare earth elements of the Periodic Table. According to one embodiment, the conductive gate dielectric can contain doped hafnium zirconium nitride or doped hafnium zirconium oxynitride.
    Type: Application
    Filed: March 20, 2007
    Publication date: September 25, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Robert D. CLARK
  • Publication number: 20080230855
    Abstract: A semiconductor structure with reduced inter-diffusion is provided. The semiconductor structure includes a semiconductor substrate; a first well region in the semiconductor substrate; a second well region in the semiconductor substrate; an insulating region between and adjoining the first and the second well regions; a gate dielectric layer on the first and the second well regions; and a gate electrode strip on the gate dielectric and extending from over the first well region to over the second well region. The gate electrode strip includes a first portion over the first well region, a second portion over the second well region, and a third portion over the insulating region. A thickness of the third portion is substantially less than the thicknesses of the first and the second portions.
    Type: Application
    Filed: March 19, 2007
    Publication date: September 25, 2008
    Inventor: Jhon-Jhy Liaw
  • Publication number: 20080230856
    Abstract: An intermediate probe structure for atomic force microscopy is disclosed. The probe structure comprises a semiconductor substrate with one or more moulds formed on a surface of one side of the substrate. The probe structure further comprises one or more probe configurations formed on the one side of the semiconductor substrate, wherein each probe configuration comprises a contact region and at least one set of a probe tip and a cantilever. The probe structure further comprises one or more holders attached to each of the contact regions, wherein the surface area of each contact region is smaller in size than the surface area of the holder which is attached to the contact region.
    Type: Application
    Filed: July 9, 2007
    Publication date: September 25, 2008
    Applicant: Interuniversitair Microelektronica Centrum (IMEC) vzw
    Inventor: Marc Fouchier
  • Publication number: 20080230857
    Abstract: A sensor chip and substrate assembly for use in a MEMS device includes a substrate and a sensor chip. The substrate has a top surface, a bottom surface opposite to the top surface, and a passage obliquely penetrating through the top surface and the bottom surface. The sensor chip is mounted on the top surface of the substrate and provided with a sensing zone facing the passage of the substrate. The oblique passage provides a buffering effect to prevent damage to the sensor chip when the quantity of the physical property sending from the detected object increases sharply.
    Type: Application
    Filed: December 3, 2007
    Publication date: September 25, 2008
    Applicant: Lingsen Precicion Industries, LTD.
    Inventor: Jeson HSU
  • Publication number: 20080230858
    Abstract: A multi-layer package structure for an acoustic microsensor, the package structure mainly utilizes a stack of multiple substrates for housing and protecting circuit elements such that integrated circuit element and acoustic microsensor arranged in recessions of a substrate can reduce volume of the package structure. By adding various sound hole designs, the problem of larger package volume can be effectively solved and sensing frequency of the acoustic microsensor can be increased simultaneously.
    Type: Application
    Filed: February 15, 2008
    Publication date: September 25, 2008
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventor: Hsin-Tang Chien
  • Publication number: 20080230859
    Abstract: The design, fabrication, post-processing and characterization of a novel SAW (Surface Acoustic Wave) based bio/chemical sensor in CMOS technology is introduced. The sensors are designed in AMI 1.5 ?m 2 metal, 2 poly process. A unique maskless post processing sequence is designed and completed. The three post-processing steps are fully compatible with any CMOS technology. This allows any signal control/processing circuitry to be easily integrated on the same chip. ZnO is used as the piezoelectric material for the SAW generation. A thorough characterization and patterning optimization of the sputtered ZnO was carried out. The major novelties that are introduced in the SAW delay line features are: The embedded heater elements for temperature control, compensation and acoustic absorbers that are designed to eliminate edge reflections and minimize triple transit interference. Both of these attributes are designed by using the CMOS layers without disturbing the SAW performance.
    Type: Application
    Filed: April 20, 2007
    Publication date: September 25, 2008
    Inventors: MONA ZAGHLOUL, Onur Tigli
  • Publication number: 20080230860
    Abstract: The invention provides an integrated circuit package and method of fabrication thereof. The integrated circuit package comprises an integrated circuit chip having a photosensitive device thereon; a bonding pad formed on an upper surface of the integrated circuit chip and electrically connected to the photosensitive device, a barrier formed between the bonding pad and the photosensitive device; and a conductive layer formed on a sidewall of the integrated circuit chip and electrically connected to the bonding pad. The barrier layer blocks overflow of the adhesive layer into a region, on which the photosensitive device is formed, to improve yield for fabricating the integrated circuit package.
    Type: Application
    Filed: July 25, 2007
    Publication date: September 25, 2008
    Inventors: Yu-Lin Yen, Chen-Mei Fan
  • Publication number: 20080230861
    Abstract: An improved imaging device having a pixel arrangement featuring a multilayer light shield. The multilayer light shield includes stacked layers of light-shielding and light-transparent material. The light-transparent material, such as a dielectric, is selected to have a stress, such as a tensile stress, that offsets the stress, such as a compressive stress, of the light shielding material. Without the stress offset, the high compressive stress of the refractory metal could damage the integrity of the nearby silicon. The refractory metal is capable of withstanding the high temperatures associated with front end CMOS processing. The laminate structure allows the light shield to be placed close to the pixel surface. The light-transparent material has a thickness equal to about one-quarter wavelength of the light to be blocked, to act as an anti-reflective coating. An aperture in the light shield exposes the active region of the pixel's photoconversion device.
    Type: Application
    Filed: May 8, 2008
    Publication date: September 25, 2008
    Inventors: Jiutao Li, Jin Li
  • Publication number: 20080230862
    Abstract: Here, we demonstrate new material/structures for the photodetectors, using semiconductor material. For example, we present the Tunable Avalanche Wide Base Transistor as a photodetector. Particularly, SiC, GaN, AlN, Si and Diamond materials are given as examples. The desired properties of an optimum photodetector is achieved. Different variations are discussed, both in terms of structure and material.
    Type: Application
    Filed: March 22, 2007
    Publication date: September 25, 2008
    Inventor: Ranbir Singh
  • Publication number: 20080230863
    Abstract: In accordance with the teachings of the present disclosure, methods and apparatus are provided for a semiconductor device having thin anti-reflective layer(s) operable to absorb radiation that may otherwise reflect off surfaces disposed inwardly from the anti-reflective layer(s). In a method embodiment, a method for manufacturing a semiconductor device includes forming a support structure outwardly from a substrate. The support structure has a first thickness and a first outer sidewall surface that is not parallel with the substrate. The first outer sidewall surface has a first minimum refractive index. The method further includes forming an anti-reflective layer outwardly from the first outer sidewall surface. The anti-reflective layer has: a second outer sidewall surface that is not parallel with the substrate, a second refractive index that is greater than the first minimum refractive index, and a second thickness that is less than the first thickness.
    Type: Application
    Filed: March 21, 2007
    Publication date: September 25, 2008
    Inventors: Stanford Joseph Gautier, Rabah Mezenner, Randy Long
  • Publication number: 20080230864
    Abstract: Disclosed is an image sensor which includes a plurality of pixel patterns formed on corresponding metal interconnections of an interlayer dielectric and a dummy pixel pattern formed between adjacent pixel patterns of the plurality of the pixel patterns. The dummy pixel patterns are not formed connected to the metal interconnections. The dummy pixel patterns can be formed spaced a distance apart from the plurality of pixel patterns such that air gaps form between the dummy pixel patterns and the pixel patterns in an intrinsic layer that is formed on the dummy pixel pattern and the plurality of pixel patterns.
    Type: Application
    Filed: August 21, 2007
    Publication date: September 25, 2008
    Inventor: MIN HYUNG LEE
  • Publication number: 20080230865
    Abstract: An image sensor and method of manufacturing the same are provided. According to an embodiment, the image sensor comprises: a circuit including an interconnection on a substrate; a lower electrode on the interconnection; a separated intrinsic layer on the lower electrode; a second conductive type conduction layer on the separated intrinsic layer; and an upper electrode on the second conductive type conduction layer. The separated intrinsic layer can have an inwardly sloping sidewall to focus light incident the photodiode for the unit pixel.
    Type: Application
    Filed: March 17, 2008
    Publication date: September 25, 2008
    Inventor: JI HO HONG
  • Publication number: 20080230866
    Abstract: A system and method for manufacturing semiconductor wafers comprising an RFID temperature sensor and generally described herein. Other embodiments may be described and claimed.
    Type: Application
    Filed: March 20, 2007
    Publication date: September 25, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: John M. Kulp
  • Publication number: 20080230867
    Abstract: A process for forming an ohmic contact on the back surface of a semiconductor body includes depositing a donor layer on the back surface of the semiconductor body followed by a sintering step to form a shallow intermetallic region capable of forming a low resistance contact with a contact metal.
    Type: Application
    Filed: April 29, 2008
    Publication date: September 25, 2008
    Inventor: Giovanni Richieri
  • Publication number: 20080230868
    Abstract: A method for producing predetermined shapes in a crystalline Si-containing material that have substantially uniform straight sides or edges and well-defined inside and outside corners is provided together with the structure that is formed utilizing the method of the present invention. The inventive method utilizes conventional photolithography and etching to transfer a pattern, i.e., shape, to a crystalline Si-containing material. Since conventional processing is used, the patterns have the inherent limitations of rounded corners. A selective etching process utilizing a solution of diluted ammonium hydroxide is used to eliminate the rounded corners providing a final shape that has substantially straight sides or edges and substantially rounded corners.
    Type: Application
    Filed: April 24, 2008
    Publication date: September 25, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas W. Dyer, Kenneth T. Settlemyer, James J. Toomey, Haining Yang