Abstract: The invention provides methods for the production of synthesis gas. More particularly, various embodiments of the invention relate to systems and methods for volatilizing fluid fuel to produce synthesis gas by using a metal catalyst on a solid support matrix.

Abstract: There is provided a strengthened composite material that is able to improve yield, handling, and reliability when it is applied to members of semiconductor manufacturing apparatus. Five to 60 mol % ZrO2 is contained relative to Y2O3, and temperature after a sintering process is maintained between 1,200° C. to 1,500° C. for 5 minutes or longer or temperature falling speed to reach 1,200° C. is adjusted to 200° C./h or slower, thereby producing the composite material containing, as major crystalline phases, a Y2O3 solid solution in which ZrO2 is dissolved in Y2O3 and a ZrO2 solid solution in which Y2O3 is dissolved in ZrO2.

Abstract: Most carbon-centered free radical antioxidants are generated through hydrogen abstraction. Disclosed herein a new class of antioxidant precursor compounds of the formula A-B, wherein upon exposure of the compounds to an increase in temperature, the compounds undergo at least partial dissociation into free radicals Ao and Bo at least one of which may be functional as an antioxidant. Preferably, each of Ao and Bo is a carbon centered free radical.

Abstract: Disclosed are anisotropic conductive balls for electric connection comprised of conductive balls and insulation resin layers coating the surfaces of those conductive balls. The conductive balls are coated with a core-shell-structured emulsion-phase or suspension-phase or water-dispersible resin to form insulation resin layers as the shells of the insulation resin layers are coated with resin layers having the water-emission ability. Also disclosed are methods of manufacturing anisotropic conductive balls for electric connection as well as the products using them. Although the surfaces of the anisotropic conductive balls are coated with single- or multi-layered insulation resin layers, they show superior alive and insulation characteristics.

Abstract: A semiconductor nanocrystal composite comprising a semiconductor nanocrystal composition dispersed in an inorganic matrix material and a method of making same are provided. The method includes providing a semiconductor nanocrystal composition having a semiconductor nanocrystal core, providing a surfactant formed on the outer surface of the composition, and replacing the surfactant with an inorganic matrix material. The semiconductor nanocrystal composite emits light having wavelengths between about 1 and about 10 microns.

Abstract: A transparent conductive material contains a conductive particle, a polyfunctional compound, and an organic compound having a side chain including an ester group, while the ester group is expressed by —COOR, where R is a substituted or unsubstituted alkyl group having a carbon atom number of 2 or greater.

Abstract: In an ultrafine metal powder slurry containing an organic solvent, a surfactant, and an ultrafine metal powder, the surfactant is oleoyl sarcosine, the content of the ultrafine metal powder in the ultrafine metal powder slurry is 70 to 95 percent by mass, and more than 0.05 to less than 2.0 parts by mass of the surfactant is contained relative to 100 parts by mass of the ultrafine metal powder. By the above slurry, reduction in labor and treatment time can be realized in a conductive paste forming process. In addition, since aggregation of particles of the ultrafine metal powder is prevented, an ultrafine metal powder slurry can be provided having superior dispersibility and dry film density.

Abstract: A novel phosphor material which can be manufactured without utilizing a fault formation process which is difficult to be controlled. The phosphor material has a eutectic structure formed of a base material that is a semiconductor formed of a Group 2 element and a Group 6 element, a semiconductor formed of a Group 3 element and a Group 5 element, or a ternary phosphor formed of an alkaline earth metal, a Group 3 element, and a Group 6 element, and a solid solution material including a transition metal. The phosphor material is suited for an EL element because of less variation of characteristic since defect formation process in which stress is applied externally to form a defect inside of a phosphor material is not needed.

Abstract: Compositions of encapsulated triboelectrically charged particles and methods for making them using a spinning disc process are disclosed. The methods can be used to make charged pigment particles embedded in a neutral polymer matrix. The polymer matrix keeps oppositely charged pigment particle from agglomerating. The particles can be used for electrophoretic displays.

Abstract: A composition for forming a ferroelectric thin film includes: a PZT sol-gel solution including at least one of: a whole or partial hydrolysate of a lead precursor and a whole or partial hydrolyzed and polycondensated product thereof; a whole or partial hydrolysate of a zirconium precursor, a whole or partial hydrolyzed and polycondensated product thereof, and a zirconium complex having at least one hydroxy ion and at least one non-hydrolyzable ligand; and a whole or partial hydrolysate of a titanium precursor, a whole or partial hydrolyzed and polycondensated product thereof, and a titanium complex having at least one hydroxyl ion and at least one non-hydrolyzable ligand; and a Bi2SiO5 sol-gel solution including at least one of: a whole or partial hydrolysate of a silicon precursor and a whole or partial hydrolyzed and polycondensated product thereof, and a resultant obtained by refluxing triphenyl bismuth as a bismuth precursor.

Abstract: Optical compensation films (positive C-plate) with mesogen anisotropic subunits (OASUs) that have high positive birefringence throughout the wavelength range 400 nm<?<800 nm are provided. The optical compensation films may be processed by solution casting to yield a polymer film with high birefringence without the need for stretching, photopolymerization, or other processes. Such optical compensation films are suitable for use as a positive C-plate in LCDs, particularly IPS-LCDs.

Abstract: A colored photosensitive resin composition comprising an alkali-soluble resin, a photosensitive compound, a curing agent, a solvent and a colorant represented by the formula (I): The colored photosensitive resin composition can form a color filter array which shows good spectral characteristics.

Abstract: A colored photosensitive resin composition comprises a compound represented by the formula (I) or a salt thereof: wherein R10, R11, R13 and R14 represent independently of each other a hydrogen atom or an alkyl group; R12 represents a sulfonic acid group, a carboxylic acid group, an ester thereof, or an amide represented by the formula (1) —SO2NHR15 , and ??(1) X? represents BF4?, PF6?, Y? or YO4? (in which Y represents a halogen atom), or a dye having a sulfonic acid group.

Abstract: Compositions are provided for alleviating or preventing discoloration, known as “scorching”, in flame-retarded flexible polyurethane foams. The anti-scorch compositions contain combinations of antioxidant agents, epoxy compounds, organic phosphites—alone or in combination with metal salts of carboxylic acids. The compositions are useful, for example, for polyurethane foams retarded with aliphatic or aromatic phosphorus-based flame retardants, or with halogen-containing flame retardants.

Abstract: An electronic device with an elevating mechanism includes a body and the elevating mechanism connected with the body. The elevating mechanism includes a support base, an elevating element, and a fastening element. The elevating element capable of moving between a first position and a second position relative to the support base is connected with both the support base and the body. The elevating element includes a first wedging component. The fastening element disposed around the second position relative to the support base is rotatable between a third position and a fourth position. The fastening element includes a second wedging component. When the fastening element is rotated to the fourth position, the second wedging component is wedged on the first wedging component for fastening the elevating element at the second position.

Abstract: A door and board lifting device comprising a foot operated lever and locking means wherein said locking means is operative to releasably secure the lever in a substantially fixed position.

Abstract: An interwoven, adhesive backed, electric fence barrier ribbon and tape and a method of weaving thereof. The present invention discloses a fully self contained electric fencing system that is adaptable to many conditions and one that does not require a ground rod or any special soil conditions to operate. The invention accomplishes this by providing two different groups of conductors, each being electrically potentially different from the other and all weaved within the same tape for use with high voltage or low voltage systems. The invention also provides for an efficient and cost effective system to mass produce the product and further more it can be produced in a multitude of color coordinated choices as set forth in the following specifications. Objects and Advantages: The configuration of this design allows for the mass production of this invention with a very cost effective system using tools and machinery that are commonly known to those in this field.

Abstract: A gate assembly prevents keyless ingress into, and enables keyless egress from, a gated area. The gate assembly comprises a gate frame and a gate. The gate frame comprises rectangular or 360 degree frame structure for maintaining a planar gate-receiving area despite ground deformations and the like. The gate comprises rectangular gate structure that defines a planar frame-engaging area. The gate-receiving area is greater in magnitude than the frame-engaging area. The gate further comprises a state of the art interior push bar latch for enabling keyless egress, and state of the art keyed lock for preventing keyless ingress into the gated or secure area. An inferior frame member is anchored in subterranean media for positioning the gate frame during installation for maintaining the gate-receiving area should ground deformations occur.

Abstract: An anchor assembly for a temporary fence; said assembly comprising a base portion and a superposed insert portion; each said base portion and said superposed insert portion comprising a composite of a shell open at the underside, and a settable material filling said shell; and wherein respective pairs of formers integral to each said shell of said base portion and said superposed portion, define substantially vertical pairs of passages through said base portion and said superposed insert portion; said passages arranged so that when said base portion and said superposed insert portion are assembled together, respective pairs of said passages are in vertical alignment; said passages adapted for receiving therethrough respective ends of uprights of adjacent panels of said temporary fence; said ends passing through both said superposed insert portion and said base portion.

Abstract: A hingeless fence assembly is described as having a free-standing post and a tubular member. The free-standing post extends upwardly from a hole in the ground and is positioned within the ground to a depth sufficient to provide the necessary stability. The tubular member is rotatably received over the free-standing post and has a greater diameter than the free-standing post. The tubular member is free to rotate about the free-standing post.

Abstract: Phase change memory devices and fabrication methods thereof. A phase change memory device comprises a stacked heating element with a conductive portion and a relatively high resistive portion, wherein the relatively high resistive portion includes a nitrogen-containing metal silicide part. The heating stacked element such as a highly resistive nitrogen-containing metal silicide (MSixNy) is formed by a self-aligned silicidizing and nitrifying process. Self-aligned silicidization can be achieved by nitrogen ion implantation or nitrogen-containing plasma treatment. The resistance of the heating element can be regulated by adjusting the content of nitrogen or degree of nitrification.

Abstract: A conjugated polymer layer with a built-in diode is formed by providing a first metal-chalcogenide layer over a bottom electrode. Subsequently, a second metal-chalcogenide layer is provided over and in contact with the first metal-chalcogenide layer. The first metal-chalcogenide layer has a first conductivity type and the second metal-chalcogenide layer has a second conductivity type. The plane of contact between the first and second metal-chalcogenide layers creates the p-n junction of the built-in diode. Then a polymer layer is selectively deposited on the second metal-chalcogenide layer. The second metal-chalcogenide layer provides ions to the polymer layer to change its resistivity. A top electrode is then provided over the polymer layer. An exemplary memory cell may have the following stacked structure: first electrode/n-type semiconductor/p-type semiconductor/conjugated polymer/second electrode.

Abstract: Provided are a phase-change memory device using a phase-change material having a low melting point and a high crystallization speed, and a method of fabricating the same. The phase-change memory device includes an antimony (Sb)-selenium (Se) chalcogenide SbxSe100-x phase-change material layer contacting a heat-generating electrode layer exposed through a pore and filling the pore. Due to the use of SbxSe100-x in the phase-change material layer, a higher-speed, lower-power consumption phase-change memory device than a GST memory device can be manufactured.

Abstract: A phase change memory device for preventing thermal cross-talk includes lower electrodes respectively formed in a plurality of phase change cell regions of a semiconductor substrate. A first insulation layer is formed on the semiconductor substrate including the lower electrodes having holes for exposing the respective lower electrodes. Heaters are formed on the surfaces of the respective holes to contact the lower electrodes. A second insulation layer is formed to fill the holes in which the heaters are formed. A mask pattern is then formed on the first and second insulation layers, including the heaters, to have openings that expose portions of the respective heaters having a constant pitch. A phase change layer is formed on the mask pattern including the exposed portions of the heaters and the first and second insulation layers and subsequently, upper electrodes are formed on the phase change layer.

Abstract: A phase change memory device and method of manufacturing the same is provided. A first electrode having a first surface is provided on a substrate. A second electrode having a second surface at a different level from the first surface is on the substrate. The second electrode may be spaced apart from the first electrode. A third electrode may be formed corresponding to the first electrode. A fourth electrode may be formed corresponding to the second electrode. A first phase change pattern may be interposed between the first surface and the third electrode. A second phase change pattern may be interposed between the second surface and the fourth electrode.

Abstract: A microelectronic programmable structure suitable for storing information and array including the structure and methods of forming and programming the structure are disclosed. The programmable structure generally includes an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying energy to the structure, and thus information may be stored using the structure.

Abstract: Methods of making nanometer-scale semiconductor structures with controlled size are disclosed. Semiconductor structures that include one or more nanowires are also disclosed. The nanowires can include a passivation layer or have a hollow tube structure.

Abstract: The present invention provides a semiconductor light emitting element with excellent color rendering properties, a method for manufacturing the semiconductor light emitting element, and a light emitting device. The semiconductor light emitting element includes: a semiconductor substrate that has a convex portion having a tilted surface as an upper face, and a concave portion formed on either side of the convex portion, the concave portion having a smaller width than the convex portion, a bottom face of the concave portion being located in a deeper position than the upper face of the convex portion; and a light emitting layer that is made of a nitride-based semiconductor and is formed on the semiconductor substrate so as to cover at least the convex portion.

Abstract: A light emitting diode (LED) having well and/or barrier layers with a superlattice structure is disclosed. An LED has an active region between an N-type GaN-based semiconductor compound layer and a P-type GaN-based semiconductor compound layer, wherein the active region comprises well and/or barrier layers with a superlattice structure. As the well and/or barrier layers with a superlattice structure are employed, it is possible to reduce occurrence of defects caused by lattice mismatch between the well layer and the barrier layer.

Abstract: The present invention is a semiconductor light emitting device including an n-type semiconductor layer, an active layer, a first p-type semiconductor layer between the n-type semiconductor layer and the active layer, and a second p-type semiconductor layer on the opposite side of the first p-type semiconductor layer from the active layer. Further, the present invention is a nitride semiconductor light emitting device including an n-type nitride semiconductor layer, a nitride semiconductor active layer, a first p-type nitride semiconductor layer between the n-type nitride semiconductor layer and the nitride semiconductor active layer, and a second p-type nitride semiconductor layer on the opposite side of the first p-type nitride semiconductor layer from the nitride semiconductor active layer.

Abstract: In one embodiment, the present invention includes a method for forming a transistor that includes forming a first buffer layer of silicon germanium tin (SiGe(Sn)) on a silicon (Si) substrate, forming a barrier layer on the first buffer layer, the barrier layer comprising silicon germanium (Si1-xGex), and forming a quantum well (QW) layer on the barrier layer including a lower QW barrier layer formed of silicon germanium carbon (Si1-yGey(C)), a strained QW channel layer formed of germanium on the lower QW layer, and an upper QW barrier layer on the strained QW channel layer formed of Si1-zGez(C). Other embodiments are described and claimed.

Abstract: A method of fabricating a quantum well device includes forming a diffusion barrier on sides of a delta layer of a quantum well to confine dopants to the quantum well.

Abstract: A metal-base transistor is suggested. The transistor comprises a first and a second electrode (2, 6) and base electrode (6) to control current flow between the first and second electrode. The first electrode (2) is made from a semiconduction material. The base electrode (3) is a metal layer deposited on top of the semiconducting material forming the first electrode. According the invention the second electrode is formed by a semiconducting nanowire (6) being in electrical contact with the base electrode (3).

Abstract: A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection including an Si material and a Si1-xGex material; and exposing the first projection to preferential oxidation to yield a second projection including a center region comprising Ge/Si1-yGey and a covering region comprising SiO2 and enclosing the center region.

Abstract: A computing element for use in a quantum computer has at least three coupled quantum dots, and at least one gate for applying an electric field to manipulate the state of said qubit.

Abstract: In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.

Abstract: A nanoscale device and a method for creating and erasing of nanoscale conducting regions at the interface between two insulating oxides SrTiO3 and LaAlO3 is provided. The method uses the tip of a conducting atomic force microscope to locally and reversibly switch between conducting and insulating states. This allows ultra-high density patterning of quasi zero or one dimensional electron gas conductive regions, such as nanowires and conducting quantum dots respectively. The patterned structures are stable at room temperature after removal of the external electric field.

Abstract: A quantum computing device and method employs qubit arrays of entangled states using negative refractive index lenses. A qubit includes a pair of neutral atoms separated by or disposed on opposite sides of a negative refractive index lens. The neutral atoms and negative refractive index lens are selectively energized and/or activated to cause entanglement of states of the atoms. The quantum computing device enjoys a novel architecture that is workable and scalable in terms of size and wavelength.

Abstract: It is provided an organic semiconductor element having an FET which can control a channel length to a small value and does not cause a rise in contact resistance due to a step portion, and an organic light emitting display device with a large aperture using the same. A first conductive layer (2) which is one of source/drain electrodes is provided onto a substrate (1), and an organic semiconductor layer (3) and a second conductive layer (4) which is the other electrode of the source/drain electrodes are provided onto the first conductive layer (2). Then on a side face of the organic semiconductor layer or a front surface of the organic semiconductor layer (3) exposed by removing a part of the second conductive layer and a side face of the second conductive layer a gate electrode (third conductive layer) (6) is provided via an insulating layer (5), thereby to form an FET. The organic EL display device has the FET having such structure laminated on an organic EL section as a drive element.

Abstract: An electronic device including in any sequence: (a) a semiconductor layer; and (b) a phase-separated dielectric structure comprising a lower-k dielectric polymer and a higher-k dielectric polymer, wherein the lower-k dielectric polymer is in a higher concentration than the higher-k dielectric polymer in a region of the dielectric structure closest to the semiconductor layer.

Abstract: A method for a thin film transistor array panel includes forming a gate line and a pixel electrode on a substrate, forming a gate insulating layer covering the gate line, forming a data line including a source electrode and a drain electrode on the gate insulating layer, forming an interlayer insulating layer covering the data line and the drain electrode on the gate insulating layer, forming a first opening in the interlayer insulating layer, forming an organic semiconductor in the first opening, forming a passivation layer on the organic semiconductor and the interlayer insulating layer, and forming a second opening in the interlayer insulating layer to expose the pixel electrode.

Abstract: A method for manufacturing a semiconductor device includes: forming a source electrode and a drain electrode on a substrate; forming an organic semiconductor layer including a ? conjugated organic compound at least between the source electrode and the drain electrode; applying an application liquid on the organic semiconductor layer, the application liquid being made of a polymer of an alicyclic compound dissolved in a paraffin hydrocarbon solvent that is a carbocyclic compound without having aromaticity; forming a gate insulation layer including the polymer of the alicyclic compound by removing the paraffin hydrocarbon solvent from the application liquid; and forming a gate electrode on the gate insulation layer.

Abstract: The invention relates to an organic component and an electric circuit containing at least one organic component of this type, comprising the following layers: a first electrode layer composed of a first electrically conductive material, a second electrode layer composed of a second electrically conductive material, an organic semiconductor layer, and at least one insulator layer composed of a dielectric material; wherein a) the first electrode layer and the second electrode layer are arranged in the same plane alongside one another at a distance A, b) the organic semiconductor layer at least partly covers the first electrode layer and the second electrode layer and furthermore spans the distance A, and wherein c) a first insulator layer covers the organic semi-conductor layer on its side remote from the two electrode layers.

Abstract: A flat panel display device including a first region having an organic light emitting diode and a thin film transistor and a second region having a capacitor is disclosed. The capacitor comprises first, second, and third electrodes, where the area of a third capacitor electrode is reduced, thereby ensuring a distance between a first power voltage line and the third capacitor electrode. The total area of the capacitor is compensated by increasing the area of the first capacitor electrode. Thus, the area of the third capacitor electrode is reduced while the total capacitance of the capacitor is maintained, thereby preventing a dark spot caused by a short circuit between the first power voltage line and the third capacitor electrode.

Abstract: Semiconductor integrated test structures are designed for electron beam inspection of semiconductor wafers. The test structures include pattern features that are formed in designated test regions of the wafer concurrently with pattern features of integrated circuits formed on the wafer. The test structures include conductive structures that are designed to enable differential charging between defective and non-defective features (or defective and non-defection portions of a given feature) to facilitate voltage contrast defect detection of CMOS devices, for example, using a single, low energy electron beam scan, notwithstanding the existence of p/n junctions in the wafer substrate or other elements/features.

Abstract: A device or method for effectively stressing an interconnect in a test current path of a semiconductor device, which test current path is other than a current path used during normal operation of the semiconductor device. An operational voltage is adjusted to a test voltage, the test current path is opened and the test voltage is supplied to the test current path.

Abstract: By forming a trench-like test opening above a respective test metal region during the etch process for forming via openings in a dielectric layer stack of sophisticated metallization structures of semiconductor devices, the difference in etch rate in the respective openings may be used for generating a corresponding variation of electrical characteristics of the test metal region. Consequently, by means of the electrical characteristics, respective variations of the etch process may be identified.

Abstract: A semiconductor device includes a first circuit substrate having a plurality of lower wiring lines and a plurality of upper wiring lines on the lower surface side and upper surface side thereof, respectively. A second circuit substrate is provided on a lower side of the first circuit substrate, the second circuit substrate having an opening which exposes part of the first circuit substrate, the second circuit substrate also having, on the lower surface side thereof, a plurality of external-connection connection pads and a plurality of test connection pads connected to the lower wiring lines. A first semiconductor construct is disposed on the lower side of the first circuit substrate within the opening of the second circuit substrate, the first semiconductor construct having a plurality of external connection electrodes connected to the lower wiring lines.

Abstract: A design structure for an electrically tunable resistor. In one embodiment, the design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, and includes a resistor including: a first resistive layer; at least one second resistive layer; and an intermediate interdiffused layer of the first resistive layer and the at least one second resistive layer.

Abstract: The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs.