Abstract: A second semiconductor chip including the operation of receiving operation instructions given from a first semiconductor chip and outputting a signal corresponding to it is mounted on mounting means. Internal wirings for interconnecting the first and second semiconductor chips, and external terminals respectively connected to the internal wirings are provided in the mounting means to constitute a multi chip module. Further, a signal path for selectively invalidating operation instructions from the first semiconductor chip to the second semiconductor chip is provided inside the module.

Abstract: There is provided a semiconductor device including a substrate and a semiconductor film deposited on the substrate, characterized in that the semiconductor film has a laterally grown crystal having an end with a surface projection height smaller than the thickness of the semiconductor film. There are also provided a semiconductor device fabrication method and apparatus utilizing a method and apparatus for fabricating the semiconductor device, that is capable of reducing a surface projection height or a ridge formed in a last region in repeating laser exposure in the SLS method, and a semiconductor device fabricated thereby.

Abstract: A method of manufacturing a pixel structure is provided. A first patterned conductive layer including a gate and a data line is formed on a substrate. A gate insulating layer is formed to cover the first patterned conductive layer and a semiconductor channel layer is formed on the gate insulating layer above the gate. A second patterned conductive layer including a scan line, a common line, a source and a drain is formed on the gate insulating layer and the semiconductor channel layer. The scan line is connected to the gate and the common line is located above the data line. The source and drain are located on the semiconductor channel layer, and the source is connected to the data line. A passivation layer is formed on the substrate to cover the second patterned conductive layer. A pixel electrode connected to the drain is formed on the passivation layer.

Abstract: Disclosed herein is a method of manufacturing a thin film transistor including titanium oxides as an active layer and the structure of the thin film transistor film manufactured using the method. The thin film transistor includes: a substrate; an active layer formed on the substrate using polycrystalline or amorphous titanium oxides; and an insulating layer formed on the active layer. Further, the method of manufacturing the thin film transistor includes: forming a substrate; forming an active layer on the substrate using polycrystalline or amorphous titanium oxides; and forming an insulating layer on the active layer.

Abstract: A liquid crystal display (LCD) includes: a first substrate divided into a pixel part and first and second pad parts; a gate electrode and a gate line formed at the pixel part of the first substrate; an active pattern formed as an island on the gate electrode and having a width smaller than the gate electrode; an insulation film formed on the first substrate and having first and second contact holes exposing source and drain regions of the active pattern, respectively; source and drain electrodes formed at the pixel part of the first substrate and electrically connected with the source and drain regions of the active pattern via the first and second contact holes; a data line formed at the pixel part of the first substrate and crossing the gate line to define a pixel region; an etch stopper positioned between the source and drain electrodes and formed as an insulation film; a pixel electrode electrically connected with the drain electrode; and a second substrate attached with the first substrate in a facing ma

Abstract: A TFT array panel includes: first and second gate members connected to each other; a gate insulating layer formed on the first and the second gate members; first and second semiconductor members formed on the gate insulating layer opposite the first and the second gate members, respectively; first and second source members connected to each other and located near the first and the second semiconductor members, respectively; first and second drain members located near the first and the second semiconductor members, respectively, and located opposite the first and the second source members with respect to the first and the second gate members, respectively; and a pixel electrode connected to the first and the second drain members. The first gate, semiconductor, source, and drain members form a first TFT, and the second gate, semiconductor, source, and drain members form a second TFT.

Abstract: A thin film field effect transistor including, on a substrate, at least a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode, wherein an electric resistance layer is provided in electric connection between the active layer and at least one of the source electrode or the drain electrode.

Abstract: A rewritable nonvolatile memory cell is disclosed comprising a steering element in series with a carbon nanotube fabric. The steering element is preferably a diode, but may also be a transistor. The carbon nanotube fabric reversibly changes resistivity when subjected to an appropriate electrical pulse. The different resistivity states of the carbon nanotube fabric can be sensed, and can correspond to distinct data states of the memory cell. A first memory level of such memory cells can be monolithically formed above a substrate, a second memory level monolithically formed above the first, and so on, forming a highly dense monolithic three dimensional memory array of stacked memory levels.

Abstract: One embodiment of the present invention is a thin film transistor, including: an insulating substrate; a gate electrode, a gate insulating layer and a semiconductor layer including an oxide, these three elements being formed over the insulating substrate in this order, and the gate insulating layer including: a lower gate insulating layer, the lower gate insulating layer being in contact with the insulating substrate and being an oxide including any one of the elements In, Zn or Ga; and an upper gate insulating layer provided on the lower gate insulating layer, the upper gate insulating layer comprising at least one layer; and a source electrode and a drain electrode formed on the semiconductor layer.

Abstract: A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing.

Abstract: A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell. A semiconductor active region of the first memory cell is formed epitaxially on a semiconductor active region of the second memory cell, such that a defined boundary exists between the semiconductor active region of the first memory cell and the semiconductor active region of the second memory cell.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include amorphizing at least one contact area of a source/drain region of a transistor structure by implanting through at least one contact opening, forming a first layer of metal on the at least one contact area, forming a second layer of metal on the first layer of metal, selectively etching a portion of the second metal layer, and annealing the at least one contact area to form at least one silicide.

Abstract: In accordance with the invention, there are CMOS devices and semiconductor devices and methods of fabricating them. The CMOS device can include a substrate including a first active region and a second active region and a first transistor device over the first active region, wherein the first transistor device includes a high-K layer over the first active region, a first dielectric capping layer on the high-K layer, and a first metal gate layer over the first dielectric capping layer. The CMOS device can also include a second transistor device over the second active region, wherein the second transistor device includes a high-K layer over the second active region, a second dielectric capping layer on the second high-K layer, and a second metal gate layer over the second dielectric capping layer.

Abstract: A semiconductor device includes: a first semiconductor layer which is made of a first group III nitride semiconductor; a cap layer which is formed on the first semiconductor layer, which is made of a second group III nitride semiconductor, and which has an opening for exposing the first semiconductor layer; and a source electrode and a drain electrode which are formed on the cap layer so as to oppose to each other with the opening interposed. A gate electrode is formed on the bottom face of the opening with an insulating film interposed. The insulating film is formed on at least a part of the first semiconductor layer which is exposed through the opening.

Abstract: A compound semiconductor device having a transistor structure, includes a substrate, a first layer formed on the substrate and comprising GaN, a second layer formed over the first layer and containing InN whose lattice constant is larger than the first layer, a third layer formed over the second layer and comprising GaN whose energy bandgap is smaller than the second layer, and a channel region layer formed on the third layer.

Abstract: A light emitting element has a substrate of gallium oxides and a pn-junction formed on the substrate. The substrate is of gallium oxides represented by: (AlXInYGa(1-X-Y))2O3 where 0?x?1, 0?y?1 and 0?x+y?1. The pn-junction has first conductivity type substrate, and GaN system compound semiconductor thin film of second conductivity type opposite to the first conductivity type.

Abstract: A method for fabricating a diode is disclosed. In one embodiment, the method includes forming a Schottky contact on an epitaxial layer of silicon carbide (SiC) and annealing the Schottky contact at a temperature in the range of 300° C. to 700° C. The Schottky contact is formed of a layer of molybdenum.

Abstract: A high quality single crystal wafer of SiC is disclosed having a diameter of at least about 100 mm and a micropipe density of less than about 25 cm?2.

Abstract: A semiconductor epitaxial substrate includes: a single crystal substrate; an AlN layer epitaxially grown on the single crystal substrate; and a nitride semiconductor layer epitaxially grown on the AN layer, wherein an interface between the AlN layer and nitride semiconductor layer has a larger roughness than an interface between the single crystal substrate and AlN layer, and a skewness of the upper surface of the AlN layer is positive.

Abstract: A method for increasing ambient light contrast ratio within an electroluminescent device, including: a reflective electrode and a transparent electrode having an EL unit formed there-between. The EL unit includes a light-emitting layer containing quantum dots. Additionally, the method includes locating a contrast enhancement element on a side of the transparent electrode opposite the EL unit. The contrast enhancement element includes a patterned reflective layer and a patterned light-absorbing layer whose patterns define one or more transparent openings, so that light emitted by the light-emitting layer passes through the one or more transparent openings. The patterned reflective layer is located between the patterned light absorbing layer and the transparent electrode.

Abstract: An electroluminescent device comprising: a substrate; one or more light-emitting elements formed over the substrate, the one or more light-emitting elements including first and second spaced-apart electrodes wherein at least one of the first and second electrodes is transparent and a light-emitting layer comprising quantum dots formed between the first and second electrodes; a cover located over the one or more light-emitting elements and spaced apart from the one or more light-emitting elements to form a gap between the cover and the one or more light-emitting elements; and separately formed spacer elements located in the gap between the cover and the one or more light-emitting elements and wherein the spacer elements are in physical contact with the one or more light-emitting elements, the cover, or both the one or more light-emitting elements and the cover.

Abstract: Disclosed is an AC light emitting device having photonic crystal structures and a method of fabricating the same. The light emitting device includes a plurality of light emitting cells and metallic wirings electrically connecting the light emitting cells with one another. Further, each of the light emitting cells includes a first conductive type semiconductor layer, a second conductive type semiconductor layer disposed on one region of the first conductive type semiconductor layer, and an active layer interposed between the first and second conductive type semiconductor layers. In addition, a photonic crystal structure is formed in the second conductive type semiconductor layer. The photonic crystal structure prevents light emitted from the active layer from laterally propagating by means of a periodic array, such that light extraction efficiency of the light emitting device can be improved.

Abstract: A semiconductor light-emitting device of the present invention includes a first LED chip whose emitted light is wavelength-converted by a fluorescent substance layer formed by applying and curing a fluorescent substance material, and a second LED chip whose emitted light is not wavelength-converted by the fluorescent substance layer, wherein the first LED chip and the second LED chip are arranged on a substrate in such a way that a level of an emission layer of the second LED chip is higher than that of a top face of the first LED chip above the substrate.

Abstract: A light-emitting device including: a substrate; a light-emitting diode; and an optical resonance layer to resonate light emitted from the light-emitting diode. The optical resonance layer includes a first layer, including a polysilsesquioxane-based copolymer. A linking group connecting two different silicon (Si) atoms of the polysilsesquioxane-based copolymer can be —O—, or a substituted or unsubstituted C1-C30 alkylene group.

Abstract: A semiconductor light emitting device, includes an active layer radiating a light having a predetermined wavelength; a first semiconductor layer of a first conductivity type, provided on the active layer. A semiconductor substrate has a first principal surface in contact with the active layer, a second principal surface facing the first principal surface, and side surfaces connected to the second principal surface. Each of the side surfaces has a bevel angle in a range from about 45 degrees to less than 90 degrees with respect to the second principal surface. A second semiconductor layer of a second conductivity type is provided under the active layer. A first electrode is provided under the second semiconductor layer. A distance between the active layer and the first electrode depends on the wavelength and a refractive index of the second semiconductor layer.

Abstract: [Problem] To provide an adhesive sheet which is used for a light-emitting diode device, and which is free from cracks and peeling off of the adhered portions. [Means for Solving the Problem] An adhesive sheet for a light-emitting diode device, which comprises a thermoplastic polymer containing epoxy groups and a compound containing functional groups which are addition reactive with the epoxy groups or a polymerization catalyst which can effect a ring opening polymerization of the epoxy groups, and in which said thermoplastic polymer is cross-linked so that its flowability is restrained.

Abstract: A light emitting diode (LED) module. The LED module includes: an LED chip, for emitting a light beam; a packaging structure, for packaging the LED chip; and a light direction changing unit, connected to the packaging structure, for changing a direction of the light beam, wherein the light direction changing unit has a base material and at least a photoluminescent material, and the photoluminescent material is mixed within the base material to form the light direction changing unit.

Abstract: In one embodiment, an AlInGaP LED includes a bottom n-type layer, an active layer, a top p-type layer, and a thick n-type GaP layer over the top p-type layer. The thick n-type GaP layer is then subjected to an electrochemical etch process that causes the n-type GaP layer to become porous and light-diffusing. Electrical contact is made to the p-GaP layer under the porous n-GaP layer by providing metal-filled vias through the porous layer, or electrical contact is made through non-porous regions of the GaP layer between porous regions. The LED chip may be mounted on a submount with the porous n-GaP layer facing the submount surface. The pores and metal layer reflect and diffuse the light, which greatly increases the light output of the LED. Other embodiments of the LED structure are described.

Abstract: A light emitting diode apparatus includes a heat dissipating substrate, a composite layer, an epitaxial layer, a first electrode and a second electrode. The composite layer includes a reflective layer, a transparent conductive layer and a patterned insulating thermoconductive layer, which is disposed between the reflective layer and the transparent conductive layer. The composite layer is disposed between the heat dissipating substrate and the epitaxial layer and allows currents to concentrate to the reflective layer or the transparent conductive layer and then to be diffused evenly through the transparent conductive layer. The epitaxial layer includes a first semiconductor layer electrically connected with the first electrode, an active layer and a second semiconductor layer electrically connected with the second electrode.

Abstract: To provide a light emitting device that is improved in intensity of light emitted from a light outgoing surface and has excellent heat releasing property, the light emitting device according to the present invention includes an LED chip 501 mounted on a substrate and an insulating section 509 formed on a front surface of the substrate and made of light-transmitting resin. The insulating section 509 has a multilayer structure constituted of a titanium dioxide-added resin layer 509c to which titanium dioxide is added and a titanium dioxide-free resin layer 509b to which no titanium dioxide is added.

Abstract: There is provided a light emitting device that can minimize reflection or absorption of emitted light, maximize luminous efficiency with the maximum light emitting area, enable uniform current spreading with a small area electrode, and enable mass production at low cost with high reliability and high quality. A light emitting device according to an aspect of the invention includes a light emitting lamination including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer, and a conductive substrate at one surface thereof. Here, the light emitting device includes a barrier unit separating the light emitting lamination into a plurality of light emitting regions, a first electrode structure, and a second electrode structure. The first electrode structure includes a bonding unit, contact holes, and a wiring unit connecting the bonding unit to the contact holes.

Abstract: A light emitting device includes a pair of electrodes, wherein at least one electrode is transparent or semi-transparent, and an phosphor layer provided between the pair of electrodes, wherein the phosphor layer includes a layer having nitride semiconductor particles, and wherein the nitride semiconductor particles have metal nano structures precipitated in grain boundaries between the nitride semiconductor particles.

Abstract: The present invention relates to a light emitting diode (LED) package. An object of the present invention is to provide an LED package having a metal PCB, which has a superior heat dissipation property and a compact structure, does not largely restrict use of conventional equipments, and is compatible with an electronic device or illumination device currently used widely. To this end, an LED package according to the present invention comprises a metal printed circuit board (PCB) formed by laminating first and second sheet metal plates with an electric insulating layer interposed therebetween; and an LED chip mounted on the first sheet metal plate of the metal PCB, wherein the first sheet metal plate has electrode patterns and leads respectively extending from the electrode patterns.

Abstract: Disclosed is a light emitting diode lamp that has low resistance to heat emitted therefrom. The LED lamp may include a heat coupling member thermally coupling a top part of a first lead to a top part of a second lead. The LED lamp may further include one or more top parts for lowering thermal resistance of the LED lamp. This configuration facilitates heat transfer from the first lead having an LED chip mounted thereon to the top part of the second lead and/or to the other top parts, lowering resistance to heat emitted from the LED lamp.

Abstract: An improved LED chip packaging structure includes a substrate, an insulating layer, a light emitting chip and sealing adhesive. At least two conductive traces are disposed on at least one side surface of the substrate. The insulating layer attaches on one side surface of the substrate and includes an insulating film. The light emitting chip is received in the through hole of the insulating layer and attaches on one side surface of the substrate. An adhesive is securing the light emitting chip on the substrate, and the light emitting chip connects with at least one conducting wire. The sealing adhesive is filled into the through hole of the insulating layer. By the direct combination of the light emitting chip and the substrate, the present invention has the advantageous of low cost, the heat dispersal effect is improved, the packaging efficiency is increased, and the market competition is enhanced.

Abstract: A semiconductor light-emitting device includes a lead frame, a semiconductor light-emitting element mounted on the top surface of the bonding region, and a case covering part of the lead frame. The bottom surface of the bonding region is exposed to the outside of the case. The lead frame includes a thin extension extending from the bonding region and having a top surface which is flush with the top surface of the bonding region. The thin extension has a bottom surface which is offset from the bottom surface of the bonding region toward the top surface of the bonding region.

Abstract: A light emitting device of the invention includes an electron transporting layer, a hole transporting layer provided mutually facing the electron transporting layer with a distance between the hole transporting layer and the electron transporting layer, a phosphor layer having a layer of a plurality of semiconductor fine particles sandwiched between the electron transporting layer and the hole transporting layer, a first electrode provided facing the electron transporting layer and connected electrically, and a second electrode provided facing the hole transporting layer and connected electrically: in which the semiconductor fine particles composing the phosphor layer have a p-type part and an n-type part inside of the particles and have a pn-junction in the interface of the p-type part and the n-type part and are arranged in a manner that the p type part is partially brought into contact with the hole transporting layer and at the same time, the n type part is partially brought into contact with the electron

Abstract: A Group III-V semiconductor device bonded to a conductive support substrate, which device has a side surface whose surface layer has a high-resistance region formed through ion implantation.

Abstract: A semiconductor switch comprises a PNPN structure arranged to provide an SCR-like functionality, and a MOS gate structure, preferably integrated on a common substrate. The switch includes ohmic contacts for the MOS gate, and for the cathode and gate regions of the PNPN structure; the anode contact is intrinsic. A fixed voltage is typically applied to an external node. The MOS gate structure allows current to be conducted between the external node and the intrinsic anode when on, and the PNPN structure conducts the current from the anode to the cathode when an appropriate voltage is applied to the gate contact. Regenerative feedback keeps the switch on once it begins to conduct. The MOS gate inhibits the flow of current between the external node and anode—and thereby turns off the switch—when off. When on, the MOS gate's channel resistance serves as a ballast resistor.

Abstract: In a high breakdown voltage semiconductor element among elements integrated together on an SOI substrate in which its rated voltage is shared between an embedded oxide layer and a drain region formed by an element active layer, both high integration and high breakdown voltage are realized while also securing suitability for practical implementation and practical use. The high breakdown voltage is realized without hampering size reduction of the element by forming an electrically floating layer of a conductivity type opposite to that of the drain region at the surface of the drain region. Further, the thickness of the embedded oxide layer is reduced to a level suitable for the practical implementation and practical use by setting the thickness of the element active layer of the SOI substrate at 30 ?m or more.

Abstract: A III-nitride power semiconductor device that includes a first III-nitride power semiconductor device and a second III-nitride power semiconductor device formed in a common semiconductor die and operatively integrated to form a half-bridge.

Abstract: The invention specifies a radiation detector for detecting radiation (8) according to a predefined spectral sensitivity distribution (9) that exhibits a maximum at a predefined wavelength ?0, comprising a semiconductor body (1) with an active region (5) serving to generate a detector signal and intended to receive radiation, in which according to one embodiment the active region (5) includes a plurality of functional layers (4a, 4b, 4c, 4d) that have different band gaps and/or thicknesses and are implemented such that they (4a, 4b, 4c, 4d) at least partially absorb radiation in a range of wavelengths greater than ?0. According to a further embodiment, disposed after the active region is a filter layer structure (70) comprising at least one filter layer (7, 7a, 7b, 7c), said filter layer structure determining the short-wave side (101) of the detector sensitivity (10) according to the predefined spectral sensitivity distribution (9) by absorbing wavelengths smaller than ?0.

Abstract: Source and drain regions of an FET are etched by a crystallographic anisotropic etch to form a cavity surrounded by crystallographic facets. The exposure of the sidewalls of shallow trench isolation (STI) is avoided or reduced compared to the prior art. The crystallographic anisotropic etch may be combined with an isotropic etch or a recess etch to create undercuts beneath gate spacers and/or a pegging line beneath a top surface of the STI. The at least one cavity is then filled with a lattice-mismatched embedded material so that stress is applied to the channel of the FET. The resulting structure has increased containment of the embedded semiconductor region by shallow trench isolation. A reduction in stress due to the unconstrained sidewall area and an increase in the junction current due to the recessing of the pegging line are eliminated or alleviated.

Abstract: A semiconductor device (10) comprising a substrate (12) and an oxide layer (14) formed over the substrate is provided. The semiconductor device further includes a first semiconductor layer (16) having a first lattice constant formed directly over the oxide layer. The semiconductor device further includes a second semiconductor layer (26) having a second lattice constant formed directly over the first semiconductor layer, wherein the second lattice constant is different from the first lattice constant.

Abstract: A transistor structure and a system including the transistor structure. The transistor structure comprises: a substrate including a first layer comprising a first crystalline material; a tensile strained channel formed on a surface of the first layer and comprising a second crystalline material having a lattice spacing that is smaller than a lattice spacing of the first crystalline material; a metal gate on the substrate; a pair of sidewall spacers on opposite sides of the metal gate; and a source region and a drain region on opposite sides of the metal gate adjacent a corresponding one of the sidewall spacers.

Abstract: A method for forming and the structure of a strained vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect to the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (boron) into the body. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials.

Abstract: A semiconductor device includes a substrate common to a first field effect transistor and a second field effect transistor, a channel layer of a first conductivity type formed on the substrate and common to the first and second field effect transistors, a an upper compound semiconductor layer formed on the channel layer and common to the first and second field effect transistors, a compound semiconductor region of a second conductivity type formed in the same layer as the upper compound semiconductor layer, a gate electrode of the first field effect transistor in ohmic contact with the compound semiconductor region, and a gate electrode of the second field effect transistor in Schottky contact with the upper compound semiconductor layer.

Abstract: The objective of the present invention is to provide a semiconductor device of a hetero-junction field effect transistor that is capable of obtaining a high output and a high breakdown voltage and a manufacturing method of the same. The present invention is a semiconductor device of a hetero-junction field effect transistor provided with an AlxGa1-xN channel layer with a composition ratio of Al being x (0<x<1) formed on a substrate, an AlyGa1-yN barrier layer with a composition of Al being y (0<y?1) formed on the channel layer, and source/drain electrodes and a gate electrode formed on the barrier layer, wherein the composition ratio y is larger than the composition ratio x.

Abstract: A method for fabricating nitrogen-face (N-face) nitride-based electronic devices with low buffer leakage, comprising isolating a buffer from a substrate with an AlGaInN nucleation layer to suppress impurity incorporation from the substrate into the buffer. A method for fabricating N-face nitride-based electronic devices with low parasitic resistance and high breakdown, comprising capping a device structure with a conductive layer to provide extremely low access and/or contact resistances, is also disclosed.

Abstract: An elongate stacked semiconductor structure is formed on a substrate. The stacked semiconductor structure includes a second semiconductor material region disposed on a first semiconductor material region. The first semiconductor material region is selectively doped to produce spaced-apart impurity-doped first semiconductor material regions and a lower dopant concentration first semiconductor material region therebetween. Etching exposes a portion of the second semiconductor material region between the impurity-doped first semiconductor material regions. The etching removes at least a portion of the lower dopant concentration first semiconductor material region to form a hollow between the substrate and the portion of the second semiconductor material region between the impurity-doped first semiconductor material regions. An insulation layer that surrounds the exposed portion of the second semiconductor material region between the impurity-doped first semiconductor material regions is formed.