Patents Issued in October 2, 2008
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Publication number: 20080237842Abstract: Methods and apparatus relating to thermally conductive molding compounds are described. In one embodiment, a molding compound may include thermally conductive particles to form a thermally conductive path in the molding compound (e.g., for improved heat dissipation through the molding compound). Other embodiments are also described.Type: ApplicationFiled: March 29, 2007Publication date: October 2, 2008Inventor: Rahul N. Manepalli
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Publication number: 20080237843Abstract: A microelectronic package. The package includes a substrate; a die mounted onto the substrate; an integrated heat spreader mounted onto the substrate, and thermally coupled to a backside of the die; and a sealant material bonding the integrated heat spreader to the substrate, the sealant material having a bulk thermal conductivity above about 1 W/m/° C. and a modulus of elasticity lower than a modulus of elasticity of solder.Type: ApplicationFiled: March 27, 2007Publication date: October 2, 2008Inventors: Ashish Gupta, Leonel R. Arana, David Song, Chia-Pin Chiu, Ravi Prasher, Chris Matayabas, Nirupama Chakrapani
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Publication number: 20080237844Abstract: A microelectronic package includes a package substrate (110, 310, 410), a plurality of dies (120, 610, 630) arranged in a stack (150, 350, 450) above the package substrate, with a first die (121) located above the package substrate at a bottom (151) of the stack and an uppermost die (122) located at a top (152) of the stack, and a plurality of heat spreaders (130, 330, 430, 620) stacked above the first die, with a first heat spreader (131) located above the uppermost die. One of the plurality of heat spreaders is located between each pair of adjacent dies. Each one of the plurality of heat spreaders has an extending portion (132) that extends laterally beyond an edge (123) of an adjacent die, and at least one of the plurality of heat spreaders both provides electrical interconnectivity and thermal conductivity.Type: ApplicationFiled: March 28, 2007Publication date: October 2, 2008Inventors: Aleksandar Aleksov, Vladimir Noveski, Sujit Sharan
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Publication number: 20080237845Abstract: A cooling apparatus includes a substrate; an integrated circuit (IC) die flip-bonded to the substrate; a thermally-conductive layer on one surface of the IC die; and a heat removal chamber having thermally-conductive microporous coat thermally coupled to the conductive layer.Type: ApplicationFiled: March 28, 2007Publication date: October 2, 2008Inventors: Jesse Jaejin Kim, Bao Tran
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Publication number: 20080237846Abstract: A BGA substrate which has a back surface to which a heat radiating plate 5 is attached and an opening for accommodating a relay wiring substrate therein, which is provided in the center of its surface, is used. The relay wiring substrate to which an ASIC chip and a memory chip are flip-chip connected, is bonded to the heat radiating plate in the opening with a thermal conductive bonding material. Further, each of the back surfaces of the ASIC chip and the memory chip is connected to a metal cap for sealing the opening through a thermal conductive material interposed therebetween.Type: ApplicationFiled: March 20, 2008Publication date: October 2, 2008Applicant: OKI ELECTRIC INDUSTRY CO., LTD.Inventors: Makoto Terui, Yasushi Shiraishi
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Publication number: 20080237847Abstract: A power semiconductor module according to the present invention includes: a planar base plate having a plurality of insulated substrates soldered on the top surface, the insulated substrates each having power semiconductor elements to be cooled mounted thereon; a plurality of radiation fins projecting from the bottom surface side of the base plate; and a peripheral wall projecting from the bottom surface side of the base plate so as to surround the radiation fins, the projecting length of the radiation fins is less than or equal to that of the peripheral wall, and the peripheral wall has end surfaces present in the same plane.Type: ApplicationFiled: March 24, 2008Publication date: October 2, 2008Applicant: Nichicon CorporationInventors: Raita Nakanishi, Toshiaki Kawamura
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Publication number: 20080237848Abstract: There is provided a semiconductor device which makes equalization of wirings between address system chips easy and reduce the influence of crosstalk noise and capacitive coupling noise among data system wirings for connecting the chips. There are mounted, on a module board, a plurality of stacked memory chips which a data processor chip simultaneously accesses. Address system bonding pads to which a plurality of memory chips correspond are commonly coupled by a wire to a bonding lead at one end of the module board wiring whose other end is coupled by a wire to an address system bonding pads of the data processor. Data system bonding pads of the data processor chip are individually coupled to data system bonding pads of the memory chip.Type: ApplicationFiled: January 25, 2008Publication date: October 2, 2008Inventors: Yasuhiro Yoshikawa, Motoo Suwa, Kazuyuki Sakata
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Publication number: 20080237849Abstract: A method of making a semiconductor die includes forming a trench around a conductive stud extending from the first side to a second side of a substrate to expose a portion of the stud and then forming a conductive layer inside the trench and in electrical contact with the stud.Type: ApplicationFiled: March 27, 2007Publication date: October 2, 2008Inventor: David Pratt
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Publication number: 20080237850Abstract: A compliant bump structure includes a substrate, at least a first polymer bump, at least a second polymer bump and at least a conductive layer. The substrate has at least a pad on a surface thereof. The first polymer bump is disposed on the pad. The second polymer bump is disposed on the surface of the substrate outside the pad. The conductive layer is disposed on the first and second polymer bumps.Type: ApplicationFiled: October 8, 2007Publication date: October 2, 2008Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventor: Shyh-Ming Chang
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Publication number: 20080237851Abstract: A semiconductor device having a structure in which a semiconductor element and a Cu or Ni electrode are connected by way of a bonding layer comprising Cu, and the Cu bonding layer and the Cu or Ni electrode are diffusion-bonded to each other. The bonding layer is formed by conducting bonding in a reducing atmosphere by using a bonding material containing particles of Cu oxide with an average particle size of 1 nm to 50 ?m and a reducing agent comprising an organic material, thereby providing excellent bonding strength to Ni or Cu electrode.Type: ApplicationFiled: January 25, 2008Publication date: October 2, 2008Inventors: Toshiaki Morita, Yusuke Yasuda, Eiichi Ide
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Publication number: 20080237852Abstract: Provided is a semiconductor device in which a high concentration n type impurity region to be a conductive path and a drain electrode are disposed in an outer circumferential end of the chip to be an inactive region as a device region. Thereby, an up-drain structure is obtained without reducing the device region or without increasing the size of a semiconductor chip. The provided n type impurity region and drain electrode causes a depletion layer of a substrate to be terminated without needing an additional conventional annular region or shield metal. This is because the n type impurity region and the drain electrode also function as the annular region and the shield metal, respectively. With this configuration, a MOSFET with the up-drain structure having necessary components is obtained, while avoiding a reduction of the device region or an increase of the chip area.Type: ApplicationFiled: March 26, 2008Publication date: October 2, 2008Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.Inventors: Tetsuya YOSHIDA, Takuji Miyata
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Publication number: 20080237853Abstract: A conventional semiconductor device has a problem that reduction of a resistance value above a pad electrode is difficult because of an oxide film formed on a surface of the pad electrode. In a semiconductor device of this invention, an oxidation preventing metal layer is formed on a pad electrode, and the oxidation preventing metal layer is exposed at an opening region formed in a spin coat resin film at a portion above the pad electrode. In addition, a plating metal layer and a copper plated layer are formed on the oxidation preventing metal layer. With this structure, the resistance value above the pad electrode is reduced because the top surface of the pad electrode is difficult to oxidize, and the oxidation preventing metal layer having considerably smaller sheet resistivity than an oxidation film serves as part of a current path.Type: ApplicationFiled: March 27, 2008Publication date: October 2, 2008Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.Inventors: Yoshimasa AMATATSU, Minoru AKAISHI, Satoshi ONAI, Katsuya OKABE, Yoshiaki SANO, Akira YAMANE
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Publication number: 20080237854Abstract: First, a substrate having a conductor therein is provided. Next, a first dielectric layer is disposed on the conductor and the substrate and a first opening is formed in the first dielectric layer for exposing the conductor. A first metal layer is deposited over the surface of the first dielectric layer and into the first opening. Next, an etching stop layer and a second metal layer are deposited over the surface of the first metal layer, and a pattern transfer process is performed by using a second dielectric layer as a mask to remove a portion of the first metal layer, the etching stop layer, and the second metal layer for exposing the first dielectric layer. A passivation layer is disposed on the second metal layer and the first dielectric layer and a second opening is formed in the passivation layer to expose a portion of the second metal layer.Type: ApplicationFiled: March 26, 2007Publication date: October 2, 2008Inventors: Ping-Chang Wu, Chieh-Ching Huang
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Publication number: 20080237855Abstract: A BGA package and a substrate for the package are disclosed. A chip is disposed on a top surface of the substrate. A plurality of solder balls are disposed on a plurality of ball pads formed on a bottom surface of the substrate. The substrate has at least a core layer with a plurality of corner cavities filled with low-modulus materials as stress buffer. Additionally, some of the ball pads at the corners of the substrate are disposed under the corner cavities.Type: ApplicationFiled: March 28, 2007Publication date: October 2, 2008Inventors: Wen-Jeng Fan, Tsai-Chuan Yu
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Publication number: 20080237856Abstract: A semiconductor package includes a wiring substrate, a semiconductor chip, and a conductor plate in order to reduce a voltage drop at the central portion of a chip caused by wiring resistance from a peripheral connection pad disposed on the periphery of the chip in the semiconductor package. Central electrode pads for use in ground/power-supply are disposed on the central portion of the chip. The conductor plate for use in ground/power-supply is disposed on the chip such that an insulating layer is disposed therebetween. The central electrode pads on the chip and the conductor plate are connected together by wire bonding through an opening formed in the insulating layer and the conductor plate. An extraction portion of the conductor plate is connected to a power-supply wiring pad on the wiring substrate. The central electrode pads and the conductor plate may also be connected together using gold stud bumps.Type: ApplicationFiled: March 24, 2008Publication date: October 2, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Takashi Hisada, Katsuyuki Yonehara
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Publication number: 20080237857Abstract: There is disclosed a method of making an electronic package (10) by: forming a metal base (50) on which to build the components of an electronic package; applying a mask layer (60) on the base to an area that is not to be occupied by interconnection pads (200) or die attachment pads (201) of the package; plating layers of metal on the un-masked areas of the base to form the interconnection and die attachment pads (200, 201); removing the mask layer; mounting a semiconductor die (302) to at least one die attachment pad (201); electrically connecting the semiconductor die (302) to one or more interconnection pads (200); embedding the components on the base in an encapsulation material (300) to form a package; removing the metal base (50) to leave a package panel; and cutting the panel into discrete package units.Type: ApplicationFiled: December 11, 2007Publication date: October 2, 2008Inventors: Andrew Wye Choong Low, Mee Sing Tiong
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Publication number: 20080237858Abstract: An electronic device includes a conductive pattern formed on a first insulating film, a second insulating film formed on the conductive pattern and the first insulating film, a hole formed in the second insulating film on the conductive pattern, carbon nanotubes formed in the hole to extend from a surface of the conductive pattern, and a buried film buried in clearances among the carbon nanotubes in the hole.Type: ApplicationFiled: March 31, 2008Publication date: October 2, 2008Applicant: FUJITSU LIMITEDInventor: Mizuhisa NIHEI
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Publication number: 20080237859Abstract: An interconnect structure for an integrated circuit and method of forming the interconnect structure. The method includes depositing a metallic layer containing a reactive metal in an interconnect opening formed within a dielectric material containing a dielectric reactant element, thermally reacting at least a portion of the metallic layer with at least a portion of the dielectric material to form a diffusion barrier primarily containing a compound of the reactive metal from the metallic layer and the dielectric reactant element from the dielectric material, and filling the interconnect opening with Cu metal, where the diffusion barrier surrounds the Cu metal within the opening. The reactive metal can be Co, Ru, Mo, W, or Ir, or a combination thereof. The interconnect opening can be a trench, a via, or a dual damascene opening.Type: ApplicationFiled: March 26, 2007Publication date: October 2, 2008Applicant: TOKYO ELECTRON LIMITEDInventors: Tadahiro Ishizaka, Satohiko Hoshino, Kuzuhiro Hamamoto, Shigeru Mizuno, Yasushi Mizusawa
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Publication number: 20080237860Abstract: Embodiments of the invention provide a method for integrating a Ru barrier film with good barrier properties into Cu metallization. The method includes exposing a substrate to a Ta-, Ti-, or W-containing precursor at a substrate temperature below the thermal decomposition temperature of the Ta-, Ti-, or W-containing precursor on the substrate to form a chemisorbed seed layer of partially decomposed Ta-, Ti-, or W-containing precursor on the substrate. The method further includes depositing a Ru barrier film on the chemisorbed seed layer, and forming bulk Cu metal on the Ru barrier film. According to additional embodiments, an interconnect structure and method of forming are provided.Type: ApplicationFiled: March 27, 2007Publication date: October 2, 2008Applicant: TOKYO ELECTRON LIMITEDInventors: Tadahiro Ishizaka, Atsushi Gomi
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Publication number: 20080237861Abstract: A method including introducing a fluorine-free organometallic precursor in the presence of a substrate; and forming a conductive layer including a moiety of the organometallic precursor on the substrate according to an atomic layer or chemical vapor deposition process. A method including forming an opening through a dielectric layer to a contact point; introducing a fluorine-free copper film precursor and a co-reactant; and forming a copper-containing seed layer in the opening. A system including a computer including a microprocessor electrically coupled to a printed circuit board, the microprocessor including conductive interconnect structures formed from fluorine-free organometallic precursor.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Inventors: Juan E. Dominguez, Adrien R. Lavoie, John J. Plombon, Joseph H. Han, Harsono S. Simka, Bryan C. Hendrix, Gregory T. Stauf
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Publication number: 20080237862Abstract: One or more diffusion barriers are formed around one or more conductors in a three dimensional or 3D memory cell. The diffusion barriers allow the conductors to comprise very low resistivity materials, such as copper, that may otherwise out diffuse into surrounding areas, particularly at elevated processing temperatures. Utilizing lower resistivity materials allows device dimension to be reduced by mitigating increases in resistance that occur when the size of the conductors is reduced. As such, more cells can be produced over a given area, thus increasing the density and storage capacity of a resulting memory array.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Inventor: Yoichiro Tanaka
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Publication number: 20080237863Abstract: A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided.Type: ApplicationFiled: April 22, 2008Publication date: October 2, 2008Applicant: Kabushiki Kaisha TosibaInventors: Hiroshi Toyoda, Mitsuhiro Nakao, Masahiko Hasunuma, Hisashi Kaneko, Atsuko Sakata, Toshiaki Komukai
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Publication number: 20080237864Abstract: Provided is a metal interconnection structure of a semiconductor device, including a first metal film pattern disposed on an upper part of an insulation film of a semiconductor substrate; an intermetallic dielectric film having a metal contact plug in which a barrier layer, a metal film for contact plug and a second metal film are sequentially disposed, on the first metal film pattern; and a second metal film pattern disposed on the metal contact plug and intermetallic dielectric film and connected to the metal contact plug.Type: ApplicationFiled: June 10, 2008Publication date: October 2, 2008Applicant: HYNIX SEMICONDUCTOR INC.Inventors: In Cheol Ryu, Sung Gon Jin
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Publication number: 20080237865Abstract: Provided is a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, without limitation, includes forming a first semiconductor layer over a substrate, and forming a second semiconductor layer over the first semiconductor layer, wherein an amorphous nitrided silicon adhesion layer is located between and adheres the first and second semiconductor layers.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Applicant: Texas Instruments IncorporatedInventors: Maria Wang, Erika Leigh Shoemaker, Mary Roby, Stuart Jacobsen
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Publication number: 20080237866Abstract: A semiconductor device is provided having an increased hardness against contact of a probe needle. The semiconductor device includes: a semiconductor substrate; a semiconductor element formed in the semiconductor substrate; an insulating film formed above the semiconductor substrate and covering the semiconductor element; a multilayer wiring structure formed in the insulating film; and a pad electrode structure connected to the multilayer wiring structure and formed on the insulating film, the pad electrode structure including a conductive adhesion film, a conductive pad electrode formed above the conductive adhesion film, and a conductive hydrogen barrier film formed above the conductive pad electrode.Type: ApplicationFiled: June 6, 2008Publication date: October 2, 2008Applicant: FUJITSU LIMITEDInventor: Wensheng WANG
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Publication number: 20080237867Abstract: A semiconductor structure and methods of making the same. The semiconductor structure includes a substrate having a suicide region disposed above a doped region, and a metal contact extending through the silicide region and being in direct contact with the doped region.Type: ApplicationFiled: March 28, 2007Publication date: October 2, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Keith Kwong Hon Wong, Chih-Chao Yang, Haining S. Yang
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Publication number: 20080237868Abstract: An integrated circuit design and a method of fabrication and, more particularly, a semiconductor structure having an ultra narrow crack stop for use in multilevel level devices and a method of making the same. The structure includes a first dielectric layer having a first connection connecting to an underlying interconnect and a second dielectric layer having a second connection connecting to the first connection. A stop gap structure extends through the first dielectric layer and the second dielectric layer, and has a width of about less than 1 um.Type: ApplicationFiled: March 29, 2007Publication date: October 2, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Matthew E. Colburn, William F. Landers, Wai-Kin LI
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Publication number: 20080237869Abstract: A method of forming an interconnection in a semiconductor device includes forming a first liner in a dielectric layer therein; depositing a tungsten filler on top of the first liner; performing chemical mechanical planarization (CMP) to smooth out and remove the first liner and tungsten filler from the semiconductor's exposed surface; selectively removing the first liner and tungsten filler in the via; wherein the selective removing results in the first liner and the tungsten filler being removed in an upper region of the via; forming a second liner in the upper region of the via and tungsten filler; selectively removing the second liner from the tungsten filler; forming a copper seed layer on top of the tungsten filler; depositing a copper filler on top of the copper seed layer; and performing chemical CMP to smooth out and remove the second liner and copper filler from the semiconductor's exposed surface.Type: ApplicationFiled: March 29, 2007Publication date: October 2, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ying Li, Keith Kwong-Hon Wong
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Publication number: 20080237870Abstract: The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.Type: ApplicationFiled: November 7, 2007Publication date: October 2, 2008Applicant: ROHM CO., LTD.Inventors: Yuichi Nakao, Satoshi Kageyama, Masaru Naitou
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Publication number: 20080237871Abstract: The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (11) and a semi-conductor body (12) which is provided with at least one semiconductor element (E) and comprising a monocrystalline silicon (1) region on top of which an epitaxial silicon region (2) is formed by providing a metal silicide region (3) on the monocrystalline silicon region (1) and a low-crystallinity silicon region (4) on top of the metal silicide region (3), after which the low-crystallinity silicon region (4) is transformed by heating into the epitaxial silicon region (2) having a high-crystallinity, during which process the metal silicide region (3) is moved from the bottom of the low-crystallinity silicon region (4) to the top of the epitaxial silicon region (2).Type: ApplicationFiled: October 27, 2006Publication date: October 2, 2008Applicant: NXP B.V.Inventors: Vijayaraghavan Madakasira, Prabhat Agarwal, Johannes Josephus Theodorus Marinus Donkers, Mark Van Dal
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Publication number: 20080237872Abstract: Disclosed is a semiconductor apparatus having a sealing structure that allows high-precision detection of defects occurring in a protective film, and a method of manufacturing the same. A semiconductor apparatus 1 includes a substrate 10, a semiconductor device 14 formed on the substrate 10, and a protective film 17 for sealing the semiconductor device 14. The semiconductor apparatus 1 further includes a first conductive layer 16 in contact with a back surface of the protective film 17, and a second conductive layer 18 in contact with a front surface of the protective film 17.Type: ApplicationFiled: January 19, 2005Publication date: October 2, 2008Inventor: Kenichi Nagayama
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Publication number: 20080237873Abstract: An integrated circuit package system includes a substrate having an opening provided therein, forming a conductor in the opening in the substrate open at the top and having a closed end at the bottom, attaching an integrated circuit die over the substrate, and connecting a die interconnect to the integrated circuit die and the closed end of the conductor.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Inventors: Il Kwon Shim, Dario S. Filoteo, Emmanuel Espiritu, Rachel Layda Abinan
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Publication number: 20080237874Abstract: A method for manufacturing a material with a low dielectric constant, comprising a step of forming cavities in silicon dioxide by implantation of a rare gas different from helium and from neon at an implantation dose greater than 1016 atoms/cm2.Type: ApplicationFiled: January 27, 2006Publication date: October 2, 2008Inventors: Esidor Ntsoenzok, Hanan Assaf, Marie-Odile Ruault
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Publication number: 20080237875Abstract: A technique of manufacturing a semiconductor device in which etching in formation of a contact hole can be easily controlled is proposed. A semiconductor device includes at least a semiconductor layer formed over an insulating surface; a first insulating layer formed over the semiconductor layer; a gate electrode formed over the first insulating layer; a second insulating layer formed over the gate electrode; and a conductive layer formed over the second insulating layer connected to the semiconductor layer via an opening which is formed at least in the semiconductor layer and the second insulating layer and partially exposes the insulating surface. The conductive layer is electrically connected to the semiconductor layer at the side surface of the opening which is formed in the semiconductor layer.Type: ApplicationFiled: March 12, 2008Publication date: October 2, 2008Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Hideomi SUZAWA, Shinya SASAGAWA, Motomu KURATA
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Publication number: 20080237876Abstract: A method for easily manufacturing a semiconductor device in which variation in thickness or disconnection of a source electrode or a drain electrode is prevented is proposed A semiconductor device includes a semiconductor layer formed over an insulating substrate; a first insulating layer formed over the semiconductor layer; a gate electrode formed over the first insulating layer; a second insulating layer formed over the gate electrode; an opening which reaches the semiconductor layer and is formed at least in the first insulating layer and the second insulating layer; and a step portion formed at a side surface of the second insulating layer in the opening.Type: ApplicationFiled: March 12, 2008Publication date: October 2, 2008Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Shinya SASAGAWA
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Publication number: 20080237877Abstract: This invention is directed to offer a semiconductor device having a structure capable of relaxing a mechanical stress applied to a bonding pad. A third interlayer insulation film having via holes is formed on a second interlayer insulation film to cover a third wiring layer. A third conductive layer is formed in the via hole. The third interlayer insulation film is composed of an array of a plurality of hexagonal column-shaped interlayer insulation films. And the via hole and the third conductive layer are formed to surround each hexagonal column-shaped interlayer insulation film. A fourth wiring layer connected with the third wiring layer through the third conductive layer is formed. The fourth wiring layer makes an uppermost wiring layer in an embodiment of this invention and serves as the bonding pad.Type: ApplicationFiled: April 1, 2008Publication date: October 2, 2008Applicants: SANYO ELECTRIC CO., LTD.Inventors: Shigehiro Morikawa, Yuichi Inaba, Yuji Goto
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Publication number: 20080237878Abstract: A semiconductor device includes a semiconductor substrate having a main surface; an element separation film formed on the main surface in an element separation area and extending in a first direction; and a semiconductor element formed on the main surface in an active area and arranged in a second direction perpendicular to the first direction. The semiconductor element includes a metal silicide film. The metal silicide film includes a first portion adjacent to the element separation film. The semiconductor device further includes an interlayer insulation film formed on the main surface of the semiconductor substrate; a wiring portion formed on the interlayer insulation film; and a conductive plug formed in the interlayer insulation film for electrically connecting the semiconductor elements and the wiring portion. The conductive plug is situated on the element separation film and the metal silicide film.Type: ApplicationFiled: March 14, 2008Publication date: October 2, 2008Inventor: Yoshitaka Satou
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Publication number: 20080237879Abstract: A structure of a semiconductor device package having a substrate with a die receiving through hole, a connecting through hole structure and a contact pad. A die is disposed within the die receiving through hole. A surrounding material is formed under the die and filled in the gap between the die and the sidewall of the die receiving though hole. Dielectric layers are formed on the both side surface of the die and the substrate. Re-distribution layers (RDL) are formed on the dielectric layers and coupled to the contact pads. Protection layers are formed over the RDLs.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Inventor: Wen-Kun Yang
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Publication number: 20080237880Abstract: An integrated circuit package system is provided including providing an integrated circuit die having a contact pad, forming a protection cover over the contact pad, forming a passivation layer having a first opening over the protection cover with the first opening exposing the protection cover, developing a conductive layer over the passivation layer, and forming a pad opening in the protection cover for exposing the contact pad.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Inventors: Yaojian Lin, Haijing Cao, Qing Zhang
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Publication number: 20080237881Abstract: Electronic devices and their formation are described. In one embodiment, a device includes a plurality of stacked semiconductor substrates. The device includes a first semiconductor substrate having a recess extending into a first surface thereof and a via extending from the recess to a second surface opposite the first surface of the first semiconductor substrate. The device also includes a solder positioned in the recess of the first semiconductor substrate. The device also includes an electrically conducting material in the via and electrically coupled to the solder positioned in the recess of the first semiconductor substrate. The device also includes a second semiconductor substrate having bonding pad extending therefrom, the bonding pad electrically coupled to the solder. The device is configured so that at least a portion of the second substrate bonding pad extends a distance into the recess in the first substrate. Other embodiments are described and claimed.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Inventors: Tony DAMBRAUSKAS, Randall L. Lyons
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Publication number: 20080237882Abstract: In some embodiments, annular via drilling (AVD) technology is presented. In this regard, an annular via is introduced comprising an inner wall and an outer wall, the inner wall and the outer wall coupled with a dielectric layer and extending linearly from a surface of a conductor to a top of the dielectric layer. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Inventor: Islam Salama
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Publication number: 20080237883Abstract: First semiconductor element 1 being buried in first insulating material 2; second semiconductor element 5 being covered by second insulating material 6; connection electrode 4 being buried in first insulating material 2 arranged between circuit surface of first semiconductor element 1 and circuit surface of second semiconductor element 5; external connection terminal 8 being arranged on lower surface of first insulating material 2 facing in the same direction as lower surface of first semiconductor element 1 opposite to circuit surface thereof; connection electrode 4 forming a part of path for electrically connecting circuit surface of first semiconductor element 1 and circuit surface of second semiconductor element 5 to each other; first semiconductor element land external connection terminal 8 being being electrically connected to each other by way of wire 3 and via 7 passing through region of insulating layer other than region thereof burying connection electrode 4.Type: ApplicationFiled: March 21, 2008Publication date: October 2, 2008Applicants: NEC CORPORATION, NEC ELECTRONICS CORPORATIONInventors: Masamoto TAGO, Yoichiro KURITA
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Publication number: 20080237884Abstract: A packaging substrate structure is disclosed, which at least comprises a build-up structure including a first dielectric layer, a second dielectric layer and a third dielectric layer. The second dielectric layer is disposed between the first dielectric layer and the third dielectric layer. The characteristic is that the Young's modulus of the second dielectric layer is lower then the first dielectric layer and the third dielectric layer so as to form a sandwich structure of high-low-high of Young's modulus. The packaging substrate structure of the present invention can improve the quality of the product.Type: ApplicationFiled: March 11, 2008Publication date: October 2, 2008Applicant: Phoenix Precision Technology CorporationInventor: Shih-Ping Hsu
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Publication number: 20080237885Abstract: A method of forming photo masks having rectangular patterns and a method for forming a semiconductor structure using the photo masks is provided. The method for forming the photo masks includes determining a minimum spacing and identifying vertical conductive feature patterns having a spacing less than the minimum spacing value. The method further includes determining a first direction to expand and a second direction to shrink, and checking against design rules to see if the design rules are violated for each of the vertical conductive feature patterns identified. If designed rules are not violated, the identified vertical conductive feature pattern is replaced with a revised vertical conductive feature pattern having a rectangular shape. The photo masks are then formed. The semiconductor structure can be formed using the photo masks.Type: ApplicationFiled: June 6, 2008Publication date: October 2, 2008Inventors: Harry Chuang, Kong-Beng Thei, Chih-Tsung Yao, Heng-Kai Liu, Ming-Jer Chiu, Chien-Wen Chen
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Publication number: 20080237886Abstract: Various embodiments of the present invention are directed to three-dimensional crossbar arrays. In one aspect of the present invention, a three-dimensional crossbar array includes a plurality of crossbar arrays, a first demultiplexer, a second demultiplexer, and a third demultiplexer. Each crossbar array includes a first layer of nanowires, a second layer of nanowires overlaying the first layer of nanowires, and a third layer of nanowires overlaying the second layer of nanowires. The first demultiplexer is configured to address nanowires in the first layer of nanowires of each crossbar array, the second demultiplexer is configured to address nanowires in the second layer of nanowires of each crossbar array, and the third demultiplexer is configured to supply a signal to the nanowires in the third layer of nanowires of each crossbar array.Type: ApplicationFiled: March 28, 2007Publication date: October 2, 2008Inventors: Wei Wu, R. Stanley Williams, Warren Robinett, Gregory S. Snider, Zhaoning Yu, Shih-Yuan Wang, Duncan Stewart
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Publication number: 20080237887Abstract: A semiconductor device is disclosed including die bond pads which are heightened to allow wire bonding of offset stacked die even in tight offset configurations. After a first die is affixed to a substrate, one or more layers of an electrical conductor may be provided on some or all of the die bond pads of the first substrate to raise the height of the bond pads. The conductive layers may for example be conductive balls deposited on the die bond pads of the first substrate using a known wire bond capillary. Thereafter, a second die may be added, and wire bonding of the first die may be accomplished using a known wire bond capillary mounting a wire bond ball on a raised surface of a first semiconductor die bond pad.Type: ApplicationFiled: March 29, 2007Publication date: October 2, 2008Inventors: Hem Takiar, Shrikar Bhagath
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Publication number: 20080237888Abstract: A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the chips has a connect plug of a metal formed in a through hole that passes through the semiconductor substrate and the interlayer insulating film. The chip with the connect plug is electrically connected with another chip by that connect plug.Type: ApplicationFiled: October 31, 2007Publication date: October 2, 2008Inventors: Nobuo Hayasaka, Katsuya Okumura, Keiichi Sasaki, Mie Matsuo
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Publication number: 20080237889Abstract: Provided is a semiconductor package, which may include a plurality of semiconductor chips to form a multi-stack semiconductor package (MSP), a method of fabricating the semiconductor package and the MSP, and a semiconductor package mold for fabricating the semiconductor package. The semiconductor package may include a first semiconductor chip package having a first substrate including a first surface having a center portion on which a first semiconductor chip is mounted, and at least one first boundary portion on which a plurality of conductive connection pad groups are formed, and a molding member including a body that covers the first semiconductor chip, and at least one extension that extends from the body towards a corner portion of the first surface of the first substrate, wherein the extension extends while avoiding the conductive connection pad group.Type: ApplicationFiled: April 2, 2008Publication date: October 2, 2008Inventors: Seung-yeol Yang, Sang-wook Park, Seung-jae Lee, Min-young Son
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Publication number: 20080237890Abstract: A wiring board (20A) includes a first wiring portion (10A) having a plurality of wiring layers (1) and external connecting bumps (5), and at least one second wiring portion (15A) having a plurality of contact plugs (14). The second wiring portion is integrated with the first wiring portion such that each terminal (14a) of the second wiring portion is in direct contact with one of the wiring layers of the first wiring portion. Hence, there is no risk to produce an internal stress caused by the diffused component of the solder bump in the junction portion between the second and first wiring portions. Accordingly, even when a semiconductor chip (30) of a low-k material is highly integrated on the wiring board, a highly reliable semiconductor device (50) can be obtained.Type: ApplicationFiled: May 18, 2005Publication date: October 2, 2008Inventor: Masamoto Tago
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Publication number: 20080237891Abstract: A semiconductor device having a stacked arrangement of a substrate and a first chip and a second chip is disclosed. In one embodiment, the first chip is arranged with a lower face on an upper face of the substrate; the second chip with a lower face on an upper face of the first chip, whereby a partial area of the upper face of the first chip that is adjacent to an edge of the first chip is uncovered by the second chip; a fifth wire contact pad is arranged on the uncovered area of the upper face of the first chip; a first bonding wire is arranged that is connected with a first wire contact pad of the substrate and the fifth wire contact pad of the first chip.Type: ApplicationFiled: March 28, 2007Publication date: October 2, 2008Applicant: QIMONDA AGInventors: Roland Irsigler, Steve Wood, Hermann Ruckerbauer, Richard Johannes Luyken, Carsten Niepelt