Patents Issued in October 2, 2008
  • Publication number: 20080237792
    Abstract: The present invention provides a metal-oxide-metal (MOM) capacitor structure having a plurality of symmetrical ring type sections. The MOM capacitor structure of the present invention does not need photomasks above standard CMOS process, and thus the process cost is cheaper. In addition, due to the semiconductor process improvement, a significantly large number of metal layers can be stacked in the MOM capacitor structure, and since the distance between the metal layers becomes smaller, the unit capacitance will be increased.
    Type: Application
    Filed: March 18, 2008
    Publication date: October 2, 2008
    Inventors: Han-Chang Kang, Ta-Hsun Yeh
  • Publication number: 20080237793
    Abstract: A method of forming a semiconductor device, includes forming a lower electrode including a metal and a nitrogen on a semiconductor substrate, irradiating a reducing gas to a surface of the lower electrode, and irradiating a gas containing silicon to the surface of the lower electrode to form a projection containing silicide by reacting the metal with the silicon in an island shape on the surface of the lower electrode. Then, a capacitor film is formed on the lower electrode and the projection, and an upper electrode is formed on the capacitor film.
    Type: Application
    Filed: March 6, 2008
    Publication date: October 2, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Daisuke Oshida, Toshiyuki Takewaki, Takuji Onuma, Koichi Ohto
  • Publication number: 20080237794
    Abstract: Disclosed is a thin film capacitor which can improve the uniformity of the capacitance while keeping a high capacitance. The thin film capacitor has a lower electrode serving as a trench forming layer where a trench pattern is to be formed, a dielectric film so provided as to cover the lower electrode, and an upper electrode laminated in order on the entire top surface of a substrate. The trench pattern is configured to have a first pattern and a second pattern separate from the first pattern. The first pattern has a plurality of protrusions provided upright at predetermined intervals, and the second pattern has a plurality of recesses provided at predetermined intervals. Trenches are each defined by the outer wall of each protrusion and the inner wall of each recess.
    Type: Application
    Filed: March 26, 2008
    Publication date: October 2, 2008
    Applicant: TDK CORPORATION
    Inventor: Shigeru Shoji
  • Publication number: 20080237795
    Abstract: There is provided a semiconductor device which includes a base insulating film formed on a semiconductor substrate, a capacitor formed on the base insulating film, an interlayer insulating film covering the capacitor, a first layer metal wiring formed on the interlayer insulating film, a single-layer first insulating film which covers the interlayer insulating film and the first layer metal wiring and has a first film thickness above the first layer metal wiring, a first capacitor protective insulating film formed on the first insulating film, a first cover insulating film which is formed on the first capacitor protective insulating film and has a second film thickness thicker than the first film thickness, above the first layer metal wiring, a third hole formed in the insulating films on the first layer metal wiring, and a fifth conductive plug formed in the third hole.
    Type: Application
    Filed: June 2, 2008
    Publication date: October 2, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Kouichi NAGAI, Wensheng WANG
  • Publication number: 20080237796
    Abstract: Methods and apparatuses to increase a surface area of a memory cell capacitor are described. An opening in a second insulating layer deposited over a first insulating layer on a substrate is formed. The substrate has a fin. A first insulating layer is deposited over the substrate adjacent to the fin. The opening in the second insulating layer is formed over the fin. A first conducting layer is deposited over the second insulating layer and the fin. A third insulating layer is deposited on the first conducting layer. A second conducting layer is deposited on the third insulating layer. The second conducting layer fills the opening. The second conducting layer is to provide an interconnect to an upper metal layer. Portions of the second conducting layer, third insulating layer, and the first conducting layer are removed from a top surface of the second insulating layer.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Inventors: Brian S. Doyle, Robert S. Chau, Vivek De, Suman Datta, Dinesh Somasekhar
  • Publication number: 20080237797
    Abstract: An electrically tunable resistor and related methods are disclosed. In one embodiment, the resistor includes a first resistive layer, at least one second resistive layer, and an intermediate interdiffused layer of the first resistive layer and the at least one second resistive layer. One method may include providing a first plurality of layers of different materials surrounded by at least one insulating layer, and passing a current pulse through the first plurality of layers to affect a conductivity structure of the first plurality of layers in order to obtain a first predetermined resistance value for the resistor.
    Type: Application
    Filed: March 27, 2007
    Publication date: October 2, 2008
    Inventors: ICKO E.T. IBEN, Alvin W. Strong
  • Publication number: 20080237798
    Abstract: A memory cell and a process for manufacturing the same are provided. In the process, a first electrode layer is formed on a conductive layer over a substrate, and then a transition metal layer is formed on the first electrode layer. After that, the transition metal layer is subjected to a plasma oxidation step to form a transition metal oxide layer as a precursor of a data storage layer, and a second electrode layer is formed on the transition metal oxide layer. A memory cell is formed after the second electrode layer, the transition metal oxide layer and the first electrode layer are patterned into a second electrode, a data storage layer and a first electrode, respectively.
    Type: Application
    Filed: October 4, 2007
    Publication date: October 2, 2008
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ming-Daou Lee, Chia-Hua Ho, Erh-Kun Lai, Kuang-Yeu Hsieh
  • Publication number: 20080237799
    Abstract: A semiconductor device is provided wherein a foundation insulating film is formed over a semiconductor substrate, a metal resistance element is formed on the foundation insulating film, and contacts are formed at both ends of the metal resistance element in a longitudinal direction of the metal resistance element and connected to the metal resistance element. The foundation insulating film comprises a single upwardly concave curved surface constituting not less than about 40 percent of an upper surface of the metal resistance element between the contacts in the longitudinal direction thereof. The curved surface of the foundation insulating film causes the metal resistance element to comprise a single upwardly concave curved surface constituting not less than about 40 percent of upper and lower surfaces of the metal resistance element between the contacts in the longitudinal direction thereof.
    Type: Application
    Filed: March 26, 2008
    Publication date: October 2, 2008
    Applicant: Ricoh Company, Ltd.
    Inventor: Kimihiko Yamashita
  • Publication number: 20080237800
    Abstract: Integrated circuits (IC) and a method of fabricating an IC, where the structure of the IC incorporates a back-end-of-the-line (BEOL) thin film resistor below a first metal layer to achieve lower topography are disclosed. The resistor directly contacts any one of: a contact metal in the front-end-of-the-line (FEOL) structure; first metal layer in the BEOL interconnect; or the combination thereof, to avoid the necessity of forming contacts with differing heights or contacts over varying topography.
    Type: Application
    Filed: March 28, 2007
    Publication date: October 2, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINESS CORPORATION
    Inventors: ANIL K. CHINTHAKINDI, Vincent J. McGahay
  • Publication number: 20080237801
    Abstract: A semiconductor device includes a resistor element formed in a semiconductor layer of an SOI substrate (Silicon On Insulator). The semiconductor device includes a low concentration impurity area formed in the semiconductor layer as the resistor element; a high concentration impurity area formed in the semiconductor layer as a resistor element wiring portion; and a silicide layer selectively formed on the high concentration impurity area. The high concentration impurity area includes one end portion contacting with an end portion of the low concentration impurity area, and the other end portion contacting with an impurity area of another element.
    Type: Application
    Filed: March 13, 2008
    Publication date: October 2, 2008
    Inventors: Hideki Kisara, Masao Okihara
  • Publication number: 20080237802
    Abstract: A method of passivating germanium that comprises providing a germanium material and carburizing the germanium material to form a germanium carbide material. The germanium carbide material may be formed by microwave-plasma enhanced chemical vapor deposition by exposing the germanium material to a microwave generated plasma that is formed from a carbon-containing source gas and hydrogen. The source gas may be a carbon-containing gas selected from the group consisting of ethylene, acetylene, ethanol, a hydrocarbon gas having from one to ten carbon atoms per molecule, and mixtures thereof. The resulting germanium carbide material may be amorphous and hydrogenated. The germanium material may be carburized without forming a distinct boundary at an interface between the germanium material and the germanium carbide material. An intermediate semiconductor device structure and a semiconductor device structure, each of which comprises the germanium carbide material, are also disclosed.
    Type: Application
    Filed: May 13, 2008
    Publication date: October 2, 2008
    Applicant: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn
  • Publication number: 20080237803
    Abstract: A method for forming a semiconductor device is provided including processing a wafer having a spacer layer and a structure layer, the spacer layer is over the structure layer. The method continues including forming a first sidewall spacer from the spacer layer, forming a structure strip from the structure layer below the first sidewall spacer, forming a masking structure over and intersecting the structure strip, and forming a vertical post from the structure strip below the masking structure.
    Type: Application
    Filed: March 26, 2007
    Publication date: October 2, 2008
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Witold P. Maszara, Qi Xiang
  • Publication number: 20080237804
    Abstract: A method for forming a structure is provided and includes implanting an atomic species into a donor substrate having an upper surface at a given depth relative to the upper surface to form an embrittlement zone in the donor substrate, the embrittlement zone defining a removable layer within the donor substrate. The method further includes assembling the upper surface of the donor substrate to a receiver substrate. Additionally, the method includes detaching the removable layer from the donor substrate at the embrittlement zone, thereby forming a detachment surface on the removable layer, by high temperature annealing. The high temperature annealing includes a temperature upgrade phase to a predetermined maximum temperature, maintaining the maximum temperature for a predetermined exposure duration, and a temperature downgrade phase. The maximum temperature and the exposure duration are selected so as to prevent the appearance of significant defects at the detachment surface.
    Type: Application
    Filed: October 16, 2007
    Publication date: October 2, 2008
    Inventors: Konstantin BOURDELLE, Nguyet-Phuong Nguyen, Walter Schwarzenbach
  • Publication number: 20080237805
    Abstract: An object is to provide a semiconductor device which is not easily broken even if stressed externally and a method for manufacturing such a semiconductor device. A semiconductor device includes an element layer including a transistor in which a channel is formed in a semiconductor layer and insulating layers which are formed as an upper layer and a lower layer of the transistor respectively, and a plurality of projecting members provided at intervals of from 2 to 200 ?m on a surface of the element layer. The longitudinal elastic modulus of the material for forming the plurality of projecting members is lower than that of the materials of the insulating layers.
    Type: Application
    Filed: March 19, 2008
    Publication date: October 2, 2008
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hideto Ohnuma
  • Publication number: 20080237806
    Abstract: A three-dimensional semiconductor device is produced by laminating a plurality of semiconductor chips having through-electrodes running through semiconductor substrates, wherein each through-electrode includes an internal electrode, a ring-shaped semiconductor, and an external electrode. The internal electrode is formed using an internal conductive film and includes a plurality of pillar semiconductors, each of which is formed in a rectangular shape or a polygonal shape. The pillar semiconductors are each arranged with a prescribed distance therebetween in connection with the ring-shaped semiconductor. The internal conductive film is embedded in regions between the ring-shaped semiconductor and the pillar semiconductors and between the pillar semiconductors adjoining together. This makes it possible to form trenches having uniform depth, thus realizing a high-speed film growth with respect to the conductive film.
    Type: Application
    Filed: March 25, 2008
    Publication date: October 2, 2008
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Shiro UCHIYAMA
  • Publication number: 20080237807
    Abstract: A second electrode is selectively brought into contact with a semiconductor substrate. Specifically, an insulating film having opening portions is provided on the second principal surface of the semiconductor substrate, and the second electrode is provided on the insulating film. The second electrode comes into contact with the second principal surface of the semiconductor substrate through the opening portions. The total area of the opening portions is approximately the half of the total area of the second principal surface of the semiconductor substrate. Consequently, minority carriers (holes) are prevented by the insulating film from being drawn out, and thus, the loss of the minority carriers around the second electrode is decreased. Accordingly, the conductivity modulation effect is improved. Therefore, the forward voltage can be decreased even with a structure in which the impurity concentration of a p type impurity region is decreased in order to shorten a reverse recover time.
    Type: Application
    Filed: March 26, 2008
    Publication date: October 2, 2008
    Applicants: SANYO ELECTRIC CO., LTD, SANYO SEMICONDUCTOR CO., LTD.
    Inventors: Seiji MIYOSHI, Tetsuya Okada
  • Publication number: 20080237808
    Abstract: Disclosed is a semiconductor device in which emitter pad electrodes connected to an active region, collector and base pad electrodes are formed on a surface of a semiconductor substrate. Furthermore, on a back surface of the semiconductor substrate, a backside electrode is formed. Moreover, the emitter pad electrodes connected to a grounding potential are connected to the backside electrode through feedthrough electrodes penetrating the semiconductor substrate in a thickness direction.
    Type: Application
    Filed: June 6, 2008
    Publication date: October 2, 2008
    Applicants: Sanyo Electric Co., Ltd., Kanto Semiconductors Co., Ltd.
    Inventors: Hirotoshi Kubo, Yukari Shirahata, Shigehito Matsumoto, Masamichi Yamamuro, Koujiro Kameyama, Mitsuo Umemoto
  • Publication number: 20080237809
    Abstract: A method of fabricating a hybrid orientation substrate is described. A silicon substrate with a first orientation having a silicon layer with a second orientation directly thereon is provided, and then a stress layer is formed on the silicon layer. A trench is formed between a first portion and a second portion of the silicon layer through the stress layer and into the substrate. The first portion of the silicon layer is amorphized. A SPE process is performed to recrystallize the amorphized first portion of the silicon layer to be a recrystallized layer with the first orientation. An annealing process is performed at a temperature lower than 1200° C. to convert a surface layer of the second portion of the silicon layer to a strained layer. The trench is filled with an insulating material after the SPE process or the annealing process, and the stress layer is removed.
    Type: Application
    Filed: March 29, 2007
    Publication date: October 2, 2008
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yao-Tsung Huang, Chien-Ting Lin, Che-Hua Hsu, Guang-Hwa Ma
  • Publication number: 20080237810
    Abstract: Methods and apparatus to control surface properties via colloidal coatings are described. In one embodiment, colloidal coating may be used on a surface to enhance flow control. Other embodiments are also described.
    Type: Application
    Filed: March 29, 2007
    Publication date: October 2, 2008
    Inventors: Gopalakrishnan Subramanian, Nirupama Chakrapani, Larry DeCesare, Shripad Gokhale, Jason Murphy, Jinlin Wang
  • Publication number: 20080237811
    Abstract: A method for capturing process history includes performing at least a first process for forming features on a semiconducting substrate. A first cap is formed over a first region of the semiconducting substrate after performing the first process. At least a second process is performed for forming the features in a second region other than the first region while leaving the first cap in place to thereby prevent the features in the first region covered by the first cap from being exposed to the second process. A first characteristic of a first feature is measured in the first region, and a second characteristic of a second feature in the second region is measured. A wafer includes a first partially completed feature disposed in a first region. A first cap is formed above the first partially completed feature. A second partially completed feature is disposed in a second region of the wafer different than the first region.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Inventors: Rohit Pal, David F. Brown
  • Publication number: 20080237812
    Abstract: A method of manufacturing a semiconductor device includes the steps of forming a trench on a semiconductor substrate to define a first and a second element regions; burying a first oxide film in the trench; forming a second oxide film on surfaces of the first and second element regions; performing a first ion doping using a first mask which is exposing a first region containing the first element region and a part of the first oxide; performing a second ion doping using a second mask which is exposing a second region containing the second element region and a part of the first oxide film; and removing the second oxide film formed in the first element region and the second element region by etching, and the first oxide film is selectively thinned using the first or second mask after performing the first or second ion doping.
    Type: Application
    Filed: March 21, 2008
    Publication date: October 2, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Masanori TERAHARA, Masaki NAKAGAWA
  • Publication number: 20080237813
    Abstract: A printed circuit board includes a source interconnect and a ground interconnect, and the circuit board has a two-dimensional geometry having a corner. Protruding portions are provided in circumferences of the source interconnect and the ground interconnect in regions except the corner in plan view, and the source interconnect and the ground interconnect are connected to a common first decoupling capacitor in each of the protruding portions.
    Type: Application
    Filed: March 17, 2008
    Publication date: October 2, 2008
    Inventor: Shoichi Chikamichi
  • Publication number: 20080237814
    Abstract: An integrated circuit package is described that includes a die and a lead frame that includes recessed regions for preventing the undesired spread of solder during reflow. The die includes a plurality of solder bumps formed on its active surface. The lead frame includes a plurality of leads, each having an associated solder pad. Each solder pad is suitably positioned adjacent and electrically contacting an associated solder bump on the die. Each lead also includes a recessed region in a region adjacent to the solder pad. The recessed region serves to isolate the surface of the solder pad from the other surfaces of the lead. In this manner, the solder of the solder bump that contacts the lead is confined to the surface of the associated solder pad.
    Type: Application
    Filed: March 26, 2007
    Publication date: October 2, 2008
    Inventor: Jaime A. Bayan
  • Publication number: 20080237815
    Abstract: A tape carrier includes: a base film with insulating property; a wiring pattern provided on the base film within a product region, the product region being demarcated by a cutting line so as to divide the tape carrier into individual products by cutting along the tape carrier along the cut line; and a solder resist provided on the base film so as to cover the wiring pattern. The solder resist protrudes outward from within the product region.
    Type: Application
    Filed: March 21, 2008
    Publication date: October 2, 2008
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Masahiko YANAGISAWA
  • Publication number: 20080237816
    Abstract: An integrated circuit package system is provided including forming a lead frame includes forming a mold gate, providing a first surface, and providing a second surface opposite the first surface; and forming angled gate sides facing each other in the mold gate between the first surface and the second surface.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Inventors: Henry Descalzo Bathan, Jeffrey D. Punzalan, Abelardo Hadap Advincula, Jose Alvin Caparas
  • Publication number: 20080237817
    Abstract: An integrated circuit package system comprising: providing a package substrate; attaching an integrated circuit die over the package substrate wherein the integrated circuit die has a mount height; attaching an attachment structure having a height substantially the same as the mount height and planar dimensions predetermined to fit adjacent the integrated circuit die and over the package substrate; and attaching a heat dissipation device over the integrated circuit die and the attachment structure.
    Type: Application
    Filed: March 18, 2008
    Publication date: October 2, 2008
    Inventor: Rajendra D. Pendse
  • Publication number: 20080237818
    Abstract: Methods and apparatus for providing an integrated circuit using a multi-stage molding process to protect wirebonds. In one embodiment, a method includes attaching a die to a leadframe having a lead finger, attaching a wirebond between the die and the leadfinger, applying a first mold material over at least a portion of the wirebond and the die and the leadfinger to form an assembly, waiting for the first mold material to at least partially cure, and applying a second mold material over the assembly.
    Type: Application
    Filed: March 29, 2007
    Publication date: October 2, 2008
    Inventors: Raymond W. Engel, Nirmal Sharma, William P. Taylor
  • Publication number: 20080237819
    Abstract: The present invention relates to a bipolar carrier wafer and a mobile, bipolar electrostatic wafer arrangement. Carrier wafers and wafer arrangements of this type can be used in particular in the field of handling technology of semiconductor wafers. The carrier wafer according to the invention serves for mounting a disc-shaped semiconductor component. It has a first surface (2a) as front-side and a second surface (2b) which is situated opposite the first surface (2a) as rear-side. The carrier wafer is configured such that it has a carrier layer (2), an electrically insulating cover layer (3) which surrounds the carrier layer and an electrically conductive layer (4), the latter being disposed on the electrically insulating cover layer and being structured in at least two regions which are separated from each other electrically as electrodes.
    Type: Application
    Filed: November 15, 2006
    Publication date: October 2, 2008
    Inventors: Robert Wieland, Dieter Bollmann
  • Publication number: 20080237820
    Abstract: A package structure including a substrate, a shielding element, a chip, a sealant layer and a semiconductor device is provided. The substrate has a first surface and a second surface opposite to the first surface. The shielding element is disposed on the first surface. The chip is disposed on the shielding element and is electrically connected to the substrate. The sealant layer is disposed on the first surface, and encapsulates the chip and the shielding element. The semiconductor device is disposed on the second surface.
    Type: Application
    Filed: March 28, 2007
    Publication date: October 2, 2008
    Inventors: Hyeongno Kim, Soo-Min Choi, Jae-Sun An, Young-Gue Lee, Sang-Jin Cha
  • Publication number: 20080237821
    Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a substrate, a shielding plate, a first chip, a first sealant, a second chip and a second sealant. The substrate has a lower surface and an upper surface on which the shielding plate is disposed. The first chip disposed on the shielding plate is electrically connected to the substrate. The first sealant disposed on the upper surface encapsulates the shielding plate and the first chip. The second chip disposed on the lower surface is electrically connected to the substrate. The second sealant disposed on the lower surface encapsulates the second chip.
    Type: Application
    Filed: March 28, 2007
    Publication date: October 2, 2008
    Inventors: Hyeongno Kim, Soo-Min Choi, Jae-Sun An, Young-Gue Lee, Sang-Jin Cha
  • Publication number: 20080237822
    Abstract: A microelectronic die and a package including the die. The die comprises a die substrate including a base and a die passivation layer disposed on the base. The die passivation layer includes a nanocomposite including a matrix and nanoparticles dispersed within the matrix.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Inventors: Nachiket R. Raravikar, Sumant Padiyar, Neha Patel
  • Publication number: 20080237823
    Abstract: Aluminum or aluminum alloy on each of a pair of semiconductor wafers is thermocompression bonded. Aluminum-based seal rings or electrical interconnects between layers may be thus formed. On a MEMS device, the aluminum-based seal ring surrounds an area occupied by a movably attached microelectromechanical structure. According to a manufacturing method, wafers have an aluminum or aluminum alloy deposited thereon are etched to form an array of aluminum-based rings. The wafers are placed so as to bring the arrays of aluminum-based rings into alignment. Heat and compression bonds the rings. The wafers are singulated to separate out the individual semiconductor devices each with a bonded aluminum-based ring.
    Type: Application
    Filed: January 11, 2008
    Publication date: October 2, 2008
    Applicant: ANALOG DEVICES, INC.
    Inventor: John R. Martin
  • Publication number: 20080237824
    Abstract: A method of fabricating a stacked electronic component package includes placing a single-sided film spacer on an upper surface of a lower electronic component inward of bond pad with a pickup tool. After being adhered to the upper surface of the lower electronic component, the pickup tool is retracted from the single-sided film spacer. An upper surface of a film, e.g., an organic film, of the single-sided film spacer is nonadhesive. Accordingly, the single-sided film spacer does not stick to the pickup tool during retraction of the pickup tool from the single-sided film spacer.
    Type: Application
    Filed: February 17, 2006
    Publication date: October 2, 2008
    Inventors: Roger D. St. Amand, ChangSuk Han, YounSang Kim, KyungRok Park
  • Publication number: 20080237825
    Abstract: A stacked integrated circuit package system is provided including providing a first device and a second device with the first device, the second device, or a combination thereof having an integrated circuit die; forming a conductive spacer structure over the first device with the conductive spacer structure having a spacer filler around a conductive element; mounting the second device over the conductive spacer structure and the first device; and encapsulating the first device, the second device, and the conductive spacer structure.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Inventors: Lionel Chien Hui Tay, Rui Huang, Seng Guan Chow
  • Publication number: 20080237826
    Abstract: A method of protecting a micro-mechanical sensor structure embedded in a micro-mechanical sensor chip, in which the micro-mechanical sensor structure is fabricated with a protective membrane, the micro-mechanical sensor chip is arranged so that a surface of the protective membrane faces toward a second chip, and the micro-mechanical sensor chip is secured to the second chip.
    Type: Application
    Filed: September 21, 2007
    Publication date: October 2, 2008
    Inventor: Karsten Funk
  • Publication number: 20080237827
    Abstract: A microelectronic device including a microelectronic circuit and at least one planar flexible lead. These planar flexible leads are adapted to bend and flex during mechanical stress allow direct mounting of the device to a member, and withstand extreme thermal cycling, such as ?197° C. to +150° C. such as encountered in space.
    Type: Application
    Filed: March 27, 2007
    Publication date: October 2, 2008
    Inventor: Tracy Autry
  • Publication number: 20080237828
    Abstract: The present invention discloses a structure of package comprising a substrate with at least one die receiving through holes, a conductive connecting through holes structure and a contact pads on both side of substrate. At least one die is disposed within the die receiving through holes. A first material is formed under the die and second material is formed filled in the gap between the die and sidewall of the die receiving though holes. Dielectric layers are formed on the surface of both side of the die and the substrate. Redistribution layers (RDL) are formed on the both sides and coupled to the contact pads. A protection bases are formed over the RDLs.
    Type: Application
    Filed: November 7, 2007
    Publication date: October 2, 2008
    Applicant: ADVANCED CHIP ENGINEERING TECHNOLOGY INC.
    Inventor: Wen-Kun YANG
  • Publication number: 20080237829
    Abstract: A semiconductor package that includes a lead frame riveted to pillars electrically connect to an electrode of a semiconductor die.
    Type: Application
    Filed: December 7, 2007
    Publication date: October 2, 2008
    Inventors: Chuan Cheah, Kunzhong Hu
  • Publication number: 20080237830
    Abstract: There is provided a semiconductor device whose cost is low and whose case is restrained from breaking. In the semiconductor device having a semiconductor sensor chip, a signal processing circuit for processing signals output from the semiconductor sensor chip and a hollow case for mounting the semiconductor sensor chip and the signal processing circuit therein, the case is constructed by bonding a concave bottom member whose one end is opened with a plate-like lid member that covers the opening of the bottom member. Then, the bottom and lid members are both made of a semiconductor material and are bonded by means of anode bonding or metal bonding for example.
    Type: Application
    Filed: March 7, 2008
    Publication date: October 2, 2008
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventors: Yoshihiko Ino, Takeharu Suzuki
  • Publication number: 20080237831
    Abstract: A multi-chip semiconductor package structure is disclosed according to the present invention, the package structure includes: a carrier board having a first surface, a second surface, and at least an opening penetrating the first and second surfaces, the first and second surfaces each having electrically connecting pads; a semiconductor component received in the opening, the semiconductor component has a first active surface and a second active surface, and each of the first and second active surfaces has a plurality of electrode pads; a plurality of first conductive elements electrically connected to the electrically connecting pads of the first and second surfaces of the carrier board with the electrode pads of the first and second active surfaces of the semiconductor component; and a molding material formed on a portion of the first surface of the carrier board, the first active surface of the semiconductor component, a portion of the second surface of the carrier board, and the second active surface of th
    Type: Application
    Filed: January 17, 2008
    Publication date: October 2, 2008
    Applicant: Phoenix Precision Technology Corporation
    Inventors: Shih-Ping Hsu, Chung-Cheng Lien, Chia-Wei Chang
  • Publication number: 20080237832
    Abstract: A multi-chip semiconductor package structure is disclosed, including a carrier board having a first and an opposing second surfaces and formed with at least an opening penetrating the first and second surfaces, wherein a plurality of electrically connecting pads are formed on the first and second surfaces of the carrier board, respectively; a semiconductor component disposed in the opening, the semiconductor component having a first and a second active surfaces each with a plurality of electrode pads being formed thereon; a third semiconductor chip having an active surface and an inactive surface, the active surface having a plurality of electrode pads formed thereon for electrically connecting with the electrically connecting pads on the first surface of the carrier board and the electrode pads on the first active surface of the semiconductor component; and a fourth semiconductor chip having an active surface and an inactive surface, the active surface having a plurality of electrode pads formed thereon for
    Type: Application
    Filed: March 13, 2008
    Publication date: October 2, 2008
    Applicant: PHOENIX PRECISION TECHNOLOGY CORPORATION
    Inventors: Shih-Ping Hsu, Chung-Cheng Lien, Chia-Wei Chang
  • Publication number: 20080237833
    Abstract: A multi-chip semiconductor package structure is disclosed according to the present invention.
    Type: Application
    Filed: March 13, 2008
    Publication date: October 2, 2008
    Applicant: PHOENIX PRECISION TECHNOLOGY CORPORATION
    Inventors: Shih-Ping Hsu, Chung-Cheng Lien, Chia-Wei Chang
  • Publication number: 20080237834
    Abstract: A chip packaging structure comprising a chip, a plurality of conductive pillars surrounding the chip, an encapsulation encapsulating the chip and the conductive pillars, and a connecting layer is provided. The encapsulation has a first side and a second side corresponding to the first side. The connecting layer is disposed at the first side of the encapsulation and electrically connected between the chip and the conductive pillars. Furthermore, a chip packaging process accompanying the chip packaging structure is also provided. The chip packaging structure is more useful and powerful and is suitable for various chip packaging applications, and the chip packaging process can reduce the manufacturing time and save the production cost.
    Type: Application
    Filed: March 29, 2007
    Publication date: October 2, 2008
    Applicant: ADVANCED CHIP ENGINEERING TECHNOLOGY INC.
    Inventors: Dyi-Chung Hu, Yu-Shan Hu, Chih-Wei Lin
  • Publication number: 20080237835
    Abstract: A transistor outline package having a feedthrough via and lead configuration that maximizes the amount of usable area on a header of the package is disclosed. In one embodiment, the package includes a header having an interior surface that includes a first and second lead assembly. The first lead assembly includes two vias having a first diameter, with each first via being positioned along a first pin circle imaginarily defined on the interior surface of the header. Each first via also includes first leads received therein. The second lead assembly includes four vias having a second diameter each, with each second via being positioned along a second pin circle that has a diameter greater than that of the first pin circle. Each second via includes second leads received therein. This configuration increases usable area on the header interior surface between the leads, enabling relatively larger submounts to be placed thereon.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Applicant: Finisar Corporation
    Inventors: Chris Kiyoshi Togami, Darin J. Douma
  • Publication number: 20080237836
    Abstract: A semiconductor chip embedding structure is disclosed, including a carrier board having a first and an opposed second surfaces and formed with at least a through hole; a semiconductor chip received in the through hole, the chip having an active surface and an inactive surface opposite to one another, wherein the active surface has a plurality of electrode pads, a passivation layer is formed on the active surface with the electrode pads exposed from the passivation layer, and metal pads are formed on surfaces of the electrode pads; a buffer layer formed on the first surface of the carrier board and on surfaces of the passivation layer and the metal pads; a first dielectric layer formed on the buffer layer; and a first circuit layer formed on the first dielectric layer and electrically connected with the metal pads of the chip via first conductive structures formed in the buffer layer and the first dielectric layer, wherein the CTE (Coefficient of Thermal Expansion) of the buffer layer is between the CTE of the
    Type: Application
    Filed: March 26, 2008
    Publication date: October 2, 2008
    Applicant: PHOENIX PRECISION TECHNOLOGY CORPORATION
    Inventors: Kan-Jung Chia, Shang-Wei Chen
  • Publication number: 20080237837
    Abstract: An integrated circuit arrangement including a nonplanar substrate on which an integrated circuit is formed on at least one side, wherein the side of the substrate a which has the integrated circuit is arranged on a carrier and the carrier is produced from a chemically resistant material.
    Type: Application
    Filed: February 14, 2005
    Publication date: October 2, 2008
    Inventors: Jurgen Fischer, Manfred Mengel, Frank Puschner
  • Publication number: 20080237838
    Abstract: The semiconductor device includes a plurality of semiconductor chips, and a circuit substrate having a substantially rectangular outer shape. The semiconductor device is an MCM having an MCM packaging structure in which the plurality of semiconductor chips are juxtaposed on the semiconductor chip mounting surface of the circuit substrate, and the semiconductor chip mounting surface is covered by a sealing resin along an outer edge of the circuit substrate so that the plurality of semiconductor chips are sealed.
    Type: Application
    Filed: March 18, 2008
    Publication date: October 2, 2008
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Kazuo Tamaki
  • Publication number: 20080237839
    Abstract: A semiconductor apparatus and a method of manufacturing same can simplify the manufacturing process and prevent a decrease in production yield without decreasing in sensor sensitivity.
    Type: Application
    Filed: March 14, 2008
    Publication date: October 2, 2008
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventor: Yoshihiko Ino
  • Publication number: 20080237840
    Abstract: A flexible circuit electronic package including a heat sink, a flexible circuit having a semiconductor chip positioned thereon and electrically coupled thereto, and a quantity of heat shrunk adhesive securing the flexible circuit to the heat sink such that the flexible circuit is planar. This package is then adapted for being positioned on and electrically coupled to a circuitized substrate such as a printed circuit board. A method of making this package is also provided.
    Type: Application
    Filed: March 26, 2007
    Publication date: October 2, 2008
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: David J. Alcoe, Varaprasad V. Calmidi
  • Publication number: 20080237841
    Abstract: A microelectronic package includes a substrate (110) having a first die (120) and a second die (130) located thereon, a first thermal interface material (121) located over the first die, and a second thermal interface material (131) located over the second die. The first thermal interface material has a first set of characteristics, the second thermal interface material has a second set of characteristics, and the first set of characteristics is not identical to the second set of characteristics.
    Type: Application
    Filed: March 27, 2007
    Publication date: October 2, 2008
    Inventors: Leonel R. Arana, Vijay S. Wakharkar, James C. Matayabas, Paul A. Koning, Cynthia K. Koning