Abstract: A surface emitting laser element includes an active layer and a dielectric multilayer mirror formed with a plurality of dielectric layers having different refractive indices for reflecting a light generated in the active layer. At least one of boundaries between the dielectric layers is formed to have a predetermined surface roughness to obtain a desired target reflectance of the dielectric multilayer mirror.

Abstract: The two-dimensional photonic crystal surface emitting laser according to the present invention includes a semiconductor substrate, a main laser section and a reflection film. The main laser section includes a lower cladding layer, an active layer, a two-dimensional photonic crystal layer, an upper cladding layer and a contact layer, which are all deposited on the semiconductor substrate. The reflection film, which surrounds the entire side surfaces of the main laser section, is made of a thin titanium-gold film deposited by sputtering.

Abstract: A VSCEL capable of being easily and inexpensively manufactured and of stabilizing the polarization direction of laser light in one direction is provided. The Vertical Cavity Surface Emitting Laser includes a semiconductor lamination structure including a first multilayer film reflector, an active layer having a light emitting region, and a second multilayer film reflector in this order over a substrate from the substrate side. The semiconductor lamination structure has a pair of grooves provided with a region opposed to the light emitting region in between, and one or a plurality of first oxidation layers including a first non-oxidation region provided at least in a region opposed to the light emitting region and a first oxidation region provided on each side face of the pair of grooves.

Abstract: In a semiconductor optical device, the first conductive type semiconductor region includes a first semiconductor portion and a second semiconductor portion. The first and second regions of the first semiconductor portion are arranged along a predetermined plane. The second semiconductor portion is provided on the first region of the first semiconductor portion. The active layer is provided on the second semiconductor portion of the first conductive type semiconductor region. The second conductive type semiconductor region is provided on the second region of the first semiconductor portion of the first conductive type semiconductor region. The side of the second semiconductor portion of the first conductive type semiconductor region, the top and side of the active layer, the second region of the first conductive type semiconductor region and the second conductive type semiconductor region constitute a pn junction.

Abstract: A surface emitting laser includes the plurality of surface emitting lasers including a first surface emitting laser, a second surface emitting laser adjacent to the first surface emitting laser, and a third surface emitting laser adjacent to the second surface emitting laser. Each of the plurality of surface emitting lasers is operated by an independent signal with respect to one another and includes a first mirror, an active layer, a second mirror, and a columnar portion composed of at least the first mirror and the active layer. A diameter of the columnar portion of the second surface emitting laser is smaller than a diameter of the columnar portion of the first surface emitting laser, and larger than a diameter of the columnar portion of the third surface emitting laser.

Abstract: Systems and methods for efficiently operating a gas discharge excimer laser are disclosed. The excimer laser may include a chamber containing laser gases, first and second electrodes within the chamber, and a plurality of reflective elements defining an optical resonant cavity. The method may include setting the laser gases to a first pressure; after setting the gases to the first pressure, applying a first voltage to the electrodes, thereby propagating a laser beam in the optical resonant cavity; measuring energy of the beam; adjusting the first voltage until the energy of the beam is substantially equal to a target pulse energy; operating the laser for an amount of time; after the amount of time, measuring energy of the beam; and changing the pressure of the gases to a second pressure different from the first pressure.

Abstract: A semiconductor laser of the present invention is constructed such that the reflectance of the front facet coating film or the rear facet coating film dramatically decreases at wavelengths greater than a predetermined wavelength. This causes the loss of the semiconductor laser to dramatically increase at wavelengths greater than the predetermined wavelength. As a result, the oscillation wavelength of the semiconductor laser at high temperatures is clamped to around the predetermined wavelength.

Abstract: The invention relates to a target illuminator (1) for night-vision technology, comprising a laser source (2), the radiation power of the laser source being at least 15 mW, in particular from 100 to 500 mW, and the laser source being formed for emission of radiation having a wavelength ? of from 700 nm to 1400 nm, and a second optical system (4) for the divergent emission of the radiation. Furthermore, the target illuminator (1) has a first optical system (3) arranged down-circuit of the laser source (2) and before the second optical system (4) and intended for increasing the beam cross-section before entry into the second optical system (4) to a diameter of at least 5 mm and for guiding the beam into the second optical system (4). The angle of divergence (10) of the emitted radiation can be varied in a defined manner, the variability being limited for ensuring a minimum divergence.

Abstract: On the fulfillment of a specified condition, a temperature signal outside an actuating device is detected to which a piezoelectric actuator is assigned. A piezoelectric temperature value is determined by the temperature signal. A temperature-capacitance characteristic value of the piezoelectric actuator is determined by the piezoelectric temperature value through specified mapping. A measured capacitance characteristic value is determined by a detected piezoelectric actuator charge and voltage corresponding to the temperature signal. A first correction capacitance characteristic value is determined by the measured capacitance characteristic value and the temperature-capacitance characteristic value. Independently, the charge and the voltage of the piezoelectric actuator is detected and the measured capacitance characteristic value is determined on the basis of these.

Abstract: A method for evaluating a solder joint portion by means of which a part and a substrate are joined to each other includes a preparation process for preparing the substrate including the solder joint portion, a thermal shock process for applying thermal shock to the solder joint portion multiple times, and an evaluation process for obtaining a change of a crystal grain size in the solder joint portion caused by the application of the thermal shock so as to evaluate a lifespan of the solder joint portion based on the change of the crystal grain size obtained.

Abstract: A micromechanical device includes a micromechanical functional structure and an electromagnetic radiation heating associated with the micromechanical functional structure, which is formed to cause a spatially and temporally defined temperature or a spatially and temporally defined temperature course in the micromechanical functional structure.

Abstract: A fast accurate multi-channel frequency dependent scheme for analyzing noise in a signal processing system is described herein. Noise is decomposed within each channel into frequency bands and sub-band noise is propagated. To avoid the computational complexity of a convolution, traditional methods either assume the noise to be white, at any point in the signal processing pipeline, or they just ignore spatial operations. By assuming the noise to be white within each frequency band, it is possible to propagate any type of noise (white, colored, Gaussian, non-Gaussian and others) across a spatial transformation in a very fast and accurate manner. To demonstrate the efficacy of this technique, noise propagation is considered across various spatial operations in an image processing pipeline. Furthermore, the computational complexity is a very small fraction of the computational cost of propagating an image through a signal processing system.

Abstract: The present invention is directed to a system and method for channel estimation for a communication channel such as, for example, that found in a wireless communication network. One or more synchronization and channel estimate symbols can be combined to compute a refined channel estimate.

Abstract: A wireless device including a first radio communication portion configured to effect radio communication with a first external communication device while using frequency bands selected one after another from among a group of frequency bands, a field intensity measuring portion which is configured to measure a field intensity value for each of a plurality of frequency bands belonging to at least the group of frequency bands and which is provided in a portion different from the first radio communication portion, and an excluding portion configured to exclude each of the above-indicated plurality of frequency bands for which the measured field intensity value is higher than a predetermined threshold value, from the above-indicated group of frequency bands.

Abstract: There is provided a communication apparatus compliant with ultra wide band communication systems for improving resistance to interfering waves in combination with DS-SS (direct sequence spread spectrum). There is provided a training section based on short code spread with the same pattern repeated for each symbol length. Actual communication itself is preceded by coherent channel measurement of a transmission channel by using the training section to specify a length of the short code to be a measurement period and using N cycles of a carrier as a time resolution for measurement. A chip timing is controlled at the time resolution for measurement. At all points given by a time resolution for a measurement period, a measured value is obtained by using the short code to despread A/D-converted values from an input signal based on the chip timing.

Abstract: A plurality of signals are received in a shared spectrum. Samples of the received user signals are produced as a received vector. The received vector is segmented into a plurality of segments. For each segment, successively determining symbols for each user or group of signals (the group of signals having similar received power) by determining symbols for one user/group and removing a contribution of that one user/group from the received vector. The determined symbols corresponding to each segment are assembled into a data vector.

Abstract: Apparatus, system, and method for an adaptive transmission selection technique. A retransmission scheme is selected for a multiple-input-multiple-output (MIMO) wireless communications system. Techniques are provided herein for selecting from a plurality of wireless communication techniques when a first device needs to retransmit a signal (one or more packets of data) to a second device. The first device determines when the signal which was originally wirelessly transmitted using beamforming techniques via multiple antennas of the first device to the second device needs to be retransmitted to the second device. If a retransmission is needed, the first device determines channel conditions with respect to the second device. The first device selects a retransmission scheme from a plurality of transmission schemes based on the channel conditions for retransmitting the signal via the multiple antennas of the first device to the second device.

Abstract: A communications system including: a plurality of sub-surface portable transceivers each including: a digital data source, a modulator coupled to the digital data source, a power amplifier coupled to the modulator and a loop antenna inductively coupled to the power amplifier; and a base transceiver including: an electrically insulated ferrite core antenna for receiving magnetic signals, an electric di-pole antenna for receiving ambient noise, a noise canceller coupled to the insulated ferrite core antenna and electric dipole antenna and responsive to the electric-dipole antenna to filter noise from signals received via the insulated ferrite core antenna, a demodulator coupled to the noise canceller and a decoder coupled to the demodulator.

Abstract: An integrated circuit radio transceiver and method therefor includes a high-pass variable gain amplifier (HPVGA) operably disposed within one of the transmitter and the receiver front ends operable to provide a linear variable gain and a substantially constant high-pass frequency corner that does not vary with changes in gain level settings. The HPVGA includes an amplifier operably disposed to receive an input signal and to produce an amplified output based upon the input signal, an adjustable resistance block operable to adjust resistance based upon a gain control input and corner drift compensation block operably disposed to provide corner frequency compensation at the input terminal of the amplifier that is further coupled to receive the input signal from the adjustable resistance block.

Abstract: In one implementation, a method includes receiving control information in a transceiver from a baseband processor and computing ramp values in the transceiver based on the control information. The ramp values may be computed in a signal generator of the transceiver such as an algorithmic generator. Depending on mode of operation, the ramp values may be provided to a power amplifier or a gain block of the transceiver.

Abstract: A transmitter/receiver device includes: a transmitter unit including a parallel/serial converting circuit, a waveform deteriorating circuit, and a transmitter circuit; and a receiver unit including a receiver circuit, a serial/parallel converting circuit, and an error detecting circuit. The parallel/serial converting circuit converts a transmitter-side parallel signal to a transmitter-side serial signal. The waveform deteriorating circuit deteriorates a signal waveform of the transmitter-side serial signal. The transmitter circuit transmits to the receiver unit the signal whose waveform is deteriorated. The receiver circuit receives, as a receiver-side serial signal, the signal transmitted from the transmitter circuit. The serial/parallel converting circuit converts the receiver-side serial signal to a receiver-side parallel signal. The error detecting circuit detects a bit error rate of the receiver-side parallel signal.

Abstract: The present invention relates to a home system, and more particularly to a home network system that is able to reduce of electric device by application of a modem that is capable of independently processing data. The present invention comprises a first electric device to transmit data including a home code input by the outside to a second electric device through a predetermined network; and a second electric device that comprises a modem by which it is connected to the first electric device through the network, and makes the modem to receive the data, after the initialization of the modem is finished, and read the home code from the data and establish it as its own home code.

Abstract: Systems and methods for orthogonal frequency division multiplexing are provided. In one embodiment, a multi-carrier modem comprises: a receiver configured to receive a waveform comprising a plurality of spectrally overlapping carrier signals from at least two of a plurality of remote units, wherein the plurality of spectrally overlapping carrier signals are modulated using an inverse Fourier transform algorithm; a transmitter; a processor coupled to the transmitter, wherein the processor outputs data for transmission to the transmitter, wherein the processor applies an inverse Fourier transform algorithm to the data provided to the transmitter; a controller programmed to instruct the transmitter to transmit a predetermined identifier on at least one of the spectrally overlapping carrier signals, the predetermined identifier identifying to a first remote unit a range of the plurality of spectrally overlapping carrier signals for the first remote unit to receive control information.

Abstract: There is provided a response probability calculating method for use in a communication system in which a response probability is sent from a communication network to a plurality of terminals, and the terminals report terminal information to the communication network according to the response probability, including a step of selecting a first calculation formula for monotonously increasing the response probability or a second calculation formula for calculating the response probability using the response probability sent at the previous time and the previous number of responses in accordance with the number of responses from the terminals, and a step of calculating the response probability in accordance with the selected calculation formula.

Abstract: A method, where data is transmitted from a network node to user equipment in a succession of communication frames. An estimate indicative of the quality of the user equipment transmission channel in a reference communication frame is ascertained, and modified by an amount that varies in dependence on a configuration of the resources allocated to the user equipment in the reference communication frame. The modified estimate is used in selecting one or more connection parameters for a data transmission in a target communication frame.

Abstract: A device and method for estimating a carrier to interference-plus-noise ratio (CINR) in an OFDM system are provided. The CINR estimating method includes (a) receiving a preamble symbol and transmit subcarrier transmitted from a base station; (b) calculating an interference power and noise power using the preamble symbol and transmit subcarrier; (c) calculating a receive power used for the base station to transmit a preamble and data symbol; (d) estimating a preamble CINR value using an interference power, a noise power, and a receive power; (e) calculating the noise power from a subcarrier not transmitting a preamble; and (f) calculating an average CINR of data subcarriers using the preamble CINR value and the noise power.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for an automatic calibration circuit for a continuous-time equalizer (CTE). In some embodiments, the calibration circuit separately locks the direct (DC) voltage swing and the alternating (AC) voltage swing of a CTE to reference voltage.

Abstract: Described are methods and circuits for margin testing receivers equipped with Decision Feedback Equalization (DFE) or other forms of feedback that employ historical data to reduce intersymbol interference (ISI). In one example, a high-speed serial receiver with DFE injects the correct received data (i.e., the “expected data”) into the feedback path irrespective of whether the receiver produces the correct output data. The margins are therefore maintained in the presence of receiver errors, allowing in-system margin tests to probe the margin boundaries without collapsing the margin limits. Some receivers include local expected-data sources that either store or generate expected data for margin tests. Other embodiments derive the expected data from test data applied to the receiver input terminals.

Abstract: Digital filter, comprising a multiplier configured to generate an intermediate signal, wherein said intermediate signal is generated by multiplying an input signal with a filter coefficient signal, wherein said multiplier is operated at a clock rate and said input signal has a sampling rate, wherein said clock rate is higher than said sampling rate; a first buffer configured to supply said filter coefficient signal to said multiplier at said clock rate, wherein said filter coefficient signal represents N filter coefficients in a periodic order, wherein N denotes the order of said digital filter; a second buffer configured to buffer N/2 samples of an intermediate output signal and to generate a respective time delayed intermediate output signal; and an adder configured to generate said intermediate output signal or an output signal of said digital filter based on an addition of said time delayed intermediate output signal and said intermediate signal.

Abstract: Communication signal symbol timing error detection and recovery apparatus and techniques are disclosed. A communication signal that includes symbols is sampled according to receive symbol timing. The samples are band-edge filtered to provide a filtered output signal including band edges of the samples. The filtered output signal is converted to baseband, and a phase error of the receive symbol timing is calculated based on the down converted baseband signal. The communication signal may include symbols associated with quadrature channels, in which case a respective filtered output signal that includes band edges of samples associated with each quadrature channel may be down converted. The down converted baseband signals may then be separated into upper and lower band-edge signals, which are used to calculate a phase error of the receive symbol timing. The upper and lower band-edge signals may also be used for other purposes, such as slope equalization and/or carrier synchronization.

Abstract: A method of balancing signal interconnect path delays between an analog domain and a digital domain of an integrated circuit includes applying a test signal to a selected one of a plurality of communication paths between the analog domain and the digital domain. A rising edge delay and a falling edge delay of the test signal is equalized by adjusting a body bias voltage of a delay element configured within the selected communication path. A rising edge delay and a falling edge delay for each of the remaining communication paths is compared with the equalized rising edge delay and falling edge delay of the selected communication path, and a body bias voltage for one or more of a plurality of delay elements configured within each of the remaining communication paths is adjusted until corresponding rising and falling edge delays thereof match the equalized rising edge delay and falling edge delay of the selected communication path.

Abstract: An equalization circuit is disclosed that enables high data rate transmission over high loss communications channels. Also disclosed is a set of functional blocks and update criteria that allow for the equalization function to be adapted for a large variety of different communications channels. A fully continuous adaptive equalizer is used in conjunction with a Decision Feedback Equalizer to fully equalize a wide range of communications channels. Interoperability and Bit Error Rate performance are optimized through compensation of pre-cursor inter-symbol interference, which is performed adaptively in the receiver as opposed to the transmitter.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design of a decision feedback equalizer (DFE) Clock-And-Data Recovery (CDR) architecture that utilizes/produces one sample-per-bit in the receiver and reduces bit-error-rate (BER) is provided. The design generally includes a receiver circuit. The receiver circuit generally includes a decision feedback equalizer (DFE) that produces one sample per bit, and means for automatically self-adjusting the DFE to enable an eye centering process by which peak energy is maintained within the receiver circuit when phase error is a minimum.

Abstract: A method and system for enhancing the performance of wideband digital RF transport systems, which enables the selection of a serial data rate to be transported over a transport medium. Thus, the present invention allows the system to be adapted to different transport mediums, and allows the user to set the serial data rate based on the input bandwidth of the system. The present invention also enables the transport of different bandwidth segments on a plurality of wideband channels by selecting an optimal clock sample rate for each bandwidth segment to be transported. Thus, the present invention allocates the bandwidth segments proportionally so that an optimum amount of bandwidth can be transported at the serial bit rate.

Abstract: In one embodiment, a method for compression is disclosed, including receiving source data, creating at least one template based upon common data, and creating a compressed record including a reference to the at least one template and a template delta that represents a difference between the at least one template and source data.

Abstract: A sequence of data within a bitstream may be determined. An offset value corresponding to a location of a validity code within the bitstream may be determined, relative to the sequence of data. A marker code and the offset value may be inserted into the bitstream in association with the sequence of data. Also, a received bitstream may be scanned to determine a potential marker code, a potential offset value may be determined, based on the potential marker code. A validity code within the bitstream may be determined, based on the potential offset value, and a validity of the potential marker code may be determined, based on the validity code.

Abstract: A video-processing architecture. In a specific embodiment, the architecture includes a first set of modules that accommodate certain functional traffic flowing between each module thereof. A broadcast module broadcasts video traffic to one or more of the first set of modules. In a more specific embodiment, the first set of modules and the broadcast module are configured to facilitate Isolation of video traffic from functional traffic. The first set of modules includes plural modules having similar module architecture. The similar module of architecture includes a local memory in each of the plural modules, wherein the local memory stores video data associated with the video traffic. The local, memory includes a first memory bank for storing input pixel data and a second memory bank for storing reconstructed pixel data.

Abstract: An approach is provided for distributing video signals. A digital video feed is received at a media distributor that includes a plurality of decoders and a corresponding plurality of modulators, wherein the digital video feed includes a plurality of video channels. The decoders decode the digital video feed to output analog video signals. The modulators modulate the analog video signals; and a combiner combines the outputs of the modulators to generate a channelized video signal.

Abstract: An integrated circuit for processing a media stream, including an RF input interface, an RF receiver unit configured for receiving an RF media stream from the RF input interface and extracting the media stream from the RF media stream, an input interface unit configured for receiving the media stream from a content source, a plurality of processing units, a switch, operatively connected to the RF receiver unit, to the input interface unit, and to each of the processing units, the switch configured to allow more than one of the operatively connected units to simultaneously receive the media stream, thereby allowing simultaneous processing of the media stream by the processing units, and an output interface, operatively connected to the switch, configured for outputting the simultaneously processed media stream. Related apparatus and methods are also described.

Abstract: Methods and systems for receiving, processing and/or decoding digital video transmissions are disclosed. In one embodiment, a method of a method of processing a digital video signal includes the steps of applying an initial set of video transmission parameter values to one or more digital video signal processes, decoding video transmission parameter information from the digital video signal, and updating the initial set of video transmission parameter values with the decoded video transmission parameter information. Embodiments of the present invention can advantageously demodulate and decode a digital video signal before transmission parameters embedded in the signal are completely decoded. Thus, the time to acquire and/or scan a digital video channel is improved.

Abstract: Provided are a method and apparatus for displaying video data without displaying delay in a video decoder which cannot judge the end of a picture. The method includes receiving video data including a picture formed of blocks; extracting an address of a current block in the received video data; and selectively displaying the picture based on the extracted address of the current block.

Abstract: An entropy coding apparatus. In a specific embodiment, the entropy coding apparatus, includes a renormalization process and an encode-decision process that communicates with the renormalization process. The encode-decision process is adapted to run in parallel with the renormalization process without the renormalization process being nested therein. In a more specific embodiment, the entropy coding apparatus includes an entropy encoder that is H.264 compliant. The encode-decision process includes a first .mechanism for pre-computing certain parameters to eliminate the need to nest the renormalization process within the encode-decision process. The renormalization process and the encode-decision process are components of a Context Adaptive Binary Arithmetic Coding (CABAC) module.

Abstract: Disclosed is a context modeller (103) used in decoding data (202) encoded using Context Adaptive Binary Arithmetic Coding, said context modeler (103) comprising a Read Only Memory (1001) for storing uninitialized context model values, said uninitialized context model values being stored in the Read Only Memory (1001) in a manner that enables a plurality of uninitialized context model values to be read from the Read Only Memory (1001) in a single clock cycle, an Arithmetic Logic Module (1003) comprising a plurality of parallel processing paths (2202-2207), each said processing path comprising a plurality of pipeline stages, a Random Access Memory (1005) and a memory controller (1008) for determining, using the Arithmetic Logic Module (1005) operating on said plurality of uninitialized context model values read from the Read Only Memory (1001) in each clock cycle, initialized context model values for storage in the Random Access Memory (1001) based upon header information in said incoming encoded data (202).

Abstract: Techniques and tools are described for adaptive deadzone (“DZ”) resizing during quantization. For example, in some embodiments, for quantization of an AC frequency coefficient of a block, a video encoder adjusts DZ size of a selected quantizer depending on the texture of the block. In other embodiments, a video encoder adjusts DZ size depending on the frequency of a coefficient being quantized. In still other embodiments, for quantization of an AC frequency coefficient of a block, a video encoder adjusts DZ size depending on the texture of the block and the frequency of the coefficient being quantized.

Abstract: An information processing apparatus is for decoding a video encoded sequence and includes: a CPU that decodes the video encoded sequence by executing software; a GPU that decodes the video encoded sequence; a main memory that temporarily stores data for the decoding process performed by the CPU; and a VRAM that temporarily stores data for the decoding process performed by the GPU, wherein the GPU continues the decoding process of subsequent pictures of at least the second and third pictures after the GPU decoded the referenced third picture, until the refresh first picture is subjected to the decoding process.

Abstract: An apparatus, a method, and a computer-readable medium having instructions encoded thereon that when executed cause a method to be carried out. The method includes dividing at least a portion of a picture of a video stream into parts of blocks, and processing the parts in parallel by a plurality of interconnected processors. The processing of a respective part by its respective processor includes edge detection and color segmentation to determine block-level edge features including block-level color-segmented edge features. Each processor also performs coding functions on its respective part of the picture. The method also includes block-level processing using the block-level edge features to determine which blocks in the picture are likely to be that of a face, the block-level processing being at the granularity of at least a block.

Abstract: There is provided an intra prediction system having high prediction performance and satisfactory encoding efficiency in a pattern image in which pixel value is periodically changed and a pattern image in which pixel value has a constant change tendency like gradation effect. A frequency component extraction unit allows a pixel value of an encoded MB to be made one-dimensional for one-dimensional orthogonal conversion. A frequency component-considering prediction value calculation unit receives, as inputs, a pixel value of an encoded adjacent MB and an alternating current frequency component output to create an orthogonal conversion coefficient. The orthogonal conversion coefficient then is subjected inverted orthogonal conversion (IDCT) to generate a prediction value p(i).

Abstract: Methods and apparatus to selectively transmit compressed data based upon whether a image movement threshold has been met. In one embodiment, edge map frames are transmitted during periods of camera movement. Edge maps generated from a video stream are processed to identify the periods of camera movement.

Abstract: A moving picture coding apparatus includes a computing unit configured to compute a distortion robustness indicating degree of imperceptibility of coding distortion in a region to be coded in an input picture, an estimation unit configured to estimate coding distortions based on a first prediction residual of an intra predicted picture, and a second prediction residual of an inter predicted picture, an estimation unit configured to estimate code lengths to be generated when coding the first and second prediction residuals, a computing unit configured to compute coding costs of the first and second prediction residuals by weighted addition of the coding distortions and code lengths so that effect of the code lengths more increases than that of the coding distortions as the distortion robustness increases, a selection unit configured to select one of the first and second prediction residuals for which the coding cost is minimized.

Abstract: A first motion vector points from a source region of a source picture to a destination region of a destination picture. A second motion vector is scaled from the first motion vector based on a first temporal distance between the source picture and the interpolation picture. A third motion vector is scaled from the first motion vector based on a second temporal distance between the destination picture and the interpolation picture. A weight of a first interpolation region of the interpolation picture is calculated using distortion energy of the source region. A first motion compensation picture compensated from the source region to a temporal position of the interpolation picture using the second motion vector, and a second motion compensation picture compensated from the destination region to the temporal position using the third motion vector are calculated.