Abstract: A method of reducing parametric variation in an integrated circuit (IC) chip and an IC chip with reduced parametric variation. The method includes: on a first wafer having a first arrangement of chips, each IC chip divided into a second arrangement of regions, measuring a test device parameter of test devices distributed in different regions; and on a second wafer having the first arrangement of IC chips and the second arrangement of regions, adjusting a functional device parameter of identically designed field effect transistors within one or more regions of all IC chips of the second wafer based on a values of the test device parameter measured on test devices in regions of the IC chip of the first wafer by a non-uniform adjustment of physical or metallurgical polysilicon gate widths of the identically designed field effect transistors from region to region within each IC chip.

Abstract: Generally, the present invention provides a variable thickness gate oxide anti-fuse transistor device that can be employed in a non-volatile, one-time-programmable (OTP) memory array application. The anti-fuse transistor can be fabricated with standard CMOS technology, and is configured as a standard transistor element having a source diffusion, gate oxide, polysilicon gate and optional drain diffusion. The variable gate oxide underneath the polysilicon gate consists of a thick gate oxide region and a thin gate oxide region, where the thin gate oxide region acts as a localized breakdown voltage zone. A conductive channel between the polysilicon gate and the channel region can be formed in the localized breakdown voltage zone during a programming operation. In a memory array application, a wordline read current applied to the polysilicon gate can be sensed through a bitline connected to the source diffusion, via the channel of the anti-fuse transistor.

Abstract: An integrated circuit device is disclosed as comprising a feature that is susceptible to oxidation. A poly-oxide coating is used over the feature susceptible to oxidation to protect the feature susceptible to oxidation from oxidizing. Various method can be used to form the poly-oxide coating include conversion of a ploy-silicon coating using UV O3 low temperature oxidation and plasma nitridation using either decoupled plasma nitridation or NH3 annealing.

Abstract: A high-k dielectric film, a method of forming the high-k dielectric film, and a method of forming a related semiconductor device are provided. The high-k dielectric film includes a bottom layer of metal-silicon-oxynitride having a first nitrogen content and a first silicon content and a top layer of metal-silicon-oxynitride having a second nitrogen content and a second silicon content. The second nitrogen content is higher than the first nitrogen content and the second silicon content is higher than the first silicon content.

Abstract: A method for forming a poly-crystalline silicon film on a substrate by positioning a substrate within a processing chamber, heating the processing chamber to a first temperature between about 640° C. and about 720° C., stabilizing a deposition pressure between about 200 Torr and about 350 Torr, introducing a silicon precursor into the processing chamber to deposit a silicon film comprising an amorphous or hemisphere grain film, and heating the processing chamber to a second temperature between about 700° C. and about 750 C.° to anneal the amorphous or hemisphere grain film into a poly-crystalline nano-crystalline grain film.

Abstract: A semiconductor device includes an Nch transistor having a first gate electrode and a Pch transistor having a second gate electrode. The first gate electrode and the second gate electrode are made of materials causing stresses of different magnitudes.

Abstract: The dR/R ratios of TMR and GMR devices, having a FeCo/NiFe type of free layer, have been significantly increased by inserting a suitable surfactant layer within (as opposed to above or below) the free layer. Our preferred surfactant material has been oxygen but similar-acting materials could be substituted. The concept can be applied to GMR CPP, CIP, and CCP sensor designs.

Abstract: One embodiment of the present invention includes multi-state current-switching magnetic memory element including a stack of two or more magnetic tunneling junctions (MTJs), each MTJ having a free layer and being separated from other MTJs in the stack by a seeding layer formed upon an isolation layer, the stack for storing more than one bit of information, wherein different levels of current applied to the memory element causes switching to different states.

Abstract: A detector system (100) with a microelectronic semiconductor chip (20) and a separate optoelectronic detector chip (10) is specified, wherein the detector chip is positioned on the semiconductor chip. A detector subassembly with such a detector system is also specified.

Abstract: Various embodiments of the present invention are directed to integrated circuits having photonic interconnect layers and methods for fabricating the integrated circuits. In one embodiment of the present invention, an integrated circuit comprises an electronic device layer and one or more photonic interconnect layers. The electronic device layer includes one or more electronic devices, and the electronic device layer is attached to a surface of an intermediate layer. One of the photonic interconnect layers is attached to an opposing surface of the intermediate layer, and each of the photonic interconnect layers has at least one photonic device in communication with at least one of the electronic devices of the electronic device layer.

Abstract: A solid state imaging device comprises: photoelectric conversion portions on or above a substrate; and color filters on or above the respective photoelectric conversion portions. Each of the photoelectric conversion portions comprises: a lower electrode on or above the substrate; a photoelectric conversion film on or above the lower electrode; and an upper electrode on or above the photoelectric conversion film. The device further comprises: a first inorganic material film that protects each of the photoelectric conversion portions, is formed by a first method and is above the upper electrode and below the color filters; a second inorganic material film that prevents characteristic deterioration of the photoelectric conversion portion caused by the first method, is formed by a second method and is between the upper electrode and the first inorganic material film; and a polymeric material film that enhances a function of the first inorganic material film and is on or above the first inorganic material film.

Abstract: A semiconductor device according to one embodiment includes a cell disposition region in which plural basic cells are disposed and a basic power supply wiring. In the cell disposition region are disposed a primitive cell connected to the basic power supply wiring and a high current consumption cell connected to the basic power supply wiring. Furthermore, in the cell disposition region are disposed regularly plural ordinary power switch cells that supply a first current to the primitive cell respectively. The power reinforcement cell including a power switch cell configured so as to flow a predetermined current to the high current consumption cell is disposed near the high current consumption cell.

Abstract: An SOI substrate having an SOI layer that can be used in practical applications even when a substrate with low upper temperature limit, such as a glass substrate, is used, is provided. A semiconductor device using such an SOI substrate, is provided. In bonding a single-crystal semiconductor layer to a substrate having an insulating surface or an insulating substrate, a silicon oxide film formed using organic silane as a material on one or both surfaces that are to form a bond is used. According to the present invention, a substrate with an upper temperature limit of 700° C. or lower, such as a glass substrate, can be used, and an SOI layer that is strongly bonded to the substrate can be obtained. In other words, a single-crystal semiconductor layer can be formed over a large-area substrate that is longer than one meter on each side.

Abstract: Structures for spanning gap in body-bias voltage routing structure. In an embodiment, a structure is comprised of at least one metal wire.

Abstract: A semiconductor device. The device includes an active region isolated by an isolation structure on a substrate, and a dielectric layer overlying the active region and the isolation structure. The dielectric layer comprises a lower part overlying the active region beyond the boundary of the active region and the isolation structure, and a protruding part overlying the boundary of the active region and the isolation structure.

Abstract: A semiconductor structure and a related method for fabrication thereof include an isolation region located within an isolation trench within a semiconductor substrate. The isolation region comprises; (1) a lower lying dielectric plug layer recessed within the isolation trench; (2) a U shaped dielectric liner layer located upon the lower lying dielectric plug layer and partially filling the recess; and (3) an upper lying dielectric plug layer located upon the U shaped dielectric liner layer and completely filling the recess. The isolation region provides for sidewall coverage of the isolation trench, thus eliminating some types of leakage paths.

Abstract: The invention provides a semiconductor device. The semiconductor device includes a semiconductor chip having an active surface on which pads are disposed, a passivation layer pattern disposed to cover the active surface of the semiconductor chip and to expose the pads, a first insulation layer pattern disposed on the passivation layer pattern, a second insulation layer pattern disposed on only a portion of the first insulation layer pattern, and redistribution line patterns electrically connected to the pads and disposed so as to extend across the second insulation layer pattern and the first insulation layer pattern. A method of fabricating the same is also provided.

Abstract: According to one aspect of the present invention, a method of forming a microelectronic assembly, such as an integrated passive device (IPD) (72), is provided. An insulating dielectric layer (32) having a thickness (36) of at least 4 microns is formed over a silicon substrate (20). At least one passive electronic component (62) is formed over the insulating dielectric layer (32).

Abstract: An electric discharge device includes a bipolar transistor configuration comprising a base, an emitter, and a collector. At least one pinched resistor is formed in a region comprising both the base and emitter so as to produce a pinched resistive area that develops a voltage once the bipolar transistor experiences junction breakdown.

Abstract: A crossbar structure includes a first layer or layers including first p-type regions and first n-type regions, a second layer or layers including second p-type regions and second n-type regions, and a resistance programmable material formed between the first layer(s) and the second layer(s), wherein the first layer(s) and the second layer(s) include first and second intersecting wiring portions forming a crossbar array.

Abstract: A method for manufacturing a semiconductor device that comprises implanting a first dopant type in a well region of a substrate to form implanted sub-regions that are separated by non-implanted areas of the well region. The method also comprises forming an oxide layer over the well region, such that an oxide-converted first thickness of the implanted sub-regions is greater than an oxide-converted second thickness of the non-implanted areas. The method further comprises removing the oxide layer to form a topography feature on the well region. The topography feature comprises a surface pattern of higher and lower portions. The higher portions correspond to locations of the non-implanted areas and the lower portions correspond to the implanted sub-regions.

Abstract: A method realizes a contact of a first well of a first type of dopant integrated in a semiconductor substrate next to a second well of a second type of dopant and forming with it a parasitic diode. The method comprises: formation of the first well; formation of the second well next to the first well; definition of an oxide layer above the first and second wells; and formation of an electric contact layer above the oxide layer in correspondence with the first well for realizing an electric contact with it. The definition step of the oxide layer further comprises a deposition step of this oxide layer above the whole first well and a removal step of at least one portion of the oxide layer in correspondence with a contact area of the first well so that the contact area has a shorter length than a length of the first well.

Abstract: Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The first and third doped regions are of the same type sandwiching the second doped region of the second type. A first input terminal is coupled to the first and third doped regions and a second terminal is coupled to the second doped region. At the interfaces of the doped regions are first and second depletion regions whose width can be varied by varying the voltage across the terminals from zero to full reverse bias.

Abstract: A method that solves the increased nucleation temperature that is exhibited during the formation of cobalt disilicides in the presence of Ge atoms is provided. The reduction in silicide formation temperature is achieved by first providing a structure including a Co layer including at least Ni, as an additive element, on top of a SiGe containing substrate. Next, the structure is subjected to a self-aligned silicide process which includes a first anneal, a selective etching step and a second anneal to form a solid solution of (Co, Ni) disilicide on the SiGe containing substrate. The Co layer including at least Ni can comprise an alloy layer of Co and Ni, a stack of Ni/Co or a stack of Co/Ni. A semiconductor structure including the solid solution of (Co, Ni) disilicide on the SiGe containing substrate is also provided.

Abstract: A semiconductive device is fabricated by forming, within a semiconductive substrate, at least one continuous region formed of a material having a non-uniform composition in a direction substantially perpendicular to the thickness of the substrate.

Abstract: A positive-intrinsic-negative (PIN)/negative-intrinsic-positive (NIP) diode includes a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate is of a first conductivity. The PIN/NIP diode includes at least one trench formed in the first main surface which defines at least one mesa. The trench extends to a first depth position in the semiconductor substrate. The PIN/NIP diode includes a first anode/cathode layer proximate the first main surface and the sidewalls and the bottom of the trench. The first anode/cathode layer is of a second conductivity opposite to the first conductivity. The PIN/NIP diode includes a second anode/cathode layer proximate the second main surface, a first passivation material lining the trench and a second passivation material lining the mesa. The second anode/cathode layer is the first conductivity.

Abstract: A method for controlling catalyst nanoparticle positioning includes establishing a mask layer on a post such that a portion of a vertical surface of the post remains exposed. The method further includes establishing a catalyst nanoparticle material on the mask layer and directly adjacent at least a portion of the exposed portion of the vertical surface.

Abstract: A method is disclosed which includes forming an opening in an insulating material, performing a plasma process to introduce nitrogen into a portion of the insulating material to thereby form a nitrogen-containing region at least on an inner surface of the opening, and, after forming the nitrogen-containing region, performing an etching process through the opening. A device is disclosed which includes an insulating material comprising a nitrogen-enhanced region that is proximate an opening that extends through the insulating material and a conductive structure positioned within the opening.

Abstract: The present invention is a semiconductor device characterized by including a substrate, an insulating film consisting of a fluorine added carbon film formed on the substrate, a barrier layer consisting of a silicon nitride film and a film containing silicon, carbon, and nitride formed on the insulating film, and a hard mask layer having a film containing silicon and oxygen formed on the barrier layer, wherein the barrier layer consists of a silicon nitride film and a film containing silicon, carbon, and nitride that are laminated from the bottom in that order, and functions to prevent the fluorine in the fluorine added carbon film from moving to the hard mask layer.

Abstract: According to an example embodiment, a stacked die package 800 includes a first die (806), first active circuitry (808) disposed on an upper surface of the first die, and a first conductive pattern (820) disposed on the first active circuitry. The stacked die package further includes a second die (826) disposed over the first die, where the first die is wider than the second die in a cross-section of the stacked die package, second active circuitry (828) disposed on an upper surface of the second die, and a second conductive pattern (830) disposed on the second active circuitry. The stacked die package further includes a first wirebond (822) that connects the first conductive pattern to the second conductive pattern and a mold compound (824) disposed on the first die, the mold compound encapsulating the second die and the wirebond.

Abstract: A source mounted semiconductor device package is described which includes a semiconductor die having first and second opposing major surfaces, first and second major electrodes disposed on respective major surfaces and a control electrode disposed on the second major surface, and a thin metal clip electrically connected to the first major electrode of the die. The thin metal clip has a relatively large surface area, and package resistance which is caused by skin effect phenomenon is reduced thereby in high frequency applications.

Abstract: A metal backing tab supports the semiconductor device and has an extending portion extending from an edge. A top leg, a middle leg and a bottom leg are all coupled to the semiconductor device and each has a lead terminal portion extending beyond the boundary of said molded housing. The top leg has a first top leg section that protrudes directly away from the molded housing, a second top leg section that bends toward a direction of a face of the molded housing, and a third top leg section bending downward. The middle leg has a first middle leg section connected to the package that protrudes away from the molded housing, and a middle leg downward section that points downward. The bottom leg has a first bottom leg section that protrudes away from the molded housing face, a second bottom leg section that points away from the molded housing face, and third bottom leg section that points downward.

Abstract: The present invention provides a method of manufacturing a semiconductor device in which a plurality of wires are connected to the same electrode on a semiconductor chip, the method making it possible to inhibit an increase in electrode area. First, ball bonding is performed to compressively bond a first ball to an electrode on a semiconductor chip to form a first connection portion. Wedge bonding is then performed on an inner lead. Subsequently, ball bonding is performed to compress a second ball against the first connection portion from immediately above to bond the second ball to form a second connection portion. Wedge bonding is then performed on the inner lead.

Abstract: In an exemplary embodiment, a packaged device having enhanced thermal dissipation characteristics includes a semiconductor chip having a major current carrying or heat generating electrode. The semiconductor chip is oriented so that the major current carrying electrode faces the top of the package or away from the next level of assembly. The packaged device further includes a conductive clip for coupling the major current carrying electrode to a next level of assembly, and a heat spreader device formed on or integral with the conductive clip. A portion of the heat spreader device may be optionally exposed.

Abstract: A chip package structure including a circuit pattern, a frame, a first adhesive layer, a plurality of leads, an insulating adhesive layer, a chip, a plurality of first bonding wires, a plurality of second bonding wires, and a molding compound is provided. The frame and leads are disposed around the circuit pattern. The first adhesive layer fastens the frame and the circuit pattern. The insulating adhesive layer is disposed between the leads and the frame. The chip has a plurality of bonding pads and is disposed on the first adhesive layer. The first bonding wires electrically connect the bonding pads individually to the circuit pattern. The second bonding wires electrically connect the leads individually to the circuit pattern. Thus, the bonding pads are electrically connected with the leads through the first bonding wires, the circuit pattern, and the second bonding wires. The molding compound covers foregoing components.

Abstract: This semiconductor device includes a semiconductor chip, and a lead arranged around the semiconductor chip to extend in a direction intersecting with the side surface of the semiconductor chip, and having at least an end farther from the semiconductor chip bonded to a package board, wherein a joint surface to the package board and an end surface orthogonal to the joint surface are formed on the end of the lead farther from the semiconductor chip, and a metal plating layer made of a pure metal is formed on the end surface.

Abstract: There is provided an imager package including an image sensor die attached to a transparent substrate such that sensitive image sensing components on the sensor die face the transparent substrate. In accordance with an embodiment of the present technique, the imager package may be coupled to an external package via bond wires and other interconnect elements. The sensor die and bond wires may be protected by an encapsulant on which the interconnect elements may be disposed. The bond wires may enable placement of the interconnect elements partially or directly above the sensor die, as opposed to around an outer periphery of the sensor die. There is further provided a method of manufacturing an imager package wherein interconnect elements may be located partially or directly above the sensor die, enabling the manufacture of smaller imager packages than previously envisioned.

Abstract: The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices. In preferred embodiments, the plastic body of one or more leaded packaged ICs bear conductive traces that create circuitry to provide stacking related electrical interconnections between the constituent ICs of a stacked module without the use of separate interposers or carrier structures. Typically, the circuitry is borne by the body of the upper one of the ICs of a two-IC leaded package stack to implement stacking-related connections between the constituent ICs.

Abstract: A stacked package module is disclosed, which comprises: a first package structure comprising a first circuit board with a first chip embedded therein, wherein the first chip has a plurality of electrode pads; the first circuit board comprises a first surface, an opposite second surface, a plurality of exposed electro-connecting ends, a plurality of first conductive pads on the first surface, a plurality of conductive vias, and at least one circuit layer, therewith the electrode pads of the first chip electrically connecting to the electro-connecting ends and the first conductive pads directly through the conductive vias and the circuit layer; and a second package structure electrically connecting to the first package structure through a plurality of first solder balls to make a package on package. The stacked package module of this invention has characters of compact size, high performance, high flexibility, and detachability.

Abstract: A microelectronic unit is provided in which front and rear surfaces of a semiconductor element may define a thin region which has a first thickness and a thicker region having a thickness at least about twice the first thickness. A semiconductor device may be present at the front surface, with a plurality of first conductive contacts at the front surface connected to the device. A plurality of conductive vias may extend from the rear surface through the thin region of the semiconductor element to the first conductive contacts. A plurality of second conductive contacts can be exposed at an exterior of the semiconductor element. A plurality of conductive traces may connect the second conductive contacts to the conductive vias.

Abstract: An integrated circuit device includes a semiconductor chip and a control chip at different supply potentials. A lead chip island includes an electrically conductive partial region and an insulation layer. The semiconductor chip is arranged on the electrically conductive partial region of the lead chip island and the control chip is cohesively fixed on the insulation layer.

Abstract: A semiconductor system (200) of one or more semiconductor interposers (201) with a certain dimension (210), conductive vias (212) extending from the first to the second surface, with terminals and attached non-reflow metal studs (215) at the ends of the vias. A semiconducting interposer surface may include discrete electronic components or an integrated circuit. One or more semiconductor chips (202, 203) have a dimension (220, 230) narrower than the interposer dimension, and an active surface with terminals and non-reflow metal studs (224, 234). One chip is flip-attached to the first interposer surface, and another chip to the second interposer surface, so that the interposer dimension projects over the chip dimension. An insulating substrate (204) has terminals and reflow bodies (242) to connect to the studs of the projecting interposer.

Abstract: A grid array package includes a rectangular pattern of electrical contacts around a perimeter of the package. The grid array package also includes a polar pattern of electrical contacts inside of, and concentric with, the rectangular pattern. The grid array package also includes additional electrical contacts arranged between the rectangular pattern and the polar pattern.

Abstract: A frame-shaped sidewall is provided on a metallic base plate surrounding a semiconductor element arranged on the metallic base plate, a first dielectric plate is arranged on one side of the semiconductor element and a first circuit pattern is formed on its surface, a second dielectric plate is arranged on another side of the semiconductor element and a second circuit pattern is formed and the first and the second dielectric plate. Power supply portions are provided on a part of the sidewall, through which a first or a second band-shaped conductors is penetrating. A relay post is provided on the dielectric plate. The first band-shaped conductor is connected to the circuit pattern by an interconnection via the relay post.

Abstract: A frame-shaped sidewall is provided on a metallic base plate surrounding a semiconductor element arranged on the metallic base plate, which is provided with a stepped surface positioned at lower level at a portion of the base plate than a main surface of the base plate. A first dielectric plate is arranged on one side of the semiconductor element and a first circuit pattern is formed on its surface, a second dielectric plate is arranged on another side of the semiconductor element and a second circuit pattern is formed on the first and the second dielectric plate. An insulator is mounted on the stepped surface of the base plate, which forms a part of the sidewall. Power supply portions are provided including a band-shaped conductor. An interconnection is provided which connects the band-shaped conductor to the circuit pattern.

Abstract: A heat dissipation unit and a semiconductor package having the same are disclosed. The semiconductor package includes a carrier; an electronic component mounted on and electrically connected to the carrier; a heat dissipation unit, which includes a flat section attached to the electronic component, extension sections connected to the flat section, and a heat dissipation section connected to the extension sections; and an encapsulant encapsulating the electronic component and the heat dissipation unit, wherein stress releasing sections are at least disposed at intersectional corners between the extension sections and the flat section so as to prevent projections from being formed by concentrated stresses in a punching process of the heat dissipation unit, thereby maintaining flatness of the flat section and further preventing circuits of the electronic component from being damaged due to a contact point produced between the electronic component and the flat section in a molding process.

Abstract: An embedded metal heat sink for a semiconductor device is described. The embedded metal heat sink for a semiconductor device comprises a metal thin layer, a metal heat sink and two bonding pads. The metal thin layer including a first surface and a second surface on opposite sides, wherein at least one semiconductor device is embedded in the first surface of the metal thin layer, and the semiconductor device has two electrodes with different conductivity types. The metal heat sink is deposited on the second surface of the metal thin layer. The bonding pads are deposed on the first surface of the metal thin layer around the semiconductor device and are respectively corresponding to the electrodes, wherein the electrodes are electrically and respectively connected to the corresponding bonding pads by at least two wires, and the bonding pads are electrically connected to an outer circuit.

Abstract: A method for fabricating a contact pad is disclosed. A first metal layer is disposed on a substrate for serving as a probing region. A second metal layer is disposed on the substrate thereafter to serve as an electrical connection region. Preferably, the first metal layer and the second metal layer are composed of different material and are electrically connected. The present invention uses two different metals to form a probing region and an electrical connection region of a contact pad. The probing region is used for providing a contacting surface for a test probe, whereas the electrical connection region is used for establishing an electrical connection in the later bumping or wire bonding process. By providing a contact pad having two different regions, the present invention is able to achieve probing process while prevent the surface of the contact pad from being damaged by the contact of test probes.

Abstract: A method of creating an electrical contact involves locating a barrier material at a location for an electrical connection, providing an electrically conductive bonding metal on the barrier material, the electrically conductive bonding metal having a diffusive mobile component, the volume of barrier material and volume of diffusive mobile component being selected such that the barrier material volume is at least 20% of the volume of the combination of the barrier material volume and diffusive mobile component volume. An electrical connection has an electrically conductive bonding metal between two contacts, a barrier material to at least one side of the electrically conductive bonding metal, and an alloy, located at an interface between the barrier material and the electrically conductive bonding metal. The alloy includes at least some of the barrier material, at least some of the bonding metal, and a mobile material.

Abstract: A method of manufacturing a wiring substrate comprises: a first step of forming, on a support plate, an electrode pad made of metal; a second step of etching the support plate in such a manner that the support plate has a shape which includes a projection portion to be contacted with the electrode pad; a third step of forming, on the surface of the support plate, an insulating layer for covering the electrode pad; a fourth step of forming, on the surface of the insulating layer, a conductive pattern to be connected to the electrode pad; and, a fifth step of removing the support plate.