Abstract: A technology for reducing distance between adjacent pixel electrodes to smaller than the limit set by conventional process margin and also preventing adjacent pixel electrodes from being short circuited is provided.

Abstract: An array substrate for a liquid crystal display device includes a substrate, a gate line and a data line crossing each other to define a pixel region, a thin film transistor at a crossing of the gate and data lines, a metal pattern over the gate line, a passivation layer exposing the substrate in the pixel region, a part of the thin film transistor and a part of the metal pattern, and a pixel electrode in the pixel region. The pixel electrode is connected to the part of the thin film transistor and contacts the part of the metal pattern. The metal pattern has at least one curved portion in a side contacting the pixel electrode.

Abstract: In a liquid crystal display device substrate, an insulating layer covers a thin film transistor. Another insulating layer covers a black matrix, which is formed on the insulating layer and covers the thin film transistor, a gate line, and a data line except a portion of a drain electrode. A first transparent conductive layer covers the top insulating layer and contacts the exposed portions of the drain electrode, a gate pad and a data pad. A buffer layer is formed on the first conductive layer and a color filter is formed on the buffer layer. The buffer layer is exposed by the color filter to reveal portions of the first conductive layer. A second transparent conductive layer covers the color filter and the revealed portions of the first conductive layer. The conductive layers are patterned to form pixel electrodes and double-layered gate and data pad terminals.

Abstract: A method for manufacturing a lower substrate of a liquid crystal display device is disclosed and more particularly, a method for manufacturing a color filter layer on a lower substrate is disclosed. This method is achieved by using a photosensitive insulating layer as a passivation layer or an overcoat of a thin film transistor to reduce the number of masks, or of photographic steps. The photosensitive insulating layer used in the method has the characteristics of both photoresist and passivation layers so as to protect a thin film transistor from moisture and oxygen. In addition, the number of masks, or of photographic steps used in this method can be further reduced by ink-jet printing a color filter layer or by half-tone mask technique.

Abstract: A light-emitting diode (LED) and a method for manufacturing the same are described. The method for manufacturing the LED comprises the following steps. An illuminant epitaxial structure is provided, in which the illuminant epitaxial structure has a first surface and a second surface on opposite sides, and a substrate is deposed on the first surface of the illuminant epitaxial structure. A metal layer is formed on the second surface of the illuminant epitaxial structure. An anodic oxidization step is performed to oxidize the metal layer, so as to form a metal oxide layer. An etching step is performed to remove a portion of the metal oxide layer, so as to form a plurality of holes in the metal oxide layer.

Abstract: A method of fabricating thin films of semiconductor materials by implanting ions in a substrate composed of at least two different elements at least one of which can form a gaseous phase on bonding with itself and/or with impurities includes the following steps: (1) bombarding one face of the substrate with ions of a non-gaseous heavy species in order to implant those ions in a concentration sufficient to create in the substrate a layer of microcavities containing a gaseous phase formed by the element of the substrate; (2) bringing this face of the substrate into intimate contact with a stiffener; and (3) obtaining cleavage at the level of the microcavity layer by the application of heat treatment and/or a splitting stress.

Abstract: A method of making an etch structure in a substrate involves the steps of providing a mask on a substrate with a pattern that leaves at least one opening leaving the substrate in direct contact with the ambient, performing an isotropic or quasi-isotropic etch through a mask to create a cavity under the mask, which mask is left behind as a suspended membrane above the cavity; and performing a subsequent anisotropic etch that etches anisotropically the pattern of the mask in the bottom of the cavity.

Abstract: Disclosed herein are a semiconductor package used in digital optical instruments and a method of manufacturing the same. The semiconductor package comprises a wafer made of a silicon material and having pad electrodes formed at one side surface thereof, an IR filter attached on the pad electrodes of the wafer by means of a bonding agent, terminals electrically connected to the pad electrodes, respectively, in via holes formed at the other side surface of the wafer, which is opposite to the pad electrodes, and bump electrodes, each of which is connected to one side of each of the terminals. The present invention is capable of minimizing the size of a semiconductor package having an image sensor, which is referred to as a complementary metal oxide semiconductor (CMOS) or a charge coupled device (CCD), through the application of a wafer level package technology, thereby reducing the manufacturing costs of the semiconductor package and accomplishing production on a large scale.

Abstract: A CMOS image sensor includes a substrate including a sensing part and a peripheral driving part; a first insulating interlayer formed over an entire surface of the substrate; a first metal line formed on the first insulating interlayer in each of the sensing and peripheral driving parts; a second insulating interlayer formed over the entire surface of the substrate including the first metal line; a second metal line formed on the second insulating interlayer in each of the sensor and peripheral drive parts; an etch-stop layer formed over the entire surface of the substrate including the second metal line; a third insulating interlayer formed on the peripheral driving part of the etch-stop layer; a third metal line formed on the third insulating interlayer; a fourth insulating interlayer formed on the third insulating interlayer including the third metal line, to be disposed in the peripheral driving part; and a fourth metal line formed on the fourth insulating interlayer.

Abstract: An encapsulated semiconductor device and method wherein an encapsulant material is deposited on the device in an environment that enhances device performance. Illustrative encapsulant materials are organic polymers, silicon polymers and metal/polymer-layered encapsulants. Encapsulant formation environments may include inert, reducing and ammonia gas environment. Further disclosed are an encapsulated transistor and a semiconductor device.

Abstract: The invention provides a taped lead frame for use in manufacturing electronic packages. The taped lead frame is composed of a tape and a lead frame formed from a plurality of individual metal features attached to the tape and arranged in a footprint pattern. The method of making the invention enables the thickness of conventional frames to shrink significantly to result in thinner packages for improved heat dissipation and shorter geometries for improved electrical performance. A plurality of such lead frames are arranged in an array on a sheet of tape and each lead frame is separated from surrounding lead frames by street regions on the tape such that no metal feature extends into a street region. Integrated circuit chips are attached and electrically connected to the lead frames and an encapsulant is applied, cured and dried over the lead frames and the street regions.

Abstract: A semiconductor package comprises a silicon substrate having an insulative surface; a patterned metal layer, formed on the insulative surface of the silicon substrate; an insulation layer formed on the patterned metal layer, and the patterned metal layer being partially exposed for functioning as at least a set of the device attaching pads and ball attaching pads; at least a device electrically connected to the set of the device attaching pads; a sealing compound for covering portions of the insulative surface of the silicon substrate and encapsulating the devices; and a plurality of solder balls attached to the set of ball attaching pads.

Abstract: An integrated circuit package is provided. The package includes a substrate having first and second surfaces and a plurality of conductive traces therebetween. The substrate further has a cavity therein and a heat slug is fixed to the substrate and spans the cavity. A semiconductor die is mounted to the heat slug such that at least a portion of the semiconductor die is disposed in the cavity. A plurality of wire bonds connect the semiconductor die to ones of the conductive traces of the substrate and an encapsulating material encapsulates the wire bonds and the semiconductor die. A ball grid array is disposed on the first surface of the substrate. Bumps of the ball grid array are in electrical connection with ones of the conductive traces.

Abstract: In one embodiment, an encapsulated electronic package includes a semiconductor chip having patterned solderable pads formed on a major surface. During an assembly process, the patterned solderable pads are directly affixed to conductive leads. The assembly is encapsulated using, for example, a MAP over-molding process, and then placed through a separation process to provide individual chip scale packages having flip-chip on lead frame interconnects.

Abstract: According to a resin encapsulation molding method for a semiconductor device, a resin-encapsulated substrate having a semiconductor device that is mounted on the substrate and that has a portion exposed is formed. With the method, a device-mounted substrate on which the semiconductor device is mounted is prepared and then the device-mounted substrate is set in one mold part. A release film is thereafter provided between the device-mounted substrate and the other mold part opposite to that one mold part. The one and other mold parts are then closed to press the release film against the portion of the semiconductor device. The device-mounted substrate has a projection enclosing the portion of the semiconductor device for preventing resin flash from being formed. When the mold parts are closed, the release film is pressed against the projection to allow the projection to dig into the release film.

Abstract: A semiconductor fuse box includes a fuse structure and a protective structure disposed between the fuse structure and an integrated circuit structure. The protective structure has at least one irregular side surface. The protective structure (which may also include a pad formed there-under) extends beyond a bottom of the fuse structure. Such an irregular side surface and such an extension of the protective structure minimize propagation of damaging energy to the adjacent integrated circuit structure when a laser beam is directed to the fuse structure.

Abstract: An organic thin film transistor and a method for fabricating the same are disclosed. The method for fabricating the organic thin film transistor includes forming a gate electrode on a substrate. A gate insulating layer is formed on an entire surface of the substrate including the gate electrode, and source and drain electrodes are formed at a predetermined interval from each other on the gate insulating layer. An organic semiconductor layer is formed on the entire surface of the substrate and a first protection layer is formed on the organic semiconductor layer. The first protection layer is patterned and the organic semiconductor layer etched using the remaining first protection layer as a mask. A second protection layer is then formed on the entire surface of the substrate.

Abstract: A semiconductor device with an increased channel length and a method for fabricating the same are provided. The semiconductor device includes: a substrate with an active region including a planar active region and a prominence active region formed on the planar active region; a gate insulation layer formed over the active region; and a gate structure including at least one gate lining layer encompassing the prominence active region on the gate insulation layer.

Abstract: A gate electrode (202) for a transistor including a metal gate structure (207) containing zirconium and a polycrystalline silicon cap (209) located there over. The metal gate structure (207) is located over a gate dielectric (205). The zirconium inhibits diffusion of silicon from the cap to the metal gate structure and gate dielectric. In one embodiment, the gate dielectric is a high K dielectric.

Abstract: A semiconductor device is fabricated with a selected critical dimension. A gate dielectric layer is formed over a semiconductor body. A gate layer comprised of a conductive material, such as polysilicon, is formed over the gate dielectric layer. The gate layer is patterned to form a gate electrode having a first horizontal dimension. One or more growth-stripping operations are performed to reduce a critical dimension of the gate electrode to a second horizontal dimension, where the second horizontal dimension is less than the first horizontal dimension.

Abstract: When the laser light is irradiated with high output in the manufacturing process for a semiconductor device, an attenuator is heated and cause a deformation due to the laser light scattered in the attenuator. As a result, the attenuation ratio of the attenuator fluctuates, and it is difficult to process the substrate with the homogeneous irradiation energy. It is a problem of the present invention to provide a laser irradiation apparatus, a method of irradiating laser light and a method of manufacturing a semiconductor device, which can perform the laser irradiation effectively and homogeneously. In the present invention, the thermal energy generated in an attenuator is absorbed by means of cooling in order to keep the temperature of the attenuator constant. By cooling the attenuator so as to prevent the change of the attenuation ratio, the function of the attenuator is protected. In addition, the energy fluctuation of the laser light irradiated on the substrate is also prevented.

Abstract: In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) providing a substrate; and (2) forming a first silicon-on-insulator (SOI) region having a first crystal orientation, a second SOI region having a second crystal orientation and a third SOI region having a third crystal orientation on the substrate. The first, second and third SOI regions are coplanar. Numerous other aspects are provided.

Abstract: Disclosed is an integrated circuit structure that has a substrate having at least two types of crystalline orientations. First-type transistors (e.g., NFETs) are formed on first portions of the substrate having a first type of crystalline orientation, and second-type transistors (e.g., PFETs) are formed on second portions of the substrate having a second type of crystalline orientation. Some of the first portions of the substrate comprise non-floating substrate portions, and the remaining ones of the first portions and all of the second portions of the substrate comprise floating substrate portions.

Abstract: A strained HOT MOSFET fabrication method. The MOSFET fabrication method includes providing a semiconductor structure which includes (a) a first semiconductor layer having a first crystallographic orientation, (b) a buried insulating layer on top of the first semiconductor layer, (c) a second semiconductor layer on top of the buried oxide layer. The second semiconductor layer has a second crystallographic orientation different from the first crystallographic orientation. The method further includes forming a third semiconductor layer on top of the first semiconductor layer which has the first crystallographic orientation. The method further includes forming a fourth semiconductor layer on top of the third semiconductor layer. The fourth semiconductor layer (a) comprises a different material than that of the third semiconductor layer, and (b) has the first crystallographic orientation.

Abstract: An object of the invention is to form an insulating film having favorable insulation and planarity. An insulating film is formed by performing heat treatment a resin containing a siloxane polymer after application, in an atmosphere including an inert gas as its main component and having an oxygen concentration of 5% or less and a water concentration of 1% or less. Preferably, an oxygen concentration is 1% or less and a water concentration is 0.1% or less. The resin containing a siloxane polymer includes a methyl group and a phenyl group. Further, the inert gas is nitrogen.

Abstract: A semiconductor device manufacturing method includes selectively removing portions of a buried oxide layer and first semiconductor layer in an SOI substrate having the first semiconductor layer formed above a semiconductor substrate with the buried oxide layer disposed therebetween and exposing part of the semiconductor substrate, removing an exposed region of the semiconductor substrate in a depth direction, and burying a second semiconductor region in the region from which part of the semiconductor substrate has been removed in the depth direction.

Abstract: Complementary metal oxide semiconductor metal gate transistors may be formed by depositing a metal layer in trenches formerly inhabited by patterned gate structures. The patterned gate structures may have been formed of polysilicon in one embodiment. The metal layer may have a workfunction most suitable for forming one type of transistor, but is used to form both the n and p-type transistors. The workfunction of the metal layer may be converted, for example, by ion implantation to make it more suitable for use in forming transistors of the opposite type.

Abstract: For obtaining p-Si by irradiating a laser beam to an a-Si layer to polycrystallize, an energy level in a region to be irradiated by the laser beam is set such that a level at the rear area of the region along a scan direction of the laser beam is lower than that at the front area or the center area of the region. The energy level at the front area or the center area of the region is set such that it is substantially equal to or more than the upper limit energy level which maximizes a grain size of the p-Si obtained. Since an energy profile is set as described above, when the laser beam is scanned on the a-Si layer, an irradiated energy of the laser on the region is gradually lowered from the upper limit as the laser beam passes through, which allows the semiconductor layer to be annealed within an optimal energy level during the latter half of the annealing process.

Abstract: Providing a semiconductor fabricating apparatus using a laser crystallization technique for enhancing the processing efficiency for substrate and for increasing the mobility of a semiconductor film. The semiconductor fabricating apparatus of multi-chamber system includes a film formation equipment for forming a semiconductor film, and a laser irradiation equipment. The laser irradiation equipment includes first means for controlling a laser irradiation position relative to an irradiation object, second means (laser oscillator) for emitting laser light, third means (optical system) for processing or converging the laser light, and fourth means for controlling the oscillation of the second means and for controlling the first means in a manner that a beam spot of the laser light processed by the third means may cover a place determined based on data on a mask configuration (pattern information).

Abstract: Apparatus and method for forming a polycrystalline silicon thin film by converting an amorphous silicon thin film into the polycrystalline silicon thin film using a metal are provided. The method includes: a metal nucleus adsorbing step of introducing a vapor phase metal compound into a process space where the glass substrate having the amorphous silicon formed thereon is disposed, to adsorb a metal nucleus contained in the metal compound into the amorphous silicon layer; a metal nucleus distribution region-forming step of forming a community region including a plurality of silicon particles every metal nucleus in a plane boundary region occupied by the metal compound by a self-limited mechanism due to the adsorption of the metal nucleus; and an excess gas removing step of purging and removing an excess gas which is not adsorbed in the metal nucleus distribution region-forming step.

Abstract: A method is described for designing a micro electromechanical device in which the risk of self-actuation of the device in use is reduced. The method includes locating a first conductor in a plane and locating a second conductor with its collapsible portion at a predetermined distance above the plane. The method also includes laterally offsetting the first conductor by a predetermined distance from a region of maximum actuation liability. The region of maximum actuation liability is where an attraction force to be applied to activate the device is at a minimum.

Abstract: A method of manufacturing a semiconductor integrated circuit including a logic part and a memory array part, the logic part having N-type and P-type FETs, and the memory array part having N-type and P-type FETs, includes the steps of forming N-type and P-type FETs constituting the logic part and the memory array part, thereafter sequentially forming a first insulation film having a tensile stress and a second insulation film on the whole surface, selectively removing the second insulation film and the first insulation film present on the upper side of the region of the P-type FET constituting the logic part, then forming a third insulation film having a compressive stress on the whole surface, and thereafter selectively removing the third insulation film present on the upper side of the region of the N-type FET constituting the logic part and the third insulation film present on the upper side of the regions of the N-type and P-type FETs constituting the memory array part.

Abstract: A method for forming BiCMOS integrated circuits and structures formed according to the method. After forming doped wells and gate stacks for the CMOS devices and collector and base regions for the bipolar junction transistor, an emitter layer is formed within an emitter window. A dielectric material layer is formed over the emitter layer and remains in place during etching of the emitter layer and removal of the etch mask. The dielectric material layer further remains in place during source/drain implant doping and activation of the implanted source/drain dopants. The dielectric material layer functions as a thermal barrier, to limit out-diffusion of the emitter dopants during the activation step.

Abstract: A stress enhanced MOS circuit and methods for its fabrication are provided. The stress enhanced MOS circuit comprises a semiconductor substrate and a gate insulator overlying the semiconductor substrate. A gate electrode overlies the gate insulator; the gate electrode has side walls and comprising a layer of polycrystalline silicon having a first thickness in contact with the gate insulator and a layer of electrically conductive stressed material having a second thickness greater than the first thickness overlying the layer of polycrystalline silicon. A stress liner overlies the side walls of the gate electrode.

Abstract: In a film formation method of a semiconductor device including a plurality of silicon-based transistors or capacitors, there exist hydrogen at least in a part of the silicon surface in advance, and the film formation method removes the hydrogen by exposing the silicon surface to a first inert gas plasma. Thereafter a silicon compound layer is formed on the surface of the silicon gas by generating plasma while using a mixed gas of a second inert gas and one or more gaseous molecules, such that there is formed a silicon compound layer containing at least a pat of the elements constituting the gaseous molecules, on the surface of the silicon gas.

Abstract: A p impurity region (3) defines a RESURF isolation region in an n? semiconductor layer (2). A trench isolation structure (8a) and the p impurity region (3) together define a trench isolation region in the n? semiconductor layer (2) in the RESURF isolation region. An nMOS transistor (103) is provided in the trench isolation region. A control circuit is provided in the RESURF isolation region excluding the trench isolation region. An n+ buried impurity region (4) is provided at the interface between the n? semiconductor layer (2) and a p? semiconductor substrate (1), and under an n+ impurity region 7 connected to a drain electrode (14) of the nMOS transistor (103).

Abstract: A method for making a semiconductor device structure includes producing a substrate having formed thereon a gate with spacers, respective source and drain regions adjacent to the gate and an; disposing a first metallic layer on the gate with spacers, and the source and drain regions, disposing a second metallic layer on the first metallic layer; doping the first metallic layer with a first dopant through a portion of the second metal layer disposed over the second gate with spacers; and then heating the intermediate structure to a temperature and for a time sufficient to form a silicide of the first metallic layer. This first layer is, for example, Ni while the second layer is, for example, TiN.

Abstract: Method of manufacturing a semiconductor device includes: forming a substrate protection film to cover an n-type FET forming region having a first gate electrode and a p-type FET forming region having a second gate electrode; opening the p-type FET forming region by patterning a resist film after the resist film is formed to cover the n-type FET and p-type FET forming regions; exposing the surface of the semiconductor substrate by selectively removing the substrate protection film in the p-type FET forming region, leaving the film only on side walls of the second gate electrode; forming a pair of p-type extension regions at both sides of the second gate electrode, by doping impurities to the semiconductor substrate, with the resist film, the second gate electrode, and the substrate protection film formed on side walls of the second electrode; and removing the resist film formed on the n-type FET forming region.

Abstract: A method for fabricating a contact structure for a stack storage capacitor includes forming the contact structure in a node contact region with contact openings, an insulating liner and a conductive filling material prior to the patterning of bit lines.

Abstract: A method for manufacturing a semiconductor memory having a memory cell selection transistor and a capacitor, comprises a step of forming a polysilicon plug having a large-diameter portion on a side of the capacitor, a step of forming a hole reaching the large-diameter portion by etching an insulating film formed on the large-diameter portion using the large-diameter portion as an etching stopper layer, and a step of forming a conductive film inside the hole so as to serve as an electrode for the capacitor.

Abstract: A method is provided for fabricating a semiconductor component that includes a capacitor having a high capacitance per unit area. The component is formed in and on a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator. The method comprises forming a first capacitor electrode in the first semiconductor layer and depositing a dielectric layer comprising Ba1-xCaxTi1-yZryO3 overlying the first capacitor electrode. A conductive material is deposited and patterned to form a second capacitor electrode overlying the dielectric layer, thus forming a capacitor having a high dielectric constant dielectric. An MOS transistor in then formed in a portion of the second semiconductor layer, the MOS transistor, and especially the gate dielectric of the MOS transistor, formed independently of forming the capacitor and electrically isolated from the capacitor.

Abstract: The present invention comprises a method including the steps of providing a substrate; forming a trench in the substrate; forming a buried plate in the substrate about the trench; depositing a dielectric layer within the trench; and then depositing a P-type metal atop the dielectric layer, where the dielectric layer is positioned between the P-type metal and the buried plate. Another aspect of the present invention provides a trench capacitor where said trench capacitor comprises a trench formed in a substrate, a buried plate formed in the substrate about the trench; a node dielectric; and a P-type metal liner deposited within the trench, where the P-type metal liner is separated from the buried plate by the node dielectric. A P-type metal is defined as a metal having a work function close to the Si valence band, approximately equal to 5.1 eV.

Abstract: A ferroelectric memory device includes a semiconductor substrate, ferroelectric capacitors, conductive patterns, and plate lines. The ferroelectric capacitors are arranged in rows and columns on the semiconductor substrate. The conductive patterns are arranged in even numbered and odd numbered rows. Each of the conductive patterns is on, and electrically connected to, a plurality of adjacent ones of the ferroelectric capacitors. The plate lines are in rows that extend along even numbered and odd numbered columns. The plate lines in the even numbered columns are electrically connected to at least two of the conductive patterns in the even numbered rows and are electrically isolated from the conductive patterns in the odd numbered rows. The plate lines in the odd numbered columns are electrically connected to at least two of the conductive patterns in the odd numbered rows and are electrically isolated from the conductive patterns in the even numbered rows.

Abstract: A method of fabricating a semiconductor device having a capacitor is provided. The method includes forming second, third, fourth, and fifth insulating layers on a first conductive layer formed in a first insulating layer. The fourth insulating layer is patterned into a first pattern before forming the fifth insulating layer thereupon. A capacitor and contact plug are formed by etching the fifth insulating layer to expose the first pattern; etching the third insulating layer using the exposed first pattern as a mask to expose the second insulating layer; exposing the first conductive layer at a capacitor region and contact plug region by etching the exposed second insulating layer; forming a second conductive layer on the exposed first conductive layer and sidewalls of the insulating layers; forming a dielectric on the second conductive layer in the capacitor region; and filling the capacitor and contact plug regions with a third conductive layer.

Abstract: A flash memory device has a resistivity measurement pattern and method of forming the same. A trench is formed in an isolation film in a Self-Aligned Floating Gate (SAFG) scheme. The trench is buried to form a resistivity measurement floating gate. This allows the resistivity of the floating gate to be measured even in the SAFG scheme. Contacts for resistivity measurement are directly connected to the resistivity measurement floating gate. Therefore, variation in resistivity measurement values, which is incurred by the parasitic interface, can be reduced.

Abstract: A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface.

Abstract: A memory structure formed between two doping regions in a semiconductor substrate includes two conductive blocks functioning as floating gates formed at two sides of a first conductive line functioning as a select gat and insulated from the first conductive line with two first dielectric spacers therebetween, wherein the two conductive blocks each have a raised top and raised parts of sides relative to the top of the first conductive line. A first dielectric layer is formed on the tops and the parts of the sides of the two conductive blocks. A second conductive line functioning as a word line is formed on the first dielectric layer, wherein the second conductive line has a part deposited between the two conductive blocks and is substantially perpendicular to the first conductive line and two doping region functioning as bit lines.

Abstract: A method for making a semiconductor device having non-volatile memory cell transistors and transistors of another type is provided. In the method, a substrate is provided having an NVM region, a high voltage (HV) region, and a low voltage (LV) region. The method includes forming a gate dielectric layer on the HV and LV regions. A tunnel oxide layer is formed over the substrate in the NVM region and the gate dielectric in the HV and LV regions. A first polysilicon layer is formed over the tunnel dielectric layer and gate dielectric layer. The first polysilicon layer is patterned to form NVM floating gates. An ONO layer is formed over the first polysilicon layer. A single etch removal step is used to form gates for the HV transistors from the first polysilicon layer while removing the first polysilicon layer from the LV region.

Abstract: A structure and method of forming a body contact for an semiconductor-on-insulator trench device. The method including: forming set of mandrels on a top surface of a substrate, each mandrel of the set of mandrels arranged on a different corner of a polygon and extending above the top surface of the substrate, a number of mandrels in the set of mandrels equal to a number of corners of the polygon; forming sidewall spacers on sidewalls of each mandrel of the set of mandrels, sidewalls spacers of each adjacent pair of mandrels merging with each other and forming a unbroken wall defining an opening in an interior region of the polygon, a region of the substrate exposed in the opening; etching a contact trench in the substrate in the opening; and filling the contact trench with an electrically conductive material to form the contact.

Abstract: The invention includes methods of forming epitaxial silicon-comprising material and methods of forming vertical transistors. In one implementation, a method of forming epitaxial silicon-comprising material includes providing a substrate comprising monocrystalline material. A first portion of the monocrystalline material is outwardly exposed while a second portion of the monocrystalline material is masked. A first silicon-comprising layer is epitaxially grown from the exposed monocrystalline material of the first portion and not from the monocrystalline material of the masked second portion. After growing the first silicon-comprising layer, the second portion of the monocrystalline material is unmasked. A second silicon-comprising layer is then epitaxially grown from the first silicon-comprising layer and from the unmasked monocrystalline material of the second portion. Other aspects and implementations are contemplated.