Abstract: An active matrix substrate including a substrate, a plurality of pixel units, a plurality of driving lines, an electron static discharge (ESD) protection circuit and a floating line is provided. The substrate has an active region and a peripheral region connected with the active region. The pixel units are arranged in a matrix in the active region. The driving lines electrically connected to the pixels are disposed in the active region and the peripheral region. The ESD protection circuit and the floating line are disposed in the peripheral region of the substrate. The ESD protection circuit is electrically connected to the driving lines. The ESD protection circuit includes an outer short ring (OSR) and an inner short ring (ISR) disposed between the pixel units and the OSR. The floating line is located beside the outer driving line.

Abstract: A semiconductor device features connecting gate patterns of all transistors to a N+ or +P junction by the first connected wiring layer to prevent degradation of characteristics of the semiconductor device which results from plasma damages during a process. In order to connect a junction to a gate layer weak to plasma damages, the gate layer is connected to the N+ or P+ junction when a first wiring layer after a transistor is formed. As a result, when the gate layer is charged up by plasma damages, the gate layer is discharged by the junction or provided to receive (?) ions or electrons so that a gate oxide is not affected by plasma damages.

Abstract: Method, apparatus, and article of manufacture for a diode defined by a portion of a gate layer of an integrated circuit. Illustrative, non-limiting embodiments of the invention are provided, including a temperature compensated DRAM, a temperature compensated CPU, a temperature compensated logic circuit and other on-chip temperature sensor applications.

Abstract: An ESD device includes a low doped well connected to a first contact and a diffusion area connected to a second contact. A substrate between the low doped well and the diffusion area has a dopant polarity that is opposite a dopant polarity of the low doped well and the diffusion area. A distance between the low doped well and the diffusion area determines a triggering voltage of the ESD device. A depletion region is formed between the low doped well and the substrate when a reverse bias voltage is applied to the ESD device. A current discharging path is formed between the first contact and the second contact when the depletion region comes in to contact with the diffusion area. The substrate is biased by a connection to the second contact. Alternatively, an additional diffusion area with the same dopant polarity, connected to a third contact, biases the substrate.

Abstract: Some embodiments include an isolation layer defining an active region of a substrate, a gate pattern formed on the active region, and source/drain regions formed in the active region. Sidewall spacers are formed on sidewalls of the gate pattern, and a blocking insulation layer is formed on the isolation layer and on a portion of the active region neighboring the isolation layer. A silicide layer is formed on source/drain regions between the blocking insulation layer and the sidewall spacers. Some embodiments include defining an active region of a substrate using an isolation layer, forming a gate pattern on the active region, implanting impurities into the active region, and forming a spacer insulation layer on a surface of the substrate with the gate pattern. A region of the spacer insulation layer becomes thinner the closer it is to the gate pattern. Other embodiments are described in the claims.

Abstract: A stacked non-volatile memory device uses amorphous silicon based thin film transistors stacked vertically. Each layer of transistors or cells is formed from a deposited a-Si channel region layer having a predetermined concentration of carbon to form a carbon rich silicon film or silicon carbide film, depending on the carbon content. The dielectric stack is formed over the channel region layer. In one embodiment, the dielectric stack is an ONO structure. The control gate is formed over the dielectric stack. This structure is repeated vertically to form the stacked structure. In one embodiment, the carbon content of the channel region layer is reduced for each subsequently formed layer.

Abstract: A first SiO2 thin film, a tungsten gate electrode, and a second SiO2 thin film are selectively formed on a first n+-type GaN contact semiconductor layer in that order and in a multilayer film structure having the three layers, a stripe-shaped opening is formed. Via the opening, an undoped GaN channel semiconductor layer and the second n+-type GaN contact semiconductor layer are formed so that both the layers are regrown by, for example, metal organic chemical vapor deposition. A source electrode and a drain electrode are formed so as to contact the corresponding second and first n+-type GaN contact semiconductor layers. The regrown undoped GaN channel semiconductor layer and the regrown second n+-type GaN contact semiconductor layer are horizontally grown portions and hence, the contact area of the electrode can be made larger than the area of the opening.

Abstract: The present invention discloses a transistor for a semiconductor device capable of preventing the generation of a depletion capacitance in a gate pattern due to the diffusion of impurity ions. The present invention also discloses a method of fabricating the transistor.

Abstract: An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal.

Abstract: Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method includes coupling a plurality of singulated imaging dies to a support member. The individual imaging dies include an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality of external contacts operably coupled to the integrated circuit. The method further includes forming a plurality of stand-offs on corresponding imaging dies before and/or after the imaging dies are singulated and electrically connecting the external contacts of the imaging dies to corresponding terminals on the support member. The individual stand-offs include a portion between adjacent external contacts.

Abstract: A PIN photodiode, and a method of manufacturing a PIN photodiode that reduces dielectric delamination and increases device reliability. The process proceeds by forming an first type electrode layer on the substrate; forming an intrinsic layer of the first type electrode layer; forming a second type electrode layer on the intrinsic layer; etching the second type electrode layer to define a mesa shaped structure; and depositing a passivation material over the mesa shaped structure.

Abstract: The invention concerns a photovoltaic device (1) comprising a plurality of p-i-n type photovoltaic cells (2) arranged on a substrate (3), wherein said cells (2) are arranged, in the form of a single layer, parallel to one another and the electrical conductive layer (7) is arranged between the n layer (6) and the p layer (5) of each consecutive cell (2) so as to electrically connect said cells (2) in series. The invention also concerns the use of such a device (1) as glazing, a method for making such a device (1), a method for controlling a transparent photovoltaic device (1) as well as an installation for implementing said control method.

Abstract: Embodiments of the invention include a temperature sensor apparatus, method and system for providing an output voltage response that is linear to the temperature of the integrated circuit to which the temperature sensor belongs and/or the integrated circuit die on which the temperature sensor resides. The output voltage of the temperature sensor has an adjustable gain component and an adjustable voltage offset component that both are adjustable independently based on circuit parameters. The temperature sensor includes a conventional bandgap circuit, which generates an internal PTAT (proportional to absolute temperature) current to produce a bandgap reference voltage, and a current mirror arrangement that provides a scaled current that is proportional to the bandgap circuit's PTAT current. Conventionally, the scaled PTAT current is sourced through an output resistor to provide the output voltage of the temperature sensor.

Abstract: A semiconductor device including memory cells isolated by a trench that may be self aligned with a stacked film pattern (7) has been disclosed. The memory cells may be flash memory cells having an active gate film (2) that may be thinner than a gate oxide film (30). The active gate film (2) may be located in a central portion under of a gate electrode (3). The gate oxide film (30) may be located under end portions of the gate electrode (3). In this way, a distance between a shoulder portion of a trench (11) and a gate electrode (3) may be increased. Thus, an electric field concentration in the shoulder portion of the trench (11) may be decreased and memory cell characteristics may be improved.

Abstract: The present invention provides a non-volatile memory device and fabricating method thereof, by which a cell size can be lowered despite high degree of cell integration and by which the device fabrication is facilitated. The present invention includes at least two trench isolation layers arranged in a device isolation area of a semiconductor substrate, each having a first depth, a first conductive type well arranged between the at least two trench isolation layers to have a second depth smaller than the first depth, a second conductive type source region and a second conductive type drain region arranged in a prescribed upper part of the first conductive type well to be separated from each other by a channel region in-between, an ONO layer on the channel region of the semiconductor substrate, the ONO layer comprising a lower oxide layer, a nitride layer, and an upper oxide layer, and a wordline conductor layer on the ONO layer.

Abstract: A semiconductor device includes a dual gate dielectric layer that increases a performance of a semiconductor device. The semiconductor device includes a first dielectric layer having a predetermined thickness on a semiconductor substrate. The first dielectric layer is formed on a first region. The semiconductor device also includes a second dielectric layer having a dielectric constant higher than that of the first dielectric layer. The second dielectric layer is formed on both the first region and a second region.

Abstract: A semiconductor device include a plurality of active element cells including first element regions of a first conductivity type and second element regions of a second conductivity type, the second element regions disposed between the first element regions; and isolation regions disposed between the active element cells so as to isolate the active element cells from each other, the isolation regions being filled with a plurality of semi-insulating particles including granular insulators covered by semiconductor films.

Abstract: An impedance matching network is integrated on a first die and coupled to a second die, with the first and second dies mounted on a conductive back plate. The impedance matching network comprises a first inductor bridging between the first and second dies, a second inductor coupled to the first inductor and disposed on the first die, and a metal-insulator-metal (MIM) capacitor disposed on the first die. The MIM capacitor has a first metal layer coupled to the second inductor, and a second metal layer grounded to the conductive back plate. A method for manufacturing the integrated impedance matching network comprises the steps of forming an inductor on a die, forming a capacitor on the die, coupling the capacitor to the inductor, coupling the die bottom surface and the capacitor to a conductive plate, and coupling the inductor to another inductor that bridges between the die and another die.

Abstract: A method of forming semiconductor device treating a surface of a substrate to produce a discontinuous growth of a material on the surface through rapid thermal oxidation of the substrate surface at a temperature of less than about 700° C.

Abstract: Described herein are embodiments of a bipolar junction transistor including a plurality of base terminal rings having an emitter terminal ring between any two base terminal rings of the plurality of base terminal rings, and a collector terminal ring surrounding the plurality of base terminal rings and the emitter terminal ring and methods of manufacturing the same.

Abstract: An improved p-type gallium nitride-based semiconductor device is disclosed. The device includes a structure with at least one p-type Group III nitride layer that includes some gallium, a first silicon dioxide layer on the p-type layer, a layer of a Group II metal source composition on the first SiO2layer, and a second SiO2 layer on the Group II metal source composition layer.

Abstract: A high power shunt switch comprises a leadframe including a paddle for supporting a shunt element, and a plurality of bond pads located around a periphery of the paddle, wherein at least a first subset of the bond pads are aligned in a substantially straight-line configuration. A shunt element is fixedly attached to the paddle and wire bonded to a top surface of one the bond pads. An encapsulant is disposed on the paddle, the shunt element, the plurality of bond pads, and the wire bond, thereby forming an encapsulated package structure. The package structure is positioned and attached to a transmission line such that the bottom surfaces of each of the at least first subset of bond pads are in simultaneous contact with the transmission line. The package structure and the transmission line are fixedly attached to a suitable substrate.

Abstract: A circuit board including a flexible insulating substrate, a plurality of conductive wirings placed in line on the flexible insulating substrate, and bumps provided at end portions of the respective conductive wirings positioned in a region for mounting a semiconductor chip is provided. The circuit board further includes an auxiliary conductive wiring positioned at an outermost corner of the region for mounting the semiconductor chip, being adjacent to and an outside the outermost conductive wiring, and an auxiliary bump formed on the auxiliary conductive wiring in line with the bumps on the conductive wirings.

Abstract: In certain embodiments, a leadframe structure for forming one or more integrated circuit packages includes a number of adjacent substantially parallel lead bars adapted to receive a die associated with an integrated circuit at one or more of the lead bars such that the one or more lead bars extend from opposite sides of the die. The leadframe structure also includes one or more support structures (e.g. lead support bars 26) adapted to help hold the lead bars together.

Abstract: A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a leadframe structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead. The die attach surface and the lead surface can be in different planes.

Abstract: In a manufacturing method of a hybrid integrated circuit device 10 according to the present invention, a first dummy pattern D1 is provided on a first wiring layer 18A. Furthermore, a second dummy pattern D2 is provided on a second wiring layer 18B. The first dummy pattern D1 and the second dummy pattern D2 are connected through a connection part 25 which penetrates an insulation layer 17. Hence, heat dissipation through a dummy pattern can be actively performed. In addition, even in the cases where a multi-layered wiring is formed, it is possible to provide a circuit device which can secure a heat dissipation property.

Abstract: A semiconductor component includes an integrated semiconductor chip and a chip housing. The chip housing has first, second, third and fourth conductor tracks that connect input and output connections of the semiconductor chip to external contact connections on the underside and top side of the chip housing in such a way that a loop back interconnection of a plurality of semiconductor components stacked one on top of another is made possible without subsequent structural alterations to the chip housings thereof.

Abstract: A silicon condenser microphone package includes a transducer unit, a substrate, and a cover. The substrate includes an upper surface transducer unit is attached to the upper surface of the substrate and overlaps at least a portion of the recess wherein a back volume of the transducer unit is formed between the transducer unit and the substrate. The cover is placed over the transducer unit and either the cover or the substrate includes an aperture.

Abstract: A cooling device including a thermally conductive body with a first mating surface, a first solder wettable material disposed in a pattern at a portion of the first mating surface, and a reflowable solder material disposed at the first mating surface. A portion of the solder material is configured to be capable of contacting an adjacently disposed second mating surface, and when melted, to form a single flow front through a bond line gap between the first mating surface of the cooling device and the second mating surface of, for example, a thermal component. A mating surface of the cooling device is positioned adjacent to a mating surface of a thermal component and the solder material is heated at least to its melting point.

Abstract: An apparatus, method, and system for providing thermal management for an integrated circuit includes a first metallic layer directly placed on a back surface of the integrated circuit. An integrated heat spreader with a substantially cap-like shape is placed over the integrated circuit, with an aperture of a ceiling wall of the integrated heat spreader exposing a back surface of the integrated circuit at least in part. The first metallic layer is directly placed on top of an exterior surface of the ceiling wall of the integrated heat spreader as well as the back surface of the integrated circuit.

Abstract: The present invention provides an electronic packaging process. The surface of the chip carrier includes at least a chip attachment region and a film attachment region adjacent to the chip attachment region. At least a baffle is formed on the surface of the chip carrier, between the chip attachment region and the film attachment region. After attaching the thin film to the film attachment region of the chip carrier through an affixture layer, the chip is electrically and physically connected to the chip attachment region of the chip carrier through an adhesive layer. The baffle can effectively prevent the gas that is released from the adhesive layer from damaging the bonding between the thin film and the affixture layer. Therefore, almost no bubbles are formed and good electrical connection between the thin film and the affixture layer is maintained.

Abstract: An integrated circuit package-in-package system is provided including forming an external interconnect having an upper portion and a lower portion; forming a packaged device; mounting an active device over the packaged device; connecting the active device to the packaged device and the upper portion; and molding the packaged device, the active device, and the upper portion.

Abstract: The RF device of the present invention includes: a semiconductor substrate; and first and second semiconductor components provided on the substrate. Each of the components includes source electrodes, a gate electrode and a drain electrode. And multiple through holes, which pass through the substrate in the thickness direction, are opened in a region of the substrate between the two components. To enhance the effect of suppressing electrical interference between the components, a gap between two adjacent ones of the through holes is preferably smaller than the thickness of the substrate.

Abstract: The present invention provides a semiconductor device comprising a semiconductor substrate, and transistors formed on the semiconductor substrate, wherein control electrode terminals constituting external electrode terminals of the transistors, and first electrode terminals which transmit output signals, are provided on a main surface of the semiconductor substrate, wherein the control electrode terminals are provided at least one, and a plurality of the first electrode terminals are arranged on one side and a plurality of the first electrode terminals are arranged on the other side with the control electrode terminals being interposed therebetween, wherein a portion including the control electrode terminals and a plurality of the first electrode terminals located on one side of the control electrode terminals constitute a first transistor portion, and wherein a portion including the control electrode terminals and a plurality of the first electrode terminals located on the other side of the control electrode

Abstract: A first insulating film is provided between a lower interconnect and an upper interconnect. The lower interconnect and the upper interconnect are connected to each other by way of a via formed in the first insulating film. A dummy via or an insulating slit is formed on/in the upper interconnect near the via.

Abstract: The present invention provides an enhanced interconnect structure with improved reliability. The inventive interconnect structure has enhanced mechanical strength of via contacts provided by embedded metal liners. The embedded metal liners may be continuous or discontinuous. Discontinuous embedded metal liners are provided by a discontinuous interface at the bottom of the via located within the interlayer dielectric layer.

Abstract: A circuit board (A1) includes an insulative substrate (1), a conductive pad (4a) formed on the substrate, and a metal (3) bonded to the pad via a solder layer (6). The metal piece (3) has a welding portion (3a) to which an external-connection terminal (5) is welded. A gap (7) is provided between the welding portion (3a) and the substrate (1). The welding portion (3a) and the solder layer (6) are separated by the gap (7).

Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Abstract: Interconnect dual damascene structure are fabricated by depositing on a layer of at least one dielectric, a mask forming layer for providing the via-level mask layer of the dual damascene structures; creating an elongated via pattern in the via-level mask layer; depositing a layer of line-level dielectric and creating a line pattern through the layer of line-level dielectric, and transferring the line pattern through the projected intersection of the elongated via-level pattern and of the line-level pattern thereby generating an aligned dual damascene structure. A conductive liner layer is deposited in the dual damascene structure followed by filling the dual damascene structure with a conductive fill metal to form a set of metal lines. The metal and liner layers are planarized.

Abstract: The generator includes: elements (4, 10) for generating a magnetic field in a first direction, a hot source (6) and a cold source (8) creating a temperature gradient (?T) in a second direction substantially perpendicular to the first direction, and at least one element (2; 14) having thermoelectric conversion properties, disposed in a plane substantially perpendicular to the direction of the temperature gradient (?T). The magnetic field generated is a field of traveling waves moving in the second direction. Each element having thermoelectric conversion properties has a continuous form in the plane perpendicular to the second direction.

Abstract: A system for generating electrical power supply signals includes at least one heat engine having a chamber that undergoes heating/cooling cycle and corresponding pressure variations. At least one piezoelectric transducer is deformed in response to the pressure variations of the heat engine. A power converter transforms the electric signals generated in response to deformation of the piezoelectric transducer(s) to a desired electrical power supply signal. The heat engine preferably uses a geothermal source of cold and an ambient source of hot or vice-versa. Hydrogen can be used as a working fluid, and metal hydride material can be used for absorbing and desorbing hydrogen during the cycle of heating and cooling of the heat engine. A phase change material can also be used. The power converter preferably includes an electromechanical battery with a flywheel storing rotational energy and possibly an electrostatic motor that adds rotational energy to the flywheel.

Abstract: It is an object of the present invention to provide a high efficiency hybrid power supply system that permits a power type power supply device such as a capacitor to be utilized effectively, and that makes it possible to even the burden on an energy type power supply device such as a storage cell. A capacitor 21 is connected to system voltage lines 26 and 27 which are connected to a load 30, and a body formed by a serial connection between a large-capacity storage cell 22 and the output terminal of a voltage controller 23 is connected in parallel with this capacitor 21. The voltage Vb of the storage cell 22 is substantially constant. The voltage controller 23 is a DC/DC converter, for example, the output voltage Vv of which is variable. A system controller 25 changes the system voltage Vs by changing the output voltage Vv of the voltage controller 23.

Abstract: A vehicle door control system provides increased usability convenience to users by a function for automatically opening and closing vehicle doors. When a response signal has been continuously received over a predetermined period from a portable device in response to a request signal periodically transmitted from a vehicle unit, it can be inferred that the holder of the portable device has not merely passed by the vehicle but stays in the vicinity of the vehicle with the will to ride in the vehicle. Therefore, vehicle doors having the automatic opening/closing function are unlocked and automatically opened. This eliminates a need for the holder of the portable device to command the operations of unlocking and automatically opening the vehicle doors.

Abstract: A switching mode power supply uses two power source inputs, an alternating current input and a direct current input. A pulse width modulation controller is used to control current from two primary windings of a transformer. The secondary of the transformer has a rectified direct current output. From the direct current output a current/voltage comparator receives a signal across a sensing resistor and through an inverter and in parallel with respect to the direct current output. The current/voltage comparator may communicate through an opto coupler/isolator and then to a pulse width modulation controller. Instructions are received about the voltage and current necessary to be supplied by the direct current output of the power supply from an internal, circuit board mounted selecting network. The selecting network can be resistive, digital, fiber optical, black and white, or color.

Abstract: A system (200) for distributing electrical power, includes: a first high voltage AC power distributing unit (210a) including a first high voltage AC bus (214a-1, 214a-2), which is selectively connected to a first high voltage AC generator (224a), and a first start bus (212a); a second high voltage AC power distributing unit (210b) including a second high voltage AC bus (214b-1, 214b-2),which is selectively connected to a second high voltage AC generator (224b), and a second start bus (212b); a first high voltage DC power distributing unit (240a) including, a first high voltage DC bus (246a), and a second high voltage DC power distributing unit (240b) including a second high voltage DC bus (246b). The first high voltage AC bus (214a-1, 214a-2) is selectively connectable to the second high voltage AC bus (214b-1, 214b-2), such that the system (200) provides redundancy for high voltage power distribution.

Abstract: Regarding output suppression control of a plurality of dispersed power sources linked to a high-voltage-to-low-voltage transformer of a commercial power system, the partiality of the output suppression of a plurality of dispersed power sources is eliminated and, cost increase of the dispersed power sources is prevented. If a voltage at a power receiving point of a dispersed power source 1a exceeds the upper limit of a proper value, then a power conditioner 4 suppresses an output to a power receiving point to store a surplus power into a storage battery 8 and transmit an output suppression start signal to a management unit 9. The management unit 9 transmits an output suppression command signal to the other dispersed power sources 1b through 1e of which the voltage at the power receiving point is not exceeding the upper limit of the proper value to make the other dispersed power sources 1b through 1e to suppress their outputs and store surplus power into storage batteries 8.

Abstract: A method and apparatus provides for high-speed switching of high-voltage and high power MOSFET-based solid state relays. A driver for a MOSFET based, high voltage, high current electronic relay includes a current supply for actuating the switching circuit and a transformer arrangement coupled to the current supply for receiving the supply of current from the current supply. The transformer arrangement is adapted for coupling with the switching circuit for selectively applying a predetermined voltage to the switching circuit which establishes the switching circuit in switch conducting or switch isolation.

Abstract: A semiconductor circuit according to an embodiment of the invention includes: a terminal resistor circuit including a first Pch transistor; and a control circuit for outputting a control signal to a gate terminal of the first Pch transistor to control a resistance value of the terminal resistor circuit, the control circuit including: a second Pch transistor having a resistance value that is changed in the same direction as a resistance value of the second first transistor with respect to a specific parameter; and a resistor having a resistance value that is less changed than the resistance value of the second transistor with respect to the specific parameter, wherein the control circuit outputting the control signal based on a voltage between the second Pch transistor and the resistor.

Abstract: An electronic switching device, which operates without contact, includes a single sensor element (1), a clock generator, which can be provided internally or which can be connected externally, an evaluation circuit (2), and an electronic or electromechanical switch (3), which is provided on an output side. The evaluation circuit (2) includes diversity processing units (4, 5), and a checking unit (6), wherein an output signal of the sensor element (1) is delivered in succession to the processing units (4, 5), and that output signals of the processing units (4, 5) are checked for consistency by the monitoring unit (6). Advantageously, with only a single sensor element (1), category 4 of EN 954-1 or safety level SIL 3 of EN 61508 requirements can be achieved.