Abstract: A system and method for controlling an electronic circuit breaker prevents the circuit breaker from contributing its own delay to a power interruption time window on a load. A monitor coupled to a control processor in the circuit breaker causes the control processor to operate in a low-energy consumption sleep mode if it detects a power interruption. During the sleep mode, the control processor draws current from an energy storage device until the power source is reconnected to the control processor. Because the control processor operation is suspended rather than stopped during the power interruption, the control processor does not need to conduct any preliminary power up operations when power is resumed.

Abstract: An inverter apparatus includes an inverter circuit, a temperature sensor, and a control circuit. The inverter circuit is driven by a PWM signal and includes switching elements that are divided in first and second groups. The temperature sensor detects a temperature of at least one of the switching elements of the first group. The control circuit controls a duty cycle of the PWM signal such that a first value of heat generated in the first group is equal to or greater than a second value of heat generated in the second group. The control circuit performs an overheat protection for protecting the inverter circuit from overheating when the detected temperature is equal to or greater than a threshold temperature.

Abstract: A power supply in which a feed voltage (Us) is guided through at least one longitudinal branch to at least one output, the at least one branch having a disconnect fuse formed as a controlled semiconductor switch (SW1) and a monitoring unit (UWE) being set up to supply a disconnect signal (s1) to the semiconductor switch when there are changes in voltage or current beyond pre-definable tolerances, in which at least one auxiliary semiconductor switch (H1A), likewise triggered by the monitoring unit (UWE), is connected in parallel to the semiconductor switch (SW1) and in the event of an overload absorbs a substantial portion of the overload current in the branch.

Abstract: A metal oxide varistor integrally formed with a heat protection structure that will automatically go to open circuit in conditions of overheating due to sustained over-voltages. The metal oxide varistor integrally formed with a heat protection structure has a body, an insulation bracket, a number of terminals and a fuse. The insulation bracket is deposited on the body and has a number of slots. The fuse connects to the body and one of the terminals. The fuse is mounted one of the slots of the insulation bracket. The fuse reacts to the overheating timely and the melting fuse spreads quickly with the assistance of capillary action evolved by the slots of the insulation bracket to speed up the action to go to open circuit in against damage due to sustained over-voltages.

Abstract: A surface discharge type air cleaning device comprises an insulating dielectric body formed in the shape of a sheet, a discharge electrode having a pattern part of a predetermined area formed on the upper surface of the insulating dielectric body and at least one non-pattern part disposed in the pattern part and a ground electrode formed at the lower surface of the insulating dielectric body. The discharge electrode and the ground electrode have a plurality of pointed ends protruded therefrom, respectively. The pointed ends of the discharge electrode and the pointed ends of the ground electrode are disposed at the upper and lower surfaces of the insulating dielectric body, respectively, such that the pointed ends of the discharge electrode and the pointed ends of the ground electrode correspond to each other. Generation of negative ions and hydroxyl radicals is increased while generation of ozone is decreased, and therefore, air cleaning efficiency is improved.

Abstract: A chip-type aluminum electrolytic capacitor is provided that allows a lead wire exposed from an insulated terminal plate to have an increased temperature sooner than the other parts to provide highly-reliable soldering in a relatively-easy reflow atmosphere environment and that has a superior vibration resistance. The capacitor includes an insulated terminal plate (3) that includes, at the outer surface thereof, an insertion hole (2a) to which a pair of lead wires (2) introduced from a sealing member of a capacitor body are inserted and a first concave groove (2a) for storing lead wires (2) inserted to the hole while lead wires (2) being bent in an orthogonal direction. Insulated terminal plate (3) is attached to the capacitor so as to be abutted with the above sealing member. Metal electrode (4) is buried in an inner face of first concave groove (2a) provided in insulated terminal plate (3) and the periphery thereof.

Abstract: According to an aspect of the present disclosure, an electrical power meter, is disclosed. The electrical power meter includes a housing for containing electrical circuitry therein, the housing including at least one of voltage and current inputs, the housing including passages extending entirely therethrough, wherein the passages are configured to receive a CT lead therethrough, and wherein the CT leads are not electrically connected to the electrical circuitry therein; and a face plate operatively supported on a surface of the housing, wherein the face plate includes at least one of displays, indicators and buttons. It is envisioned that the through passages are located along a side of the housing.

Abstract: Frames suitable for mounting flat panel displays are provided. The frame is adapted to engage and secure a flat panel display. One or more flanges on at least one side of the frame are adapted to attach to sides of an opening within a console. Also provided are methods for mounting a flat panel display in a frame and mounting the display and frame assembly within a console.

Abstract: A method for attaching a flat screen display device onto a flat surface using a surface mounted holder is disclosed. The holder includes a plurality of springy electrical contacts and a plurality of hooks each having a latch. The rear surface of the display device includes corresponding electrical contacts for corresponding with the plurality of springy electrical contacts and sockets each with a convex area corresponding to the hooks each having a latch. The method includes mounting the sockets onto the hooks and pushing the display device toward the flat surface by overcoming a biasing force of the springy contacts; and sliding the display device in a direction opposite to the direction of the hooks until the springy electrical contacts engage the corresponding electrical contacts and every convex area is latched by every latch, and is secured by the biasing force for preventing accidental release of the display device.

Abstract: A multimedia device adapted for use on portable computers is movably mounted on a portable computer which consists of a first member and a second member that are openable and foldable relative to each other. When the portable computer is opened, the multimedia device may be turned to a use position. The multimedia device has a latch member turnable to latch and couple the first and second members in a closed condition when they are moved too close to each other for folding.

Abstract: The present general inventive concept relates to a portable computer including a computer main body, a display main body coupled with the computer main body, a main board provided in the computer main body, a keyboard provided in the computer main body and disposed in parallel with the main board without overlapping with the main board, and an auxiliary memory provided in the computer main body and disposed in parallel with the main board and the keyboard without overlapping with the main board and the keyboard. Thus, the present general inventive concept provides a portable computer having an improved structure to minimize its thickness.

Abstract: Assembly and connection of electronic components are provided. In one embodiment, electronic components such as a CPU planar, power supplies, and other electronic components or subassemblies are positioned within an enclosure. An interface board removably positionable in the enclosure carries a plurality of electronic connectors, providing an electronic interface between the CPU planar, power supplies, and other electronic subassemblies. The interface board is movably mounted to a component module on a track. The component module is inserted in a first bay, with the attached interface board in a first position. The interface board connects to a movable cable plate, and is subsequently moved to a second position along with the connected cable plate to move one or more of the connectors to a second bay. An electronic subassembly positioned in the second bay or another bay may then be connected the interface board. Other electronic components may be connected to the interface board via the cable plate.

Abstract: A mounting apparatus for mounting a data storage device that has a protrusion protruding from a sidewall thereof includes a mounting board, and a bracket. The mounting board includes a depressed portion for holding the data storage device. The depressed portion includes a first side wall. The bracket includes a leg member with an end pivotably mounted to the first side wall of the depressed portion of the mounting board. A first receiving slot for receiving the protrusion of the data storage device is defined in a bottom of the leg member. A drive portion is formed at a side of the receiving slot away from the end of the leg member, for cooperating with a corresponding protrusion of the data storage device when installing the data storage device.

Abstract: A modular transmission interface is provided on a motherboard. The motherboard has a South Bridge and a power transmission port. The transmission interface includes a slot connector and an adaptor board. The slot connector is provided on the motherboard, and is connected to the South Bridge and the power transmission port. The adaptor board has a board body, a mating connector provided on the board body and connected detachably to the slot connector, a hard disk connector provided on the board body and connected to the mating connector, and an optical disk drive connector provided on the board body and connected to the mating connector. A hard disk and an optical disk drive can be connected to the motherboard through the adaptor board, thereby facilitating assembly and maintenance.

Abstract: An attachment mechanism for attaching to a wall a network device for assisting a communication device in communicating on a network includes a heat radiation member, engaged with and supporting a housing of the network device, for radiating heat from the network device, and an attachment member, engaged with the heat radiation member, for attaching to the wall the heat radiation member engaged with the housing.

Abstract: A heat sink pad for notebook computer has a supporting unit and a guiding unit attached to the supporting unit. The supporting unit includes a flat plate which has a supporting portion bending downwardly from an end thereof. A plurality of through hole areas is defined in the flat plate. A guiding rail is formed on a downward surface of the flat plate. The guiding unit includes two casings movably provided on the guiding rail. Each casing defines a slot at a side thereof for corresponding to opposite sides of the flat plate. A fan is placed in each casing. Positions of the guiding units are freely adjusted to be suitable for diverse notebook computers for dissipating heat effectively.

Abstract: A cooling structure of electric devices in a vehicle is structured to hold an inverter (300) downward of a cooling passage (356), and to hold a condenser (200) upward of the cooling passage (356). The heating value generated by the inverter (300) is larger than the heating value generated by the condenser (200).

Abstract: A radial fan includes an integrated circuit which is conductively connected to a printed circuit board to control a motor. The flow of air provided by a cooling impeller is conveyed directly to the integrated circuit to cool the integrated circuit during operation of the radial fan.

Abstract: An apparatus and method to automatically secure a chassis to a rackmount rail. The apparatus includes a pin operably attached to a chassis and an aperture disposed within a rackmount rail to receive the pin. The pin is attached to the chassis such that the pin automatically protrudes from the chassis upon inserting a component into the chassis. The aperture automatically receives the pin to secure the chassis. Removing the component from the chassis automatically disengages the pin from the aperture to release the chassis.

Abstract: A digital electronic apparatus includes a plurality of units and a cable. The plurality of units have metallic housings and are combined such that surfaces of the metallic housings are opposed to each other. The cable is laid on a surface of the metallic housing of at least one of the units. The surface on which the cable is laid is other than the surfaces of the metallic housings that are opposed to each other.

Abstract: A display device is arranged such that a voice device (2) is laminated on a liquid crystal panel (1) so as to be confined in a planar area of the liquid crystal panel (1), and a voice-system circuit block which drives the voice device (2) is formed on the thin film substrate (10) of the liquid crystal panel (1). A signal is inputted into the voice-system circuit block through an FPC (4) which is connected to the thin film substrate (10) and which inputs a video signal, and the signal processed at the voice-system circuit block is conducted through the FPC (4). A connecting terminal part (4a) is provided in a middle portion of the FPC (4) and adhered to an FPC (5). One end of the FPC (5) is connected to the voice device (2). In this way, a multifunctional display device can be achieved at low cost by efficiently using a limited space around the display element without sacrificing the advantages of a lightweight and thin-shaped flat display device.

Abstract: A computer system includes a chassis, a first printed circuit board having a surface facing the cavity and at least one component extending from the surface. The printed circuit board linearly moves between a first position in which the at least one component is at least partially received within the cavity and a second position in which the at least one component is removed from the cavity.

Abstract: A printed wiring board comprises the insulating layer 11 (12); at least one resistance element 311 (312) comprising a metal as a main component has 0.5 to 5 ?m of a roughened surface in an arithmetic means height in the one surface, in ?Z direction, and 5% to 50% of the arithmetic mean height in average thickness, which is embedded close to a surface on one side of the insulating layer 11 and a conductive pattern wired surface is composed of the one surface of the resistance element and the one side of the insulating layer 11; and the conductive pattern 351 (352), arranged on the conductive pattern wired surface, is connected to the terminal of the resistance element 311 (312). With this structure, it is provided the printed wiring board comprising the resistance element having an accurate and stable resistance value in a broader resistance value range.

Abstract: The present invention is to provide a small-sized electronic component module in which RF units of a mobile phone for multi-band and multi-system are integrated at low cost. In the RF module, an RF transceiver LSI, a SAW chip, and chip components are mounted on a module board. The SAW chip is mounted on the module board so that a cavity is formed between itself and the module board, and the SAW chip and other components such as the RF transceiver LSI and the chip components are adhered to the module board at their peripheral portions by a sheet-like sealing material, and they are directly covered with the sheet-like sealing material from outside thereof.

Abstract: According to one embodiment, a printed wiring board includes, a main body including an obverse side with an obverse wiring layer, and a reverse side with a reverse wiring layer first pads provided on the obverse side in a first region defined thereon, and to be connected to terminals arranged on a surface of a first semiconductor chip, second pads provided on the reverse side in a second region defined thereon and overlapping with the first region, and to be connected to terminals arranged on a surface of a second semiconductor chip, and interlayer wiring electrically connecting those of the first pads, which are located in an overlapping region, to those of the second pads which are located in the overlapping region.

Abstract: A protective layer for an electronic device and devices with a protective layer. In one exemplary embodiment, the protective layer includes two different layers which can be etched by the same etchant as which are at least one of optically or RF transparent.

Abstract: A patch panel system including a chassis and a plurality of modules. The chassis includes elongated structures configured to interconnect top, bottom and side portions of the chassis. The elongated structures are also configured to receive and secure a printed circuit board and the plurality of modules to the chassis. The modules include a housing and a module card. The card can include a variety of connections that provide communication to connections located on a back plane of the chassis. The system can include a combination of passive and active modules that are interchangeable to provide a variety of interface configurations.

Abstract: A method and system for housing electronic components includes a chassis having a first sub-chassis slidably dockable into a first end of the chassis. The first sub-chassis houses a first set of electronic components and includes a backplane to electrically couple the first set of electronic components to a second set of electronic components located adjacent to the first sub-chassis. The second set of electronic components is housed in a second sub-chassis, which is accessible via a second end of the chassis. The backplane is accessible by slidably undocking the first sub-chassis without removal of any one of the second set of electronic components. Some of the second set of electronic components are accessible by slidably undocking the first sub-chassis and without removal of the backplane.

Abstract: A module which includes a hermetically sealed housing and a terminal block which is integrated with the hermetically sealed housing to provide electrical connection to external devices.

Abstract: Techniques are disclosed to extend an on time period of switch to regulate a transfer of energy from an input of a power supply to an output of a power supply. One example integrated circuit includes an energy transfer element coupled between an input and an output of the power supply. A switch is coupled to the input of the energy transfer element. A controller is coupled to the switch to control switching of the switch to regulate a transfer of energy from the input of the power supply to the output of the power supply in response to a feedback signal received from the output of the power supply. The controller is coupled to limit a maximum on time period of the switch a first maximum on time period in response to a first range of power supply operating conditions and to a second maximum on time period for a second range of power supply operating conditions.

Abstract: An apparatus and method are disclosed to provide transformerless safety isolation in a power supply. One example regulated power converter includes input terminals included in a primary circuit of the power converter. Output terminals are included in a secondary circuit of the power converter. A plurality of safety capacitors including first and second safety capacitors are also included. Each of the plurality of safety capacitors includes a respective first terminal coupled to the primary circuit and a respective second terminal coupled to the secondary circuit. The plurality of safety capacitors galvanically isolates the primary circuit from the secondary circuit. A power switch is included in the primary circuit. The power switch is coupled such that switching of the power switch causes energy to transfer between the primary and secondary circuits through the plurality of safety capacitors.

Abstract: A step-up power supply unit for providing a multiplicity of different step-up voltages as needed, generated by stepping up a voltage of a single power source such as a battery. The step-up voltage of the last stage charge pump unit and the step-up voltage of at least one charge pump unit other than the last stage charge pump unit, are made available as multiple output voltages. When one or more of the output voltages are not needed, all the charge pump units subsequent to the one providing the highest output voltage are disabled based on an output voltage control signal, thereby minimizing the size and cost of the step-up circuit and reducing the power consumption by the circuit.

Abstract: A hybrid flash memory device includes an array including a first area and a second area having a larger number of stored bits per cell than the first area. The device includes a hidden area including a first reserved block area and a second reserved block area, wherein the first reserved block area includes a plurality of first memory blocks having the same number of stored bits per cell as the first area, the second reserved block area includes a plurality of second memory blocks having the same number of stored bits per cell as the second area, and a flash translation layer configured to replace a bad block generated in the first main area with the first memory block and replace a bad block generated in the second main area with the second memory block, wherein the flash translation layer flexibly assigns functions of the first memory blocks or the second memory blocks depending on whether the first and second memory blocks are all used.

Abstract: The present invention is directed to a dual chip package that is connected to a host and includes a first memory chip and a second memory chip. Each of the first and second memory chips includes a flash memory; an option pad connected to either a first or second voltage; a register configured to store a flag signal indicating whether a memory chip is selected; a comparator circuit configured to compare a flag signal stored in the register with a logic value apparent at the option pad to generate a flash access signal. Each of the first and second memory chips also includes a memory controller unit configured to access the flash memory in response to the flash access signal, and an interrupt controller unit configured to provide an interrupt signal to the host in response to the flash access signal and a control signal provided from the host.

Abstract: An over-driven access method and device for ferroelectric memory. When accessing the data stored in a ferroelectric memory, the invention further provides an over-driven current to slightly reduce/raise the voltages in bit lines BL and BL? to further enlarge the voltage difference therebetween after having raised the plate-line/bit-line voltage using the plate-line/bit-line driven method.

Abstract: A phase change memory cell may be read by driving a current through the cell higher than its threshold current. A voltage derived from the selected column may be utilized to read a selected bit of a phase change memory. The read window or margin may be improved in some embodiments. A refresh cycle may be included at periodic intervals.

Abstract: In a semiconductor memory device and method, phase-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices formed of a phase-change material. Each phase-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of phase-change memory cell groups storing data while being connected to the local bit lines, respectively.

Abstract: A memory cell with at least two detectable states among which is an unprogrammed state, comprising, in series between two terminals of application of a read voltage, at least one first branch comprising: a pre-read stage comprising, in parallel, two switchable resistors having different values with a first predetermined difference; and a programming stage formed of a polysilicon programming resistor, a terminal of the programming resistor being accessible by a programming circuit capable of causing an irreversible decrease in its value.

Abstract: Digital data apparatuses and digital data operational methods are described.

Abstract: An MRAM has a plurality of bit lines, a reference bit line, a plurality of memory cells and reference cells and a read section. The memory cells are provided along the bit lines and the reference cells along the reference bit line. The memory cell and reference cell have a tunneling magnetic resistance and a reference tunneling magnetic resistance, each of which has a spontaneous magnetization whose direction is reversed in accordance with data stored therein. The read section has a first resistance section which contains a ninth terminal connected with a bit line and a tenth terminal connected with the first power supply, a second resistance section which contains an eleventh terminal connected with the reference bit line and a twelfth terminal connected with the first power supply, and a comparing section which compares a sense voltage on the ninth terminal and a reference voltage of the eleventh terminal.

Abstract: A “toggling” type of magnetic random access memory (MRAM) has memory stacks arranged in the X-Y plane on the MRAM substrate with each memory stack having a plurality of toggle memory cells stacked along the Z axis. Each stack is located at an intersection region between the two orthogonal write lines. The cells are stacked in pairs, with the cells in each pair having their easy axes of magnetization aligned substantially parallel to one another and nonparallel with the X and Y axes. The cells in each pair have their free layers magnetically biased in opposite directions. Because the free layer of each cell in a pair is biased in a direction opposite to the bias direction of the free layer of the other cell, one cell in a pair can be toggle written without toggle writing the other cell in the pair. The bias fields on the free layers reduces the required switching field for each cell, which results in less write current and a lower-power toggling MRAM.

Abstract: A magnetic memory 1 having a wire 5 extended in a direction of arbitrary decision, an electro-resistivity effect element 4 disposed adjacently to the wire 5, and a counterelement side yoke 20B disposed adjacently on the side opposite the magneto-resistivity effect element 4 in the wire 5 and having the thickness of the counterelement side yoke 20B so set as to be larger than 50 nm and smaller than 150 nm. Owing to conformity with this invention, this magnetic memory is enabled to homogenize the magnetization property during the course of writing operation and perform the writing work with a low electric current.

Abstract: A phase change memory device is provided which includes a memory cell array including a plurality of memory cells, and a write driver for supplying a program current to the memory cell array through a global bitline. The memory cell array includes first and second cell regions, a first local bitline connected to the first cell region, a second local bitline connected to the second cell region, and a select region disposed between the first and second cell regions and supplying the program current supplied through the global bitline to the first and second local bitlines in response to a local select signal.

Abstract: A memory device is described that provides increased output data to help evaluate data errors from bit line coupling and floating gate coupling during a read operation. Multiple rows, or pages, of data are read to allow an internal or external decoder to evaluate memory cell data.

Abstract: A method is provided for programming a nonvolatile memory device including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window that identifies a plurality of memory cells in the array. A first group of memory cells to be programmed is identified from the plurality of memory cells in the programming window. The first group of memory cells is programmed and a programming state of the first group of memory cells is verified.

Abstract: An improved CMOS high-voltage latch that stores data bits to be written to memory cells of a non-volatile memory is connected to a Vdd supply voltage during a standby mode of operation and during a load-data mode of operation. During a high-voltage write mode of operation, the HV terminal is connected to a HIGH-VOLTAGE supply voltage. A cross-coupled high-voltage CMOS latch is connected between the HV terminal and a ground terminal and has a latch input node B and a latch output node A. An input buffer is connected between the HV terminal and the ground terminal and has an input terminal connected to a DATA INPUT terminal. An output terminal of the input buffer is connected to the latch input node B. The input buffer is enabled during a load-data mode of operation to load data from a DATA INPUT terminal to the latch input node B of the cross-coupled high-voltage CMOS latch.

Abstract: A single 4-transistor non-volatile memory (NVM) cell includes a shared static random access memory cell. The NVM cell utilizes a reverse Fowler-Nordheim tunneling programming technique that, in combination with the shared SRAM cell structure, allows an entire cell array to be programmed at two cycles. A single NVM cell approach with shared SRAM allows a 50% area reduction with an insignificant increase in program time.

Abstract: A nonvolatile semiconductor memory includes a memory cell array and a replacement data cell array. The memory cell array includes a plurality of main cell arrays and a plurality of redundancy cell arrays. The replacement data cell array stores a replacement data indicating a replacement of one main cell array by one redundancy cell array. The replacement data cell array includes a plurality of first storage sections and a plurality of second storage sections. The first storage section corresponds to one redundancy cell array and stores a replacement confirmation data indicating whether or not the corresponding one redundancy cell array replaces one main cell array, by nonvolatile memory cells of two bits. The second storage section corresponds to one redundancy cell array and stores an address data indicating an address for one main cell array which is replaced by the corresponding one redundancy cell array.

Abstract: A data storage system, which includes a plurality of pages, each of which includes a plurality of first memory cells, from which at least binary data can be read-out a plurality of times without destruction; a circuit which receives data-output of at least one first page, detects an error in at least one bit of data, and outputs information of the error position; another circuit which determines whether data of an error bit is “1” or “0”. When the determination is “1” or “0”, the first memory cell of the first page is erased, and error-corrected data is written.

Abstract: A NAND EEPROM having a shielded bit line architecture reduces supply voltage and ground noise resulting from charging or discharging bit lines. The EEPROM has a PMOS pull-up transistor and an NMOS pull down transistor connected to a virtual power node. A control circuit for charging or discharging bit lines controls the gate voltage of the PMOS or NMOS transistor to limit peak current when charging or discharging bit lines via the virtual power node. In particular, the control circuit operates the PMOS or NMOS transistor in a non-saturation mode to limit current. One such control circuit creates a current mirror or applies a reference voltage to control gate voltages. A programming method sets up bit lines by pre-charging unselected bit lines via the PMOS pull-up transistor having controlled gate voltage while latches in the programming circuitry charge or discharge selected bit lines according to respective data bits being stored. Another bit line setup includes two stages.