Abstract: A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.

Abstract: In a non-volatile memory, a selected page on a word line is successively programmed by a series of voltage pulses of a staircase waveform with verifications in between the pulses until the page is verified to a designated pattern. The programming voltage at the time the page is programmed verified will be to estimate the initial value of a starting programming voltage for the page. The estimation is further refined by using the estimate from a first pass in a second pass. Also, when the test is over multiple blocks, sampling of word lines based on similar geometrical locations of the blocks can yield a starting programming voltage optimized for faster programming pages.

Abstract: The present invention relates to a method for programming a memory cell having a determined transconductance curve. The programming of the memory cell comprises a series of programming cycles each comprising a step of verifying the state of the memory cell. According to the present invention, the verify step comprises a first read of the memory cell with a first read voltage greater than a reference threshold voltage, and a second read of the memory cell with a second read voltage lower than or equal to the reference threshold voltage. The memory cell is considered not to be in the programmed state if first- and second-read currents flowing through the memory cell are above determined thresholds, and programming voltage pulses are applied to the memory cell while the latter is not in the programmed state. Application in particular to the programming of Flash memory cells.

Abstract: A nonvolatile semiconductor memory device having a first circuit for selecting one from a plurality of blocks, the first circuit having a plurality of transistors connected to word lines connected to some of the nonvolatile memory cells, and a second circuit for generating a first voltage V1, a second voltage V2 and a third voltage V3 (V3<V2<V1). The first voltage is applied to a source or drain of one of the transistors connected to a selected word line at a timing of programming. The second voltage is applied to sources or drains of some of the transistors connected to non-selected word lines at the timing of programming. The third voltage is applied to a source or a drain of one of the transistors connected to at least one of the non-selected word lines at the timing of programming.

Abstract: Methods and apparatuses are disclosed for programming a page of nonvolatile memory cells across multiple nonvolatile memory cells accessed by multiple word lines.

Abstract: In a non-volatile memory programming scheme where the memory cells are programmed in two or more sequential programming passes, when there is insufficient host data to program at least some of the memory cells during the second pass, some of the memory cells may be programmed to the wrong threshold voltage. This can be prevented by modifying the programming scheme so that this does not occur. In one implementation, this is accomplished by choosing a code scheme, which does not cause the memory cells to be programmed to the wrong threshold voltage during the second programming pass, or by programming the memory cells in accordance with substitute data that would not cause the cells to be programmed to an erroneous state.

Abstract: An electrically erasable charge trap nonvolatile memory cell has an initial threshold voltage, a program voltage that is higher than the initial threshold voltage, and an erase threshold voltage that is lower than the program threshold voltage but is higher than the initial threshold voltage. The programmed electrically erasable charge trap nonvolatile memory cells may be erased by applying an erase voltage for a time interval that is sufficient to lower the threshold voltage the transistor from a program threshold voltage to an erase threshold voltage that is lower than the program threshold voltage, but is higher than the initial threshold voltage. The time interval may be determined by repeatedly performing an endurance test using a time interval that is increased or decreased from an initial time interval, to obtain the time interval that meets an endurance specification, or allows a read to be performed successfully.

Abstract: A non-volatile memory device and programming process is described that increases the programming voltage of successive programming cycles in relation to the percentage of the data bits that failed programming verification during the previous programming cycle and were not correctly programmed into the memory array. This allows for a faster on average program operation and a more accurate match of the subsequent increase in the programming voltage to the non-volatile memory device, the specific region or row being programmed and any changes due to device wear. In one embodiment of the present invention the manufacturing process/design and/or specific memory device is characterized by generating a failed bit percentage to programming voltage increase profile to set the desired programming voltage delta/increase. In another embodiment of the present invention, methods and apparatus are related for the programming of data into non-volatile memory devices and, in particular, NAND and NOR architecture Flash memory.

Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example; which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, the data input buffer is rendered inactive in advance, before the instruction for the write operation is provided, whereby wasteful power consumption is reduced.

Abstract: In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

Abstract: A method of determining an initial state of a reference cell in a fabricated memory array includes performing a first read operation of the reference cell by comparing current through the reference cell with the average current passing through a pair of data cells, and storing the result of the first read operation; inverting the value of one of the pair of the data cells; performing a second read operation of the reference cell, and storing the result of the second read operation; inverting the value of the other of the pair of the data cells; performing a third read operation of the reference cell, and storing the result of the third read operation. A majority compare operation of the results of the first, second and third operations is performed, wherein the result of the majority compare operation is the initial state of the reference cell.

Abstract: A semiconductor device card, such as a memory card for example, includes a semiconductor device, a working voltage indicator, and a working voltage generator. A working voltage indicator is set to indicate a desired level of a working voltage corresponding to the semiconductor device. A working voltage generator generates the working voltage having the desired level and being coupled to the semiconductor device. Thus, the semiconductor device card is easily adaptable to accommodate various working voltages of the semiconductor device.

Abstract: A semiconductor integrated circuit device includes a charge transfer transistor provided between a bit line and a sense amplifier, and a bit line clamp voltage generating circuit which generates bit line clamp voltage to be applied to the gate of the charge transfer transistor. The bit line clamp voltage generating circuit includes a current mirror circuit, a resistive dividing circuit provided between the input stage of the current mirror circuit and a reference potential node, a potential setting circuit provided between the output node of the resistive dividing circuit and the output stage of the current mirror circuit, and an operational amplifier which compares potential of the input stage of the current mirror circuit with reference potential to control the current mirror circuit. The operational amplifier is configured by transistors other than intrinsic transistors. The bit line clamp voltage is derived from the output stage of the current mirror circuit.

Abstract: An Static Random Access Memory (SRAM) device and a method of operating the same. In one embodiment, the SRAM device includes: (1) an SRAM array coupled to row peripheral circuitry by a word line and coupled to column peripheral circuitry by bit lines and (2) an array low voltage control circuitry that provides an enhanced low operating voltage VESS to the SRAM array during at least a portion of an active mode thereof.

Abstract: A buffer control circuit, a semiconductor memory device for a memory module including the buffer control circuit, and a control method of the buffer control circuit, in which power consumption can be reduced. The buffer control circuit includes a first control signal generator that generates an internal buffer control signal in response to write latency signals and internal control signals, and a second control signal generator that generates a buffer control signal in response to the internal buffer control signal and a termination control signal. It is therefore possible to reduce unnecessary power consumption incurred by a data input buffer.

Abstract: A latency signal generating method and a corresponding semiconductor memory device, among other things, are disclosed. Such a method includes: receiving a clock signal for the semiconductor memory device; receiving a mode characterization signal; providing the DQS; and adapting the duration of a preamble state of the DQS according to the mode characterization signal to promote conformance of a strobe state of the DQS with the clock signal.

Abstract: Improved integrated circuits, memory devices, circuitry, and data methods are described that facilitate the adjustment and reconstruction of signal timing of devices by providing for an interface having inputs and/or outputs that are adjustably delayed. This allows embodiments of the present invention to sense the signal delay and utilize adjustable input or output delays to correct the signal timing relationships such that correctly timed communication signals are received by the internal circuitry of the device. In one embodiment of the present invention, a register is utilized to adjust the timing delay of individual input and/or output signals for the device. This increases the robustness of the device and its resistance to communication or data corruption, allowing larger ranges of environmental conditions and input capacitances of systems or communication busses to be tolerated.

Abstract: A method and apparatus for minimizing errors that may occur when writing information to a magnetic memory cell array with an operating write current due to changes in the local magnetic fields and. A test write current is sent to a reference memory cell and the effect of the test current on the orientation of the magnetization in the reference cell is monitored. The write current is then modified to compensate for any changes in the optimum operating point that have occurred. Arrays of reference magnetic memory cells having varying properties may be used to more accurately characterize any changes that have occurred in the operating environment. A phase difference between a time varying current used to drive the reference cell and the corresponding variations in the orientation of the magnetization in the reference cell may also be used to further characterize changes in the operating environment.

Abstract: A DRAM bit line precharge voltage generator comprises a first amplifier having a first current source and comparing a first voltage with a precharge voltage to control a first PMOS transistor, a second amplifier having a second current source and comparing a second voltage with the precharge voltage to control a second PMOS transistor, a third amplifier having a third current source and comparing a third voltage with the precharge voltage to control a first NMOS transistor, and a fourth amplifier having a fourth current source and comparing the first voltage with the precharge voltage to control a second NMOS transistor. The precharge voltage feedbacks from an output node connected between the second PMOS transistor and the first NMOS transistor.

Abstract: A semiconductor memory device includes: a cell array with electrically rewritable and non-volatile memory cells disposed at crossings between bit lines and word lines, which intersect with each other; a row decoder configured to drive the word lines; and a sense amplifier so coupled to a selected bit line as to compare a cell current with a reference current and sense data of a selected memory cell in the cell array, wherein bit line precharge is performed for a certain time prior to the sense amplifier activation in a data read mode while word line boost is performed in advance of the bit line precharge.

Abstract: Exemplary embodiments of the present invention provide a flash memory device which includes a memory cell array. A decoder circuit is connected to the memory cell array via a plurality of select lines and a plurality of word lines. The detector circuit supplies voltages for a read operation to the plurality of select lines and the plurality of word lines during the read operation. A word line discharge unit is connected to the memory cell array via the plurality of word lines. The word line discharge unit discharges a voltage level of a selected word line during the read operation.

Abstract: A memory sense amplifier includes a sample and hold circuit followed by a differential amplifier. The sample and hold circuit samples a reference voltage on a bit line of a memory circuit when the sense amplifier is reset and a signal voltage on the same bit line when a signal representing a data bit is present in the bit line. The differential amplifier amplifies the difference between the signal voltage and the reference voltage.

Abstract: A method and device for hiding refresh operations during accesses to sub-arrays of a pseudo-static memory device. By refreshing sub-arrayj while filling the row Ri (where i?j) corresponding to sub-arrayi, refresh operations can be performed without risking that a read request will interrupt the refresh operation. Additional refresh operations of sub-arrayi can be performed serially with the operations of filling the row Ri without delaying the overall burst read or write operation if the burst is made sufficiently long.

Abstract: A semiconductor memory apparatus which can restrict a refresh operation for a period when an internal clock is synchronized with an external clock. The semiconductor memory apparatus includes a refresh control unit that disables a refresh command signal which is applied during a period when an enable signal is enabled but a lock-completion signal is not enabled in response to the enable signal outputted from a mode register, the lock-completion signal outputted from a clock synchronizing unit, and the refresh command signal outputted from a command decoder. The clock synchronizing unit can stably complete a locking operation within a predetermined time regardless of power-supply noise and so on.

Abstract: A semiconductor memory device includes a memory core circuit having memory cells for storing data, a circuit configured to refresh the memory core circuit at a refresh interval, a temperature detecting unit configured to detect temperature, and a control circuit configured to shorten the refresh interval immediately in response to detection of a predetermined temperature rise by the temperature detecting unit and to elongate the refresh interval after refreshing every one of the memory cells at least once in response to detection of a temperature drop by the temperature detecting unit.

Abstract: An integrated circuit and associated method of programming are provided. Such integrated circuit includes a memory cell with a diode and an antifuse in communication with the diode. The antifuse is constructed to include a high-K dielectric material with a K greater than 3.9. Further, the memory cell is programmed utilizing a programming pulse that reverse biases the diode thereof.

Abstract: A circuit and method efficiently powers a static storage element during a low voltage mode of operation. The static storage element is powered at a first voltage level in an active mode of the static storage element. The static storage element is powered in a low power mode using alternating first and second phases. Powering the static storage element during the first phases in the low power mode includes powering the static storage element at or below a second voltage level, wherein powering the static storage element during the second phases in the low power mode includes powering the static storage element at a higher voltage level than the second voltage level. In another form two modes of low power operation are used where a first mode uses a less power efficient operation than the second mode, but both are more power efficient than a normal power mode.

Abstract: An apparatus for controlling bank of a semiconductor memory includes a plurality of banks, a peripheral circuit unit that generates and outputs a bank selection signal and a first address, and a bank controller that generates a second address obtained by correcting the first address to match a bank control timing and outputs the generated second address to a bank corresponding to the bank selection signal among the plurality of banks. Since it is easy to ensure a timing margin, it is possible to completely prevent an address generation error, minimize a layout area, and reduce current consumption.

Abstract: A dynamic random access memory device includes an array of dynamic random access memory cells subdivided into a group of blocks. Each of the blocks of memory cells can be independently operated in either a single cell mode or a twin cell mode.

Abstract: Asynchronous behavior of a circuit is modeled by modifying latches in a netlist to add an extra port to the latches, e.g., a single-port latch is transformed into a dual-port latch. Each input port has an enable line and a data input. The data input in the added port is a feedback line from the latch output, and the enable line in the added port is the logical NOR of all of the original enable lines. By adding this extra latch port in the higher-level model, it becomes possible to introduce assertion logic to ensure that one and only one latch port for a given latch is ever active during the same simulation cycle. The model can then be tested earlier in the design methodology prior to the availability of the post-synthesis netlist. The model can also be used in both simulation and formal or semi-formal verification.

Abstract: A method for accessing a dual-port memory, wherein a data block programming procedure is performed upon the dual-port memory using status flags and check codes to determine the access sequence of the data so as to enable data exchange between two central processing units (CPU's) to be processed rapidly and correctly without interruption and thus to enhance the performance of the two CPU's.

Abstract: Various aspects of the low cost line buffer system allow a reduction in circuitry versus conventional approaches to line buffer design. A plurality of line buffers such that the output of one line buffer in the plurality of line buffers may be coupled to an input of a succeeding line buffer in the plurality of line buffers. A first line buffer in the plurality of line buffers may be coupled to an input write data signal, while the width of a subsequent plurality of line buffers may be less than or equal to the width of the previous line buffers in the plurality of line buffers.

Abstract: An apparatus for automatically calibrating a transducer are disclosed in the present invention, the apparatus comprising: an oscillator, for generating a system frequency; a micro controller, being coupled to the oscillator, for receiving the system frequency; a counting unit, being installed inside the micro processor, for generating at least a clock signal according to the system frequency; a transformer, whose input terminal is being coupled to the counting unit, for receiving the clock signal and transferring the clock signal to be a plurality of exciting signals, the output terminal feedbacks and couples the exciting signals to the interrupting signal input terminal of the micro controller, wherein the a plurality of exciting signals comprising at least a primary oscillating signal and at least a secondary oscillating signal and the amount of the clock signal equals to that of the primary oscillating signal; and a transducer, whose input terminal is being coupled to the transformer, and the transducer is

Abstract: The invention includes a geographical sensor apparatus for use under water in the sea, including a plurality of seismic sensors (1) for sensing seismic waves associated with underground formations, and a plurality of EM-sensors constituted preferably by electrodes (4) for sensing electromagnetic waves associated with the underground formations. In a preferred receiver cable configuration embodiment of the invention, the geophysical sensor apparatus includes a seismic receiver cable with a linear array of a plurality of seismic sensors (1) and EM-sensors arranged inside a flexible outer skin (25), with the EM-sensors having electrodes on the outside of the outer skin. The cable is operated on the seafloor by a surface vessel, the vessel towing an electromagnetic transmitter antenna in addition to the seismic source.

Abstract: A method of imaging in an underground formation one or more steep-sloping geologic interfaces, which are not necessarily in a plane, by forming with primary reflectors, which are not necessarily in a plane, dihedra giving rise to prismatic seismic reflections (double reflections). The geometry of the steep-sloping interface is determined from choosing seismic records of one or more events corresponding to prismatic reflections for different source-pickup pairs of an acquisition device. A new reflection tomography technique is used, wherein introduction of specific constraints guarantees the convergence of the algorithm. The velocity distribution in the geologic formation and/or the geometry of the interface(s) between the sedimentary layers can be known otherwise or determined by means of the method. The method can apply to a formation comprising several different sloping interfaces.

Abstract: The analysis of scattering diagrams of the correlation-type representation theorem in inhomogeneous media is improved by the use of virtual events. Virtual events here are events which are not directly recorded in standard seismic data acquisition, but the assumption of their existence permits the construction, of internal multiples with scattering points at the sea surface.

Abstract: A method of determining and analyzing spatial changes in the earth's subsurface. The method includes obtaining seismic attribute data as a 3D data volume and obtaining corresponding 3D dip and azimuth as a 3D volume and obtain corresponding 3D reliability volumes or 3D censor volumes which are representative of portions of the volume within in which a reliable dip and azimuth can be determined. A focused subvolume of interest within the 3D data volume is additionally selected. An average for the plurality of vector dips is computed and a flat spot direction vector for each structural dip and a flat spot direction vector dip magnitude is determined. Sequences of distances from each reliability location is defined and interpolated onto the direction of the flat pot direction vector. The sequences of interpolated seismic attribute data is summed and the summed sequences of interpolated seismic attributed data values are stored.

Abstract: A method of determining and analyzing spatial changes in the earth's subsurface. The method includes obtaining seismic attribute data as a 3D data volume and obtaining corresponding 3D dip and azimuth as a 3D volume and obtain corresponding 3D reliability volumes or 3D censor volumes which are representative of portions of the volume within in which a reliable dip and azimuth can be determined. The gradient of the seismic attribute data in the direction of structural dip is formed using either a dot product methodology or a derivative methodology after interpolation onto the direction of structural dip. At non-reliability locations or locations where no gradient could be meaningfully computed null values are stored. High gradient values in narrow time or depth ranges which are both statistically significant relative to a background level and contiguous designate regions likely to be proximal to a fluid contact or seismic flat spot.

Abstract: In one aspect of the invention, a high-speed measurement system has a first and a second well bore. A first and second plurality of network nodes is integrated into and spaced at intervals along the first and second well bore, respectively. A communications channel connects each plurality of network nodes forming a first and second downhole network. A signal source is in communication with the first downhole network and a signal receiver is in communication with the second downhole network; and a common clock source is in communication with both the signal source and the signal receiver over the first and second downhole networks, respectively. The signal source and signal receiver are synchronized with the clock source and the signal source is adapted to send a signal to the signal receiver through a subterranean formation.

Abstract: An exemplary embodiment of the present invention may include a cavitating body sonar system and method.

Abstract: In order to locate electromagnetic or acoustic signal sources of a sensor configuration (1 a through 1 c) fitted with at least two electric outputs; where the incidence-dependent transfer functions between the acoustic signals incident on the input(s) of the sensor configuration (1 a through 1 c) and the electric output signals are different, the ratio (7X through 7XX) of the output signal is formed and the result then is correlated with the previously determined ratio function (11).

Abstract: A noise control system is provided for controlling a noise level around a moveable target. The noise control system has a detecting system configured to detect a location and movement of the target, and a noise cancellation system. The noise cancellation system has a sensor for dynamically sensing noise at the location of the target. The noise cancellation system is configured to be responsive to detection of the location of the target by the detecting system and the sensed noise to provide a noise cancellation wave to a first space at and around the location of the target. The noise cancellation system is further configured to be responsive to detection of the movement of the target by the detecting system and the sensed noise, and to provide a noise cancellation wave to a second space to cover the moving target. The second space is larger than the first space.

Abstract: An inverse flextensional projector exhibits a low frequency flexural mode and a higher frequency “breathing” mode to defeat stealthy targets and to conduct short and long range detection and tracking in littoral waters. The device has much broader bandwidth than conventional flextensional transducers, slotted cylinders and conventional cylinder transducers. The device has a low frequency capability similar to slotted cylinder projectors (SCP) but is broader band and does not suffer from the unsupported gap of SCP projectors. The invention has a more uniform radiation velocity than both SCP and flextensional transducers, making it much less susceptible to cavitation limitations.

Abstract: A method of eliminating home-in noise of an optical disc drive without a home limit switch and using a variable step counter, includes: resetting the variable step counter, which counts steps of a stepping motor of an optical pickup, to zero regardless of a position of the optical pickup, when power is applied to the optical disc drive; driving a servomechanism at the position of the optical pickup and then reading a sub-code value of the optical disc to confirm a current position of the optical pickup; calculating a number of tracks from the current position of the optical pickup to a home position and converting the number of tracks into a step counter value to obtain a step counter value of the home position; and moving the optical pickup to the home position through an access operation. The step counter value of the home position is an integer varying depending on the position of the optical pickup when power is applied.

Abstract: A disk array system having first and second housings and a controller for controlling the first and second housings. Fiber channel hard disk drives are received in the first housing, and serial ATA hard disk drives are received in the second housing. When reading data stored in a serial ATA hard disk drive in the second housing, the controller reads a plurality of pieces of data including the data to be read and parity data for the plurality of pieces of data from all the hard disk drives of an RAID group to which the hard disk drive storing the data to be read belongs. Thus, the controller examines whether the plurality of pieces of data including the data to be read are written in the hard disk drives with erroneous contents or not.

Abstract: A method for dynamically adjusting a header region RF gain of a variable gain amplifier while accessing header regions of a DVD-RAM disc, and apparatus thereof. The method includes the following steps: irradiating a light spot on the DVD-RAM disc with a pickup head; detecting a 4T peak-to-peak level of a RF signal generated by the variable gain amplifier while the light spot is moving within a VFO1 column of a header region of the DVD-RAM disc; comparing the 4T peak-to-peak level with a target level; adjusting a header region RF gain of the variable gain amplifier according to a result of the comparing step.

Abstract: An optical recording and reproducing apparatus and a method for determining a write strategy thereof, includes a pickup part to record record data by irradiating a light on an optical disc, a driving part to operate the pickup part to irradiate the light corresponding to a predetermined optical parameter, an optical parameter variation part to vary the parameter within a predetermined variation range by a certain unit and to output the parameter to the driving part, a parameter determination factor measurement part to measure a parameter determination factor based on signals output from the pickup part, and a control part to determine a middle point between a maximum point and a minimum point of the optical parameter, within a range where the measured parameter determination factor does not exceed a reference value, as a final parameter. Accordingly, an optimal write strategy, in which the optical determination factor does not exceed the reference value, may be determined.

Abstract: A method for optical shape recording and/or evaluation of optically smooth, glossy or optically rough surfaces wherein a photometric stereo method and a deflectometric method are combined using a scattering body so that the positions on the scattering body surface are two-dimensionally encoded.

Abstract: A disc having an updatable defect management area used by an apparatus for managing defects on the disc, the disc including a user data area which includes user data, a spare area that is a substitute area for a defect existing in the user data area, and an area in which are recorded an address of data that is last recorded in the user data area and an address of a replacement data recorded in the spare area. Accordingly, the disc defect management method and apparatus are applicable to a recordable disc such as a write-once disc while effectively using a defect management area of the disc.

Abstract: With an object of executing excellent finishing processing when information is recorded to a rewritable type record medium or a write once type record medium, the finishing processing is switched by whether a kind of a medium for recording information is the rewritable type record medium or the write once type record medium and a method of executing the finishing processing is switched based on a state of supplying power.