Abstract: A passive mixer include a switching architecture configured to generate differential in-phase (I) and differential quadrature-phase (Q) signals using differential components of the in-phase (I) and quadrature-phase (Q) signals operating on transitions of an approximate 25% duty cycle signal.

Abstract: A subharmonic mixer circuit having an input stage (52) and a current modulating stage (64) is disclosed. The input stage (52) receives an RF input signal (RF+, RF?) at a first frequency and generates output currents (i1, i2) varying in dependence upon the Rf input signal. The current modulating stage (64) comprises a first transistor (Q3) for receiving a first local oscillator signal (LOO) respective and a second transistor (Q4) for receiving a second local oscillator signal (LOI 80), 180 degrees out of phase with the first local oscillator signal, such that a modulating current signal (i0), having twice the local oscillator frequency, is superimposed onto the output currents.

Abstract: A transconductor. The transconductor comprises first and second active device networks. The first active device network has a first node and a second node and comprises a first MOS transistor having a gate, a source coupled to the first node, and a drain coupled to the second node. The second active device network has a first node and a second node respectively connected to the first and second nodes of the first active device network and comprises a second MOS transistor and a voltage drop generator. The second MOS transistor has a gate and a source respectively connected to the gate and the source of the first MOS transistor. The voltage drop generator is coupled between a drain of the second MOS transistor and the second nodes of the first and second active device networks and generates a voltage drop across the same.

Abstract: A method of compensating a monolithic integrated operational amplifier against process and temperature variations, such that the operational amplifier is suitable for use in an active filter, the method comprising a providing an amplifier having a first stage and an output stage, wherein the output stage drives an RC load, and wherein a compensation capacitor at an output of the first stage is selected so as to scale with the capacitance C of the RC load, and a transconductance of the first stage is a function of the resistance R of the RC load.

Abstract: An integrated circuit (10) comprises a plurality of functional blocks (101, 102, 103), each of the functional blocks (101, 102, 103) being coupled between a first power supply line (110) and a second power supply line (120). A first functional block (101) is coupled to the first power supply line (110) via a first conductive path including a first switch (131) and a second functional block (102) is coupled to the first power supply line (110) via a second conductive path including a second switch (132), the first switch (131) and the second switch (132) being arranged to respectively disconnect the first functional block (101) and the second functional block (102) from the first power supply line (110) for switching said functional blocks (101; 102) from an active mode to a standby mode.

Abstract: Disclosed is a voltage switch circuit of a semiconductor device. The subject voltage switch circuit can be used to apply voltage to a semiconductor memory device control circuit. The voltage switch circuit according to an embodiment includes five transistors and a capacitor. An output terminal of the subject circuit outputs VSS when VDD is applied to an input terminal, and outputs a boosted operating voltage when VSS is applied to the input terminal.

Abstract: A proportional to absolute temperature (PTAT) current generation circuit may include a current mirror unit and/or a level control unit. The current mirror unit may be connected between a first power supply voltage, a first node, and/or a second node. The level control unit may be connected between the first node, the second node, and/or a second power supply voltage. The level control unit may be configured to control a level of an output current of the current mirror unit based on a voltage level of the first node and a voltage level of the second node. The level control unit may include a first transistor connected between the first node and the second power supply voltage, at least one second transistor connected between the second node and a third node, the at least one second transistor configured to operate in a weak inversion region, and/or a third transistor connected between the third node and the second power supply voltage.

Abstract: A fuse device includes a plurality of serially connected fuse elements whose number is n (n is an integer of two or more), a power source connected to one end of a first fuse element that is a top of the n serially connected fuse elements, and a plurality of program control transistors. Each of the program control transistors is connected to each of nodes between the fuse elements, and to an end of the n-th fuse element, respectively.

Abstract: A capacitor circuit includes a first capacitor having a positive terminal coupled to a first node and a negative terminal coupled to a second node, a second capacitor having a negative terminal coupled to the first node and a positive terminal coupled to the second node, a third capacitor having a positive terminal coupled to the first node and a negative terminal coupled to a third node, a fourth capacitor having a negative terminal coupled to the first node, and a positive terminal coupled to the third node, a first voltage drop generator coupled between the second node and a fourth node for providing a first voltage drop between the second node and the fourth node, and a second voltage drop generator coupled between the fourth node and the third node for providing a second voltage drop between the fourth node and the third node.

Abstract: An internal voltage generation circuit of a semiconductor device includes: a voltage detecting unit configured to detect a voltage level of an internal voltage output terminal to output a voltage detection signal; an oscillating unit configured to generate a first oscillation signal having a predefined frequency in response to the voltage detection signal; and a pumping unit configured to perform a charge pumping operation in response to the first oscillation signal and the voltage detection signal to output an internal voltage to the internal voltage output terminal, a period of the charge pumping operation being limited within an activation period of the voltage detection signal.

Abstract: A voltage generator that prevents latch-up includes: a charge pump circuit that is controlled by first through third enable signals, boosts an internal power voltage generated from an external power voltage, and generates first through fourth voltages; a detector that detects the first through third voltages and generates first through third flag signals that go logic high when the first through third voltages reach predetermined respective voltage levels and maintain logic low when the voltages do not reach the predetermined respective voltage levels; and a charge pump controller that receives the first through third flag signals, and generates the first through third enable signals to have the first through fourth voltages sequentially generated. The voltage generator can prevent latch-up that may occur in a boosting mode or in a normal operation mode.

Abstract: This invention discloses charge pump apparati, where a charge pump apparatus, including a positive charge pump circuit and a negative charge pump circuit, providing multiple positive and negative voltages, comprises: a capacitor set shared by said positive charge pump circuit and said negative charge pump circuit; multiple electronic switches connected to said capacitor set and a plurality of voltage sources; multiple output capacitors connected to selected ones of said multiple electronic switches and one or more output terminals; and a non-overlapping time sequence that controls the on and off states of said multiple electronic switches; wherein under the control of said non-overlapping time sequence, corresponding electronic switches are turned on and off to control the output of the positive and negative voltages provided by said output capacitors to generate output voltages that are pre-determined multiples of the one or more input voltages.

Abstract: An exponential charge pump uses a number of identical or similar charging stages, each having a first and second capacitor. During a first clock phase, the first capacitor of each stage is charged by the second capacitor of the preceding stage, and, during a complementary second clock phase, the positive plate of the first capacitor of each stage is pushed to an increased voltage by the first capacitor of the preceding stage and charges the second capacitor of the next stage to the increased voltage at the same time. A similar mechanism occurs to the second capacitors in each stage, but with complementary timing. The increased voltage of the first capacitor of the last stage is pumped to an output capacitor during the second clock phase, and the increased voltage of the second capacitor of the last stage is pumped to an output capacitor during the first clock phase.

Abstract: In a load-drive controller, a first comparing unit compares a load current supplied from an H bridge circuit and a desired setting current; a PWM control unit generates a control signal to control the load current; a gate driver drives and controls output transistors of the H bridge circuit based on the control signal, and a load current monitoring unit determines which is larger a level shift equivalent value of the setting current or a peak hold equivalent value of the load current, and the PWM control unit controls increase or decrease of the load current based on a comparison result of the first comparing unit and on a determination result of the load current monitoring unit, so that the load current quickly reaches the setting current of a micro step drive during decrease of the setting current.

Abstract: A reference bias circuit is provided. The reference bias circuit includes a voltage detector, an operational amplifier, a compensation circuit, and a reference current generator. The voltage detector detects a first input voltage and a second input voltage of the operational amplifier based on a voltage of a first node and a voltage of a second node. The voltage of the first and second nodes varies with temperature, which changes the first input voltage and the second input voltage and thus changes the output voltage of the operational amplifier. The compensation circuit compensates for the variation of the voltage of the first and second nodes caused by temperature and/or process variation, thereby preventing the variation of a reference current generated by the reference current generator based on the output voltage of the operational amplifier.

Abstract: A current biasing circuit is provided, which is designed to suppress reference current drift caused by temperature variation with a low overall temperature coefficient of a constant-voltage circuit and at least one resistor. The constant-voltage circuit comprises a diode and/or a diode-connected transistor. This current biasing circuit is based on a current mirror architecture, is easy to implement, and is a relatively temperature-independent current source.

Abstract: The present invention discloses a charge pump start up circuit comprising: a start up transistor having one end which is electrically connected with a voltage supply source, and another end which is electrically connected to a voltage node; and a charge pump circuit having an input which is electrically connected with the voltage node, and an output which is electrically with the gate of the start up transistor.

Abstract: This device has a first circuit including a first field effect transistor and a second circuit coupled to a source of the first electric field transistor. The second circuit applies a first source bias voltage, which does not reversely bias between a source and a body of the first field effect transistor, to the first field effect transistor during the operation mode of the first circuit, and applies a second source bias voltage, which reversely biases between the source and the body of the first field effect transistor, to the first field effect transistor during the standby mode of the first circuit. During the standby mode of the first circuit, the leakage current that flows through the first FET is reduced by means of the reverse bias effect produced by applying the second source bias voltage to the source of the first FET.

Abstract: An object of the present invention is to provide a filter circuit which improves NF of a Gm-C filter. The filter circuit comprises a filter comprising at least one first operational transconductance amplifier whose mutual conductance varies depending on a first control signal and a first capacitor, a second operational transconductance amplifier whose mutual conductance is controlled by the first control signal, a third operational transconductance amplifier whose mutual conductance is controlled by a second control signal, and a second capacitor connected to output terminals of the first and second operational transconductance amplifiers and input terminals of the filter.

Abstract: A system for driving an electromagnetic field generator. In one aspect, the system may include a plurality of transistors arranged in an H-bridge configuration, the H-bridge having first and second output terminals, first and second switching inputs, and a power input. The system may further include a control transistor coupling the power input to a power supply, and a diode having a cathode coupled to the power input and an anode coupled to ground. The first and second output terminals may be coupled to the electromagnetic field generator and the first and second switching inputs may receive switching signals based on an output of the electromagnetic field generator.

Abstract: An embodiment is directed to an instrumentation amplifier. The instrumentation amplifier includes an output stage for generating an output voltage, a low-frequency path coupled with the output stage, and a high-frequency path coupled with the output stage. The high-frequency path dominates the low-frequency path at frequencies above a particular frequency, and the low-frequency path dominates the high-frequency path at frequencies below the particular frequency. The low-frequency path includes an input stage for sensing a differential input and generating an intermediate current based thereon, a feedback stage coupled with the input and output stages, the feedback stage for generating a feedback current based on the output voltage, and an auto-zeroing circuit coupled with the input, feedback, and output stages, the auto-zeroing circuit for generating a nulling current.

Abstract: Output circuits using pulse width modulation (PWM) and/or pulse density modulation (PDM) are described. In one aspect, a PWM output circuit includes a PWM modulator that operates based on a square wave signal instead of a sawtooth or triangular wave signal. In another aspect, a PDM output circuit includes a PDM modulator that uses variable reference voltages to reduce variations in switching frequency. In yet another aspect, a dual-mode output circuit supports both PWM and PDM and includes a pulse modulator and a class D amplifier. The pulse modulator performs PWM on an input signal if a PWM mode is selected and performs PDM on the input signal if a PDM mode is selected. The class D amplifier receives a driver signal from the pulse modulator and generates an output signal.

Abstract: A power amplifier using N-way Doherty structure for extending the efficiency region over the high peak-to-average power ratio of the multiplexing modulated signals such as wideband code division multiple access and orthogonal frequency division multiplexing is disclosed. In an embodiment, the present invention uses a dual-feed distributed structure to an N-way Doherty amplifier to improve the isolation between at least one main amplifier and at least one peaking amplifier and, and also to improve both gain and efficiency performance at high output back-off power. Hybrid couplers can be used at either or both of the input and output. In at least some implementations, circuit space is also conserved due to the integration of amplification, power splitting and combining.

Abstract: A power amplifier controller for adjusting a supply voltage to a power amplifier. The power amplifier controller adjusts the supply voltage so that distortion in an RF output signal corresponds to a predetermined limit. An amplitude error signal is generated by the power amplifier controller which represents a difference between an RF output signal and an attenuated RF output signal. The AC components of the amplitude error signal are processed to generate a deviation signal that represents the distortion in the RF output signal. The supply voltage to the power amplifier is increased when the deviation signal exceeds a distortion level control signal, and decreased when the deviation signal drops below the distortion level control signal.

Abstract: Devices (1) comprising switching amplifiers (2,3) such as class D amplifiers and comprising loads (4) such as loud speakers are provided with controllers (2) for controlling switching circuits (3) for in respective four states introducing respective four voltage signals across the loads (4), which four voltage signals are different from each other. As a result, the switching power in the high frequency domain, which switching power is dissipated in the loads (4), is reduced. The total power consumption is reduced, which results in a longer playing time per battery. The controllers (2) control the switching circuits (3) for pulse width modulating the voltage signals in dependence of input signals and control the switching circuits (3) for in fifth states introducing fifth voltage signals across the loads (4), to further reduce the switching power and the dissipation in the loads (4) and the total power consumption and to further increase the playing time per battery.

Abstract: A method and apparatus is provided for use in power amplifiers for reducing the peak voltage that transistors are subjected to. A power amplifier is provided with first and second switching devices and an inductor connected between the switching devices. The switching devices are driven such that the switching devices are turned on and off during the same time intervals.

Abstract: A fully differential amplifier includes: an N-stage amplifier including first to Nth amplifier stages, where N is a positive integer greater than or equal to 2, the first to Nth amplifier stages being cascaded in sequence so as to generate a pair of differential output voltages; a common mode feedback circuit coupled to the N-stage amplifier, detecting a common mode level of the differential output voltages, and controlling the first amplifier stage according to the common mode level detected thereby; and a common mode frequency compensation circuit including a pair of capacitors, each having a first terminal coupled to the N-stage amplifier to receive a respective one of the differential output voltages, and a second terminal coupled to a common mode node of the first to (N-1)th amplifier stages of the N-stage amplifier.

Abstract: A circuit and method for amplifying a differential input signal over a wide dynamic range using multiple signal gains such that, over a predetermined range of values of the differential input signal, a ratio of the differential output signal to the differential input signal varies in relation to a continuous combination of the multiple signal gains.

Abstract: A circuit capable of quiescent current control, the circuit comprising a first operational transconductance amplifier (OTA) including a first output terminal, a first transistor including a first gate coupled to the first output terminal of the first OTA, a second OTA including a second output terminal, a second transistor including a second gate coupled to the second output terminal of the second OTA, a resistive load including a first terminal coupled to the first output terminal and the first gate, and a second terminal coupled to the second terminal and the second gate, a first current source capable of providing a first current flowing toward the first terminal of the resistive load, and a second current source capable of providing a second current flowing away from the second terminal of the resistive load.

Abstract: A low noise amplifier (LNA) comprises: a plurality of FETs (F1, F2, F3, F4) arranged to process signals received by the amplifier; a power input (10) arranged to receive electrical power to operate the LNA; and a monolithic support integrated circuit (IC). The monolithic support IC comprises: a FET control circuit (2) arranged to monitor and control the drain current of each FET; a FET selection circuit (3, 24, 22) arranged to detect the level of a DC component of a voltage signal supplied to the power input and to provide a FET selection signal to the FET control circuit (2) according to the detected DC level.

Abstract: A method of varying the gain of an amplifier and an amplifier array are provided. The amplifier array includes two or more amplifier stages (201, 202) connected in parallel with each amplifier stage having a gain control means. Input signal means (203, 204) are provided for each amplifier stage with the input signals of the amplifier stages being of different amplitude. Means for enabling and disabling an amplifier stage (216) are provided and means for summing the outputs of the enabled amplifier stages obtain an output signal (212).

Abstract: An overdrive control system includes a voltage controlled current source to deliver a compensation current, and being between a first voltage reference and an internal node, which is connected to an output terminal. The voltage controlled current source has a control terminal connected to an output terminal of an adding block, which has a positive input connected to an input terminal. At least one clamping block is between the output terminal and a second voltage reference, and is connected to a negative input of the adding block. The voltage controlled current source delivers its compensation current to the output terminal when a voltage signal on the input terminal has an higher value than a voltage signal on the output terminal, and forces an output voltage signal to follow an input voltage signal to an extent that depends on a clamping voltage provided by the clamping block.

Abstract: A power added efficiency optimizer apparatus is provided for measuring and monitoring input and output power of an amplifying device, and adjusting the load impedance seen by the amplifying device so that power added efficiency is maintained at optimum levels. A power added efficiency optimizing device includes a variable load impedance that can be controlled, at least one power detection device located after the load, a difference forming apparatus, and at least one coupling device. The power added efficiency optimizing device provides an ability to maintain an amplifier at peak efficiency in a dynamic way and in the presence of changing electromagnetic load conditions.

Abstract: A system for detecting power output of a power amplifier includes a first power detector configured to detect a forward power output of a power amplifier, the first power detector configured to provide a first power detector output, and a second power detector configured to receive a collector parameter signal and detect a collector parameter therefrom, the second power detector also configured to provide a second power detector output.

Abstract: An electronic signal processor for processing signals includes a complex first filter, one or more gain stages and a second filter. The first filter is characterized by a frequency response curve that includes multiple corner frequencies, with some corner frequencies being user selectable. The first filter also has at least two user-preset gain levels which may be alternately selected by a switch. Lower frequency signals are processed by the first filter with at least 12 db/octave slope, and preferably with 18 db/octave slope to minimize intermodulation distortion products by subsequent amplification in the gain stages. A second filter provides further filtering and amplitude control. The signal processor is particularly suited for processing audio frequency signals.

Abstract: A linear transimpedance amplifier includes a forward transimpedance circuit that receives an input signal from an optical device. The forward transimpedance circuit generates a linear output signal. The forward transimpedance circuit includes a first gain path and a second gain path, the first gain path configured to amplify the input signal when the first gain path is at a lower input impedance relative to the second gain path and the second gain path configured to amplify the input signal when the second gain path is at a lower input impedance relative to the first gain path. A feedback circuit includes a first circuit that detects a low frequency component of the output signal.

Abstract: An oscillator device includes an oscillation system having an oscillator and an elastic supporting member, a detecting member for detecting oscillation amplitude of the oscillator, a driving member for driving the oscillator, and a control unit for generating a driving signal for driving the oscillator and for supplying the driving signal to the driving member, wherein the control unit reciprocally sweeps a driving frequency of the driving signal so that a resonance frequency of the oscillation system is included within a frequency range swept, wherein the control unit determines a resonance frequency based on at least two frequencies with which an oscillation amplitude value obtainable by the reciprocal sweeping reaches a maximum, and wherein the control unit generates the driving signal based on the determined resonance frequency.

Abstract: Embodiments of present invention provide a circuit including a voltage regulator, a phase frequency detector, a charge pump, a low pass filter a control-voltage generating circuit and a voltage controlled oscillator. In a first mode of operation the voltage controlled oscillator produces an output clock in accordance with a control voltage produced from the control-voltage generating circuit and the output voltage of the voltage regulator. In a second mode of operation, the voltage controlled oscillator produces an output clock in accordance with a control voltage from the low pass filter and the output voltage of the voltage regulator.

Abstract: A frequency synthesizer is disclosed. According to one embodiment, the frequency synthesizer includes an input terminal and an output terminal, a loop filter, a digital phase detector, and an analog phase detector. The digital phase detector includes a first input coupled to the input terminal, a second input coupled to the output terminal, and an output coupled to the loop filter, the digital phase detector configured to operate at a first phase comparison frequency. The analog phase detector included a first input coupled to the input terminal, a second input coupled to the output terminal, and an output alternating current (AC) coupled to the loop filter, the analog phase detector configured to operate at a second phase comparison frequency. The first phase comparison frequency is different from the second phase comparison frequency.

Abstract: A tuning circuit and a method for setting its tuning voltage. The tuning circuit has a phase frequency detector coupled to a loop filter which is coupled to a voltage controlled oscillator. An output terminal of the voltage controlled oscillator is coupled to an input terminal of the phase frequency detector to form a feedback loop. A state machine is coupled between the phase frequency detector and the voltage controlled oscillator. A switch is coupled between an output terminal of the state machine and the input terminal to the loop filter or between the output terminal of the state machine and the input terminal of the voltage controlled oscillator. Alternatively, a comparator is coupled between an input terminal of the state machine and the output terminal to the loop filter or between the input terminal of the state machine and the output terminal of the phase frequency detector.

Abstract: A phase locked loop can reduce a locking time, thereby efficiently reducing power in a locking operation. The phase locked loop includes a phase detector, a control voltage generator, a voltage controlled oscillator and a start-up driver. The phase detector detects a phase difference between a reference clock and a feedback clock to generate a detection signal corresponding to the detected phase difference. The control voltage generator generates a control voltage having a voltage level corresponding to the detection signal. The voltage controlled oscillator generates an internal clock having a frequency corresponding to a voltage level of the control voltage. The start-up driver drives a control voltage terminal to a predefined start-up level in response to a start-up level multiplex signal corresponding to a frequency of the reference clock prior to activation of the voltage controlled oscillator.

Abstract: Disclosed is a resonator including a plurality of resonator elements each including at least oscillation parts and lower electrodes with an intervening space therebetween, in which the plurality of resonator elements are disposed in a closed system and the oscillation parts of the plurality of resonator elements are continuously formed in an integrated manner.

Abstract: The present invention relates to a ring oscillator including a delay stage, the delay stage includes a differential pair of input transistor, a variable resistive load coupled to the transistor, a differential output between the variable resistive load and the corresponding input transistor, a variable current source coupled to the differential pair of transistors for variably setting a bias current through the differential pair of transistors, and an input coupled to the variable resistive load and the variable current source for receiving an configuration signal, wherein the variable resistive load and the variable current source are changed in response to the configuration signal, wherein the bias current of the variable current source increases and the variable resistive load decreases, and vice versa.

Abstract: A phase noise minimization circuit is disclosed, to be used in a voltage-controlled oscillator (VCO) circuit embedded in a feedback system. The phase noise minimization circuit includes a noise power meter to analyze the control voltage fed into the VCO by the feedback system and determine its voltage noise power. Since the VCO is controlled by the feedback system, the control voltage noise power is also an indication of the VCO phase noise power for frequencies offset within the bandwidth of the feedback system. The VCO has several parameters that can be adjusted to affect its phase noise. A minimization algorithm generates the optimum set of parameters that minimize the control voltage noise power (and thus the VCO phase noise power), and sends them to the oscillator. The phase noise minimization circuit may be used in a variety of applications, particularly in phase-locked loop and frequency-locked loop VCOs.

Abstract: A fractional-N synthesized chirp generator includes a fractional-N synthesizer and a digital ramp synthesizer. The fractional-N synthesizer has a frequency synthesizer and a sigma-delta modulator module. The fractional-N synthesizer is configured to receive a reference frequency input signal and a frequency control value. The fractional-N synthesizer is configured to transform the reference frequency signal and the frequency control value to a chirped radio frequency (RF) output signal in a deterministic manner. The digital ramp synthesizer is configured to receive the reference frequency input signal and configured to generate the frequency control value utilizing the reference frequency input signal. The digital ramp synthesizer is further configured to provide the frequency control value to the fractional-N synthesizer. The frequency control value varies with time.

Abstract: An integrated temperature-compensated RC oscillator circuit includes an inverter having an input and an output. An RC network is coupled between the inverter and a pair of comparators. A first comparator has an inverting input coupled to a first reference voltage, a non-inverting input coupled to the RC network, and an output. A second comparator has an inverting input coupled to the RC network, a non-inverting input coupled to a second reference voltage, and an output. A set-reset flip-flop has a set input coupled to the output of the first comparator, a reset input coupled to the output of the second comparator, and an output coupled to the input of the inverter. Differential amplifiers in the comparators each have a diode-connected p-channel MOS transistor controlling a mirrored p-channel MOS transistor whose channel width is less than that of the diode-connected p-channel current mirror transistor.

Abstract: An electrical oscillator circuit comprising: a resonator comprised in the first subcircuit; and an active device comprised in the second subcircuit connected to energize the resonator to provide an oscillating electrical signal transmitted as a differential signal via electrical conductors to the second subcircuit. The oscillator is characterized in that the second subcircuit comprises means for receiving the differential signal transmitted via the electrical conductors and converting the differential signal to a single-ended signal with reference to the signal ground reference of the second subcircuit. Thereby a noise robust oscillator signal is provided with the use of very few components. Particularly suitable for oscillators embodied in an integrated circuit with the resonator mounted on a printed circuit board, PCB. And an integrated circuit.

Abstract: An oscillator is provided that includes a plurality of excitation units for providing an excitation signal and a tank as an oscillation generating unit for generating an oscillation signal in response to the excitation signal, whereby the tank has terminals for providing the oscillator signal, whereby each excitation unit has at least one inductor, whereby the tank is coupled magnetically to the at least one inductor of each excitation unit, and whereby the excitation signal can be transmitted between the excitation units and the tank by means of the magnetic coupling.

Abstract: The present invention relates to a two-level mounting board in which a second substrate is supported horizontally by a metal pin above a first substrate having a mounting electrode on an outer base surface, the free, lower end of the metal pin is inserted in a hole provided in the surface of the first substrate, and the metal pin is affixed by solder to an annular electrode land provided on the surface of the first substrate to form an outer periphery of the hole, wherein part of the ring of the annular electrode land is cut away to open the same. This provides a two-level mounting board in which metal pins can be connected reliably to the first substrate to support the second substrate horizontally, and a crystal oscillator using the same.

Abstract: A dual mode power amplifier can include a linear gain section and a non-linear gain section configured together as a polar amplifier. The dual mode power amplifier may be used to transmit GFSK, 4-DPSK, and 8-DPSK modulated data. In one mode, both non-linear and linear gain sections may be used to transmit 4-DPSK and 8-DPSK modulated data. Alternatively, in another mode, the linear gain section may be bypassed while the non-linear gain section may be used to transmit GFSK modulated data. By selecting the operating mode, the dual mode power amplifier may be advantageously configured to use relatively less power while supporting GFSK, 4-DPSK, and 8-DPSK modulation schemes.