Abstract: A phantom for Diffusion Tensor Imaging (DTI) to measure the main physical quantities of diffusion tensors, such as diffusion anisotrophy, a diffusion principal axis and a route of the diffusion principal axis, and to evaluate the accuracy of DTI are provided. The phantom for diffusion tensor imaging includes: an outer container providing a space; materials for diffusion measurement located in the space of the outer container and formed of bunches of microtubes; and materials for fixing located in the space of the outer container to fix the materials for diffusion measurement to a specific location.

Abstract: A magnetic resonance imaging apparatus includes a bed, a static field magnet, a gradient coil, a liner and a heat transfer material. The bed includes a table-top capable of placing thereon an object. The static field magnet generates a static magnetic field. The gradient coil, formed inside the static field magnet, generates gradient magnetic fields. The liner, provided inside the gradient coil, forms a bore in which the table-top is advanced or retreated. Further, the heat transfer material is attached to the liner.

Abstract: A system and method are provided for adjusting RF pulses and gradient waveforms to reduce B1 field magnitude in MR imaging sequences. When an RF pulse is presented which has a high amplitude segment that would exceed a maximum B1 magnitude, the system and method provided herein can apply a variable slew rate design technique. A slew rate of at least one gradient waveform can be varied to reduce a B1 field magnitude during transmission of the high amplitude segment of the RF pulse. By controlling the slew rate of gradient waveforms for non-Cartesian k-space trajectories according to a calculated maximum allowable slew rate function, embodiments of the system and method can, in effect, reduce gradient amplitude.

Abstract: An apparatus for making azimuthally sensitive resistivity measurements of a subterranean formation is disclosed. The apparatus includes a magnetically permeably ring deployed about an electrically conductive tool body. An AC voltage supply is coupled to the tool body on opposing sides of the magnetically permeable ring, with at least one connecting conductor crossing outside the ring.

Abstract: The present invention, in various embodiments, is directed to a geophysical system and method in which a transmitter coil is oriented with its axis horizontally, and a sensor is positioned below the coil to measure an ambient electrical and/or magnetic parameter associated with a conductive medium surrounding the at least one transmitter coil.

Abstract: Control of delivery of current through one or more discharge lamps. Methods include alternately switching on and off switching elements that control a fluorescent lamp, in response to receiving input, until the brightness of the lamp decreases to a threshold. Further, methods include providing control signals at complementary duty cycles to further decrease the brightness and alternating the duty cycles of the signals applied to the filaments of the fluorescent lamp.

Abstract: A method providing comprehensive information about the properties of a type of electrochemical batteries at all stages of batteries resource exhaustion at their utilization which (properties) are connected with the action of the corresponding (for this utilization) influence on the batteries is realized through acquisition of the experimental data that contains the comprehensive information about these properties, creation of the known and new relevant quantities (on the basis of the acquired experimental data and some relevant parameters of the batteries) that characterize these properties, and study of the functional behavior of the created relevant quantities.

Abstract: A method and a current operational module for on-line measurement of battery internal resistance and an on-line measurement instrument for battery internal resistance have high measurement accuracy and strong anti-interference ability. The on-line measurement instrument for battery internal resistance comprises a current work module, a voltage measurement module, an analog to digital conversion module, a signal generation module, a centre processing module, an Input/Output module, and a power supply module used for on-line measurement of battery internal resistance.

Abstract: A potential measurement apparatus is provided which can suitably maintain the oscillation state of an oscillator including a detection electrode and stably measure the potential of a measurement object. The potential measurement apparatus includes a bearing part, an elastic supporting part supported by the bearing part, an oscillator movably supported by the elastic supporting part, detection electrodes installed in the oscillator, a drive mechanism driving the oscillator and a signal detection unit. The signal detection unit is connected to the detection electrodes to detect electrical signals appearing in the detected electrodes. A stress detecting element for generating an electric signal according to the stress of the elastic suspension part 142 is provided.

Abstract: A method for determining field intensity for a particle on a substrate, the method comprising providing an incident wave, determining an electric vector of the field and a magnetic vector of the field inside and outside of the particle, and determining additional scattered fields inside and outside of the particle due to reflection of the incident wave from the substrate.

Abstract: A method and apparatus for determining a location of a phase-to-earth fault on a three-phase electric line (30) of an electric network, comprising determining an equivalent load distance curve of the electric line (30) representing a voltage drop along the electric line scaled by an equivalent load distance of the electric line, determining a fault distance line indicating an estimate of a distance of the fault (F) from the measuring point (40) in relation to the equivalent load distance, determining a distance at which the equivalent load distance curve and the fault distance line intersect when superimposed, and selecting the determined distance as the distance between the measuring point (40) and the point of fault (F).

Abstract: Provided is a test apparatus that tests a DUT, which includes a driver that outputs a test signal to the DUT, a first transmission path that electrically connects the driver and the DUT, a first FET switch provided on the first transmission path to connect or disconnect the driver and the DUT to or from each other, and a capacitance compensator that detects an output signal from the DUT, and charges or discharges a capacitive component of the first FET switch based on the detected output signal.

Abstract: A power converter includes a controller and at least one circuit component. The controller is configured for monitoring stress on the circuit component during operation of the power converter and estimating a remaining life of the circuit component based on the monitored stress.

Abstract: Provided is an arc wave generator for testing an arc fault circuit interrupter (AFCI) for use in a test system for testing whether or not an arc fault circuit interrupter (AFCI) is operating normally, in which a false arc is generated for use in testing the arc fault circuit interrupter (AFCI). The arc wave generator includes a rectifier which receives a commercial power source as an input source and rectifies alternating-current voltage of the commercial power source to generate a rectified signal. A drop resistor drops the voltage of the rectified signal to generate a voltage-dropped signal. A mono-stable multivibrator adjusts a voltage level and a pulse width of the voltage-dropped signal and generates a pulse signal which is used to generate a false arc for testing the arc fault circuit interrupter (AFCI). Thus, a false arc is generated with a simple circuit to accurately test the actions of the arc fault circuit interrupter (AFCI).

Abstract: A system and method for measuring a characteristic impedance of a transmission-line comprises transmitting energy to the line, and shortly after measuring the voltage/current involved and thus measuring the equivalent impedance. The measured characteristic impedance may then be used in order to determine the termination value required to minimize reflections. In another embodiment, the proper termination is set or measured by adjusting the termination value to achieve maximum power dissipation in the terminating device. The equivalent characteristic impedance measurement may be used to count the number of metallic conductors connected to a single connection point. This abstract is not intended to limit or construe the scope of the claims.

Abstract: Contact holes (openings) (17) are created in the upper electrode (14) and the dielectric film (15) of a polysilicon-insulator-polysilicon (PIP) capacitive element to form a plurality of evaluation patterns wherein the lower electrode (13) and upper layer wiring lines (20) for measurement are electrically connected through contacts (16). At least four evaluation patterns are created by a combination of two or more values of a distance L with different values of a width W. Since it can be assumed that a difference in the resistance value between the respective evaluation patterns is only due to the effect of a change in a rectangular region (W*L) between the contact holes (openings) (17), it is possible to easily calculate the sheet resistance of the high-resistance portion from a change in the resistance value of each of the measurement patterns.

Abstract: Systems, methods, and computer readable media storing instructions for such methods relate to generating test vectors that can be used for exercising a particular area of interest in an integrated circuit. The test vectors generally include a non-overlapping repeating and/or predictable sequence of care bits (a care bit pattern) that can be used by a tester to cause the exercise of the area and collect emissions caused by exercising the area. Such emissions can be used for analysis and debugging of the circuit and/or a portion of it. Aspects can include providing a synchronization signal that can be used by a tester to allow sensor activation at appropriate times.

Abstract: The present invention relates to a test interface to which a mixed signal processing circuit is integrated, and more particularly to a test interface of a probe card or a DUT card to which a mixed signal processing circuit is integrated, and the mixed signal processing circuit is integrated to pin electronic channels of a tester and the operation process of the mixed signal processing circuit is integrated to the system software of the tester.

Abstract: A probe apparatus includes a load port for mounting therein a carrier having therein a plurality of substrates; a plurality of probe apparatus main bodies, each having a probe card having probes on its bottom surface; a substrate transfer mechanism for transferring the substrates between the load port and the probe apparatus main bodies, the substrate transfer mechanism being rotatable about a vertical axis and movable up and down. The substrate transfer mechanism has at least three substrates capable of moving back and forth independently. Further, at least two wafers are received from the carrier by the substrate transfer mechanism, and then are sequentially loaded into the probe apparatus main bodies. The prove apparatus a high throughput increasing a wafer transfer efficiency.

Abstract: A test apparatus of a semiconductor device is provided. A signal pin can be electrically connected to a connector and can have a region for electrically connecting to a semiconductor device. The signal pin can be inserted into the connector, and the region of the signal pin for electrically connecting to a semiconductor device can be located on a portion of the signal pin that is not inserted into the connector.

Abstract: In a device and a method for positioning an object, a drive of a movement device is controlled. To this end, a visual joystick is actuated, as a result of which a moveable actuator is moved, at least linearly by means of a display of a control unit of the movement device, into a position, in which a direction of movement, which can be implemented with the drive, is displayed symbolically. The drive for the movement of the object in the displayed direction of movement is initiated by means of a switching function of the actuator.

Abstract: A prove which can be easily formed, is not limited in a mounting position and number, and capable of sufficiently securing a space allowing a contact to move is provided. The probe has a contact to be brought into contact with an inspection object, and a beam part supporting the contact at a tip end portion. A rear portion of the beam part of the probe is joined to a surface at an inspection object side, of a contactor disposed to be opposed to the inspection object. The beam part of the probe is bent so that the above described contact at the tip end portion inclines to the above described inspection object side.

Abstract: A voltage island architecture wherein the source voltage of each voltage island can be independently turned on/off or adjusted during a scan-based test. The architecture includes a plurality of voltage islands, each powered by a respective island source voltage, and a testing circuit, coupled to the voltage islands, and powered by a global source voltage that is always on during test, wherein each island source voltage may be independently controlled during test.

Abstract: A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.

Abstract: An active cancellation matrix for process parameter measurements provides feedback paths for each test location wherein each feedback path is used to sense the applied voltage and the sensed voltage is used to adjust the source voltage for any variations along the input path. The devices under test are arranged in a row and column array, and the feedback and voltage input paths are formed along respective rails which extend generally parallel to a row of devices under test. Selectors are used to selectively route the outputs of the test nodes to a measurement unit such as a current sensor. The input voltages can be varied to establish current-voltage (I-V) curves for the devices under various conditions. In the example where the devices under test are transistors, each source input includes three voltage inputs (rails) for a drain voltage, a source voltage, and a gate voltage.

Abstract: Methods of characterizing a mechanical stress level in a stressed layer of a transistor and a mechanical stress characterizing test structure are disclosed. In one embodiment, the test structure includes a first test transistor including a first stress level; and at least one second test transistor having a substantially different second stress level. A testing circuit can then be used to characterize the mechanical stress level by comparing performance of the first test transistor and the at least one second test transistor. The type of test structure depends on the integration scheme used. In one embodiment, at least one second test transistor is provided with a substantially neutral stress level and/or an opposite stress level from the first stress level. The substantially neutral stress level may be provided by either rotating the transistor, removing the stressed layer causing the stress level or de-stressing the stressed layer causing the stress layer.

Abstract: A semiconductor device comprising a programming circuit that includes an active device on or in a substrate and a programmable electronic component on the substrate. The programmable electronic component includes at least one carbon nanotube having a segment with an adjusted diameter. The programmable electronic component has a value that depends upon the adjusted diameter. The programming circuit also includes interconnects that couple the active device to the programmable electronic component. The active device is configured to control a current transmitted to the programmable electronic component.

Abstract: Apparatus controlling the driver output slew rate that includes a driver circuit having an input signal and an output signal, where the driver circuit is structured and arranged to facilitate control of the slew rate of the output signal. A delay circuit having a time delay proportional to a desired transition time of the driver output signal is coupled to the output of the driver circuit. A first comparator detects when the driver output signal rises through a specified level, and a second comparator detects when the driver output falls through a second specified level. A phase detector is coupled to outputs of the first and second comparators and an output of the delay circuit for aligning the phases of the comparator outputs and the delayed comparator outputs by adjusting the driver output slew rate.

Abstract: A system for controlling the termination impedance of memory device data bus terminals is fabricated on the same die as the memory device. The system includes a termination resistor connected to each data bus terminal, which is connected in parallel with several transistors that are selectively turned on to adjust the termination impedance. The transistors are controlled by a circuit that determines the resistance of the termination resistor and turns on the correct number of transistor to properly set the termination impedance. In one example, the resistance of the termination resistor is determined by directly measuring a resistor of the same type as the termination resistor. In another example, the resistance of the termination resistor is determined indirectly by measuring parameters that affect the resistance of the termination resistor. In either case, the system can maintain the termination impedance of the data bus terminals constant despite changes in the termination resistor.

Abstract: A driver circuit is provided comprising at least two equal main units (MU) each comprising at least two sub units (SU) coupled to a data output (dout). Each sub unit (SU) is adapted to represent a respective predetermined impedance. Each main unit (MU) is adapted to that, when in a data mode, each sub unit (SU) of the respective main unit (MU) is switchable to either a first or second reference potential depending on a data signal to transmit. Each main unit (MU) is further adapted to that, when in a termination mode, the sub units (SU) of the respective main unit (MU) are switched to either the first or second reference potential such that an output of the respective main unit (MU) is neutral with respect to the driving of the data output (dout) to the first or second reference potential.

Abstract: On die termination circuit and method for calibrating the same includes a external resistor connected to a first node, a plurality of calibration resistors connected to a second node, the plurality of calibration resistors being turned on/off in response to a calibration code set, a current mirror configured to mirror currents of the first node and the second node and a code generator configured to generate a calibration code set according to the mirrored currents. In accordance with a method for calibrating an on die termination circuit of the present invention, the method includes a step of mirroring a current of a first node connected to an external resistor and a current of a second node connected to a plurality of calibration resistors and a step of generating a calibration code set according to the mirrored currents.

Abstract: An integrated circuit is capable of controlling a communication signal by using power ramp controlled communication buffer logic to generate an outgoing communication signal based on a detected voltage on a voltage source. The voltage source is necessary to supply power for power ramp controlled communication buffer logic. The voltage on the voltage source may be detected using power ramp sensor logic. The outgoing communication signal is based on a core logic output signal if the detected voltage is greater than or equal to a predetermined voltage level. If, the detected voltage is less than the predetermined voltage level, the outgoing communication signal is predetermined to be one of: a tristate outgoing communication signal, a logic one outgoing communication signal and a logic zero outgoing communication signal. Power ramp controlled communication buffer logic may also generate a core logic input signal based on an incoming communication signal in response to the detected voltage.

Abstract: An limited-switch dynamic logic (LSDL) circuit provides reduced power consumption by reducing clock power dissipation. By clocking LSDL gates with a clock signal having a reduced voltage swing in the evaluation phase, the LSDL gates are permitted to operate, while reducing the clock power consumption dramatically. Since clock power consumption dominates in LSDL circuits, the reduction in clock power dissipation results in a significant reduction in overall circuit power consumption. The reduced swing clock is produced at a plurality of local clock buffers by supplying the local clock buffers with an extra power supply rail that is switched onto the clock distribution lines by the local clock buffers in response to the full-swing evaluate phase clock received from the global clock distribution network by the local clock buffers.

Abstract: A DDS (direct digital synthesizer) remarkably increased in the number of frequencies which can be output while maintaining the phase coherency, and an NMR instrument using such a DDS are provided. A DDS including phase accumulators and a phase-to-amplitude modulator is provided with a plurality of phase accumulators operating with fixed phase implements which are equal to powers of 2, a controller for outputting each bit of a frequency tuning word as control data, a plurality of switches for outputting an output of an associated one of the phase accumulators when an associated one of the control data supplied from the controller is 1 and outputting 0 when the associated one of the control data is 0, and an adder for adding up outputs of the switches.

Abstract: A current load driving circuit for driving a current load, including: a first current mirror circuit that outputs a current; and a second current mirror circuit that receives the current outputted from the first current mirror circuit as an input current and then amplifies the input current to drive the current load. The whole of the first current mirror circuit and the second current mirror circuit is divided into an input circuit and an output circuit; and the divided position is provided on a voltage route of the first current mirror circuit or a voltage route of the second current mirror circuit.

Abstract: A communication apparatus and a method for generating a signal thereof are provided. The communication apparatus adjusts a bandwidth or central frequency of an oscillating signal which is generated from a chaotic signal to be used in the modulation, or adjusts both the bandwidth and the central frequency. Accordingly, it is possible to transform the oscillating signal generated from the chaotic signal more diversely and thus to modulate an information signal more diversely and more adaptively.

Abstract: An external clock round-trips a round-trip delay block configured by a selector and a short delay array, and is made capable of corresponding to a wide frequency by generating a long delay time required for synchronization at the time of a low frequency operation. Further, when a plurality of phase comparators are disposed, in both cases where comparing phases all at once and comparing phases one after another, it is possible to complete the phase synchronization within a short time by making a delay amount variable.

Abstract: A clock generator (622) includes a first circuit (812) and a second circuit (814). The first circuit (812) includes a first clock input configured to receive a first clock signal at a first frequency, a second clock input configured to receive a second clock signal at the first frequency, and an output. The second clock signal is out-of-phase with the first clock signal. The second circuit (814) is coupled to the first circuit (812) and includes a mode signal input configured to receive a mode signal. The output of the first circuit (812) is configured to provide a generated clock signal whose effective frequency is based on the first and second clock signals and the mode signal.

Abstract: A delay locked loop includes: a control voltage generator configured to generate a voltage control signal having a voltage level corresponding to a phase difference between an external clock and a feedback clock; a voltage controlled delay line configured to generate a plurality of output signals by reflecting a different delay time on the external clock in response to the voltage control signal; an internal clock multiplexer configured to output one of the plurality of output signals as an internal clock in response to a skew information signal; a delay replica model configured to output the feedback clock by reflecting a delay of an actual clock/data path on the internal clock; and a skew information signal generator configured to generate the skew information signal.

Abstract: A processor (400) includes a clock source (402), a central processing unit (CPU) (408), and a clock generator (404). The clock source (402) includes an output for providing a periodic clock signal. The CPU (408) includes an input for receiving a CPU clock signal. The clock generator (404) includes a first input coupled to the output of the clock source (402), a second input for receiving a mode signal that indicates an output frequency, and an output coupled to the input of the CPU (408). The clock generator (404) provides the CPU clock signal using periodic pulse skipping such that the CPU clock signal has a number of transitions over a unit of time corresponding to the output frequency.

Abstract: An on-chip jitter measurement circuit and corresponding method are provided for receiving a reference clock and a signal of interest, including a latch for comparing the arrival time of the signal of interest to the reference clock, a delay chain in signal communication with the reference clock for varying the arrival time of the reference clock, the delay chain having a first stage, a middle stage, and a last stage, a voltage controller in signal communication with the middle stage of the delay chain for controlling the delay of the arrival time of the reference clock while permitting the first and last stages of the delay chain to retain a full voltage swing independent of the delay.

Abstract: The present invention relates to a duty correction circuit that corrects a distorted duty of a clock signal using a delay unit and a delay controller, thereby reducing the layout area and current consumption.

Abstract: In one embodiment, a PWM controller is configured to form a drive signal that has an operating frequency that varies around a center by a percentage of the center frequency.

Abstract: A scan flip-flop circuit including a data input, a scan input, a data output, a flip-flop, a multiplexer and a delay element is provided. The multiplexer allows selection of either the scan input or the data input for presentation at the input of the flip-flop. The flip-flop provides an output signal at the output of the scan flip-flop. The delay element is in a signal path between the scan input and the input of the flip-flop, and provides a signal propagation delay between the scan input and the input of the flip-flop. The delay between the scan input and the input of the flip-flop is substantially larger than the signal propagation delay between the data input and the input of the flip-flop. The delay in the scan path reduces the need for external buffers to avoid hold-time violations during scan testing of integrated circuits.

Abstract: Provided is a cross-point latch and a method of operating the cross-point latch. The cross-point latch includes a signal line, two control lines crossing the signal line, and unipolar switches disposed at crossing points between the signal line and the control lines.

Abstract: A semiconductor circuit for an inverter device, comprising a pulse generator for generating a pulse signal upon receiving the input signal for controlling the high-voltage switching device of the inverter device, a driver circuit for driving the high-voltage switching device, and a signal transfer circuit for transferring the pulse signal generated by the pulse generator to the driver circuit, wherein a wide band-gap semiconductor device is used in the signal transfer circuit

Abstract: A clock distribution circuit having plural stages of buffers disposed along branch paths for dividing up a clock signal and configured in a manner that outputs of a plurality of buffers in a final stage and/or a middle stage are short-circuited, includes in relation to at least one buffer of a plurality of buffers in the same stage on a branch path, a selector for receiving an output of an adjacent buffer located upstream in terms of chain-connection along which the plurality of buffers are connected in testing, and a signal at a branch node corresponding to the at least one buffer by a first input and a second input respectively, selecting one of the first input and the second input based on a select control signal, and supplying the selected input to the one buffer.

Abstract: An improved clock switch in an integrated circuit chip that multiplexes two asynchronous clock signals to generate a multi-frequency clock signal in a manner that avoids glitches on the clock output line and meta-stable states within the switch. The clock switch does not include a cross-coupled feedback loop, thus rendering the clock switch test-friendly and avoiding potential race conditions in the switch. The clock switch is useable with asynchronous clock sources having a variety of different clock frequencies and phases.

Abstract: An electronic circuit arrangement is disclosed for converting an input voltage signal having a first voltage level into an output signal having a second voltage level. An input unit is provided for inputting the input voltage signal at the first voltage level, while an output unit is arranged for outputting the output signal at the output of the electronic circuit arrangement. A threshold value comparison unit serves for comparing the first voltage level of the input signal with a switch-on threshold value. The circuit arrangement furthermore contains an input impedance changeover unit for changing over an input impedance of the circuit arrangement from a low value to a high value after a predetermined delay duration after the first voltage level of the input voltage signal exceeded the switch-on threshold value.

Abstract: An internal voltage generator of a semiconductor device consumes relatively small amount of driving current and generates a stable internal voltage with relatively small voltage level variation. The semiconductor device includes an oscillator configured to generate an oscillation signal in response to an input signal, wherein the oscillation signal oscillates with a first period and oscillates with a second period longer than the first period during a predetermined latter section, and an internal circuit configured to perform a predetermined operation in response to the oscillation signal.