Abstract: A semiconductor device with a sheet-like insulating substrate (101) integral with two or more patterned layers of conductive lines and vias, a chip attached to an assembly site, and contact pads (103) in pad locations has an encapsulated region on the top surface of the substrate, extending to the edge of the substrate, enclosing the chip, and having contact apertures (703) at the pad locations for external communication with the pad metal surfaces. The apertures may have not-smooth sidewall surfaces and may be filled with solder material (704) to contact the pads. Metal-filled surface grooves (710) in the encapsulated region, with smooth groove bottom and sidewalls, are selected to serve as customized routing interconnections, or redistribution lines, between selected apertures and thus to facilitate the coupling with another semiconductor device to form a package-on-package assembly.

Abstract: A semiconductor device includes a first semiconductor package, a second semiconductor package. The first semiconductor package includes a first semiconductor package base having a first cavity formed therein, a first mount component mounted in the first cavity, and a first magnet disposed on the first semiconductor package base. The second semiconductor package includes a second semiconductor package base having a second cavity formed therein, a second mount component mounted in the second cavity, and a second magnet disposed on the second semiconductor package base so as to adsorb the first magnet. The first semiconductor package and the second semiconductor package are stacked by an adsorption of magnetic force between the first magnet and the second magnet.

Abstract: A semiconductor system (300) has one or more packaged active subsystems (310, 330); each subsystem has a substrate with electrical contact pads and one or more semiconductor chips stacked on top of each other, assembled on the substrate. The system further has a packaged passive subsystem (320) including a substrate with electrical contacts and passive electrical components, such as resistors, capacitors, and indictors. The passive subsystem is stacked with the active subsystems and connected to them by solder bodies.

Abstract: In some embodiments, vertical controlled side chip connection for 3D processor package is presented. In this regard, an apparatus is introduced having a substrate, a substantially horizontal, in relation to the substrate, integrated circuit device coupled to the substrate, and a substantially vertical, in relation of the substrate, integrated circuit device coupled to the substrate and adjacent to one side of the substantially horizontal integrated circuit device. Other embodiments are also disclosed and claimed.

Abstract: Consistent with an example embodiment, an integrated circuit device (IC) is assembled on a package substrate and encapsulated in a molding compound. There is a semiconductor die having a circuit pattern with contact pads. A package substrate having bump pad landings corresponding to the contact pads of the circuit pattern, has an interposer layer sandwiched between them. The interposer layer includes randomly distributed mutually isolated conductive columns of spherical particles embedded in an elastomeric material, wherein the interposer layer is subjected to a compressive force from pressure exerted upon an underside surface of the semiconductor die. The compressive force deforms the interposer layer causing the conductive columns of spherical particles to electrically connect the contact pads of the circuit pattern with the corresponding bump pad landings of the package substrate.

Abstract: A package includes a sensor die with a micro component, such as a MEMS device, coupled to an integrated circuit which may include, for example, CMOS circuitry, and one or more electrically conductive bond pads near the periphery of the sensor die. A semiconductor cap structure is attached to the sensor die. The front side of the cap structure is attached to the sensor die by a seal ring to hermetically encapsulate an area of the sensor die where the micro component is located. The bond pads on the sensor die are located outside the area encapsulated by the seal ring. Electrical leads, which extend along outer side edges of the semiconductor cap structure from its front side to its back side, are coupled to the micro component via the bond pads.

Abstract: Electronic modules and methods of fabrication are provided implementing a first metallization level directly on a chips-first chip layer. The chips-first layer includes chips, each with a pad mask over an upper surface and openings to expose chip contact pads. Structural dielectric material surrounds and physically contacts the side surfaces of the chips, and has an upper surface which is parallel to an upper surface of the chips. A metallization layer is disposed over the front surface of the chips-first layer, residing at least partially on the pad masks of the chips, and extending over one or more edges of the chips. Together, the pad masks of the chips, and the structural dielectric material electrically isolate the metallization layer from the edges of the chips, and from one or more electrical structures of the chips in the chips-first layer.

Abstract: A packaged RE power device includes a transistor having a control terminal and an output terminal and configured to operate at a fundamental operating frequency, an RF signal input lead coupled to the control terminal, and an RF signal output lead coupled to the output terminal. A harmonic reducer is coupled to the control terminal and/or the output terminal of the transistor and is configured to provide a short circuit or low impedance path from the control terminal and/or the output terminal to ground for signals at an Nth harmonic frequency of the fundamental operating frequency, where N>1. The device further includes a package that houses the transistor and the harmonic reducer, with the input lead and the output lead extending from the package. Multi-chip packages are also disclosed.

Abstract: A packaged RF transistor device includes an RF transistor die including a plurality of RF transistor cells. Each of the plurality of RF transistor cells includes a control terminal and an output terminal. The RF transistor device further includes an RF input lead, and an input matching network coupled between the RF input lead and the RF transistor die. The input matching network includes a plurality of capacitors having respective input terminals. The input terminals of the capacitors are coupled to the control terminals of respective ones of the RF transistor cells.

Abstract: A semiconductor package and a method for manufacturing the same capable of supplying power easily without an increase in the number of pads for power supply. The semiconductor package includes a semiconductor chip having a plurality of pads including pads for power supply disposed in a center portion and an internal wiring disposed to be exposed to outside; an insulating film formed on the semiconductor to expose the pads for power supply and the internal wirings; and re-distribution lines formed on the insulating film to connect between the exposed portions of the pads for power supply and the internal wiring.

Abstract: Disclosed are a stacked semiconductor package and a method for manufacturing the same. The method for manufacturing a stacked semiconductor package includes preparing a substrate formed with a seed metal layer; laminating semiconductor chips having via holes aligned with one another on the seed metal layer to form a semiconductor chip module; and growing a conductive layer inside of the via holes using the seed metal layer to form a conductive growth layer inside of the via holes.

Abstract: According to an exemplary embodiment, an overmolded semiconductor package includes at least one semiconductor die situated over a package substrate. The overmolded semiconductor package further includes a mold compound overlying the at least one semiconductor die and the package substrate and having a top surface. The overmolded semiconductor package further includes a first patterned conductive layer situated on the top surface of the mold compound. The overmolded semiconductor package can further include at least one conductive interconnect situated in the mold compound, where the at least one conductive interconnect is electrically connected to the first patterned conductive layer. The first patterned conductive layer can include at least one passive component.

Abstract: One method of the present invention includes preparing a die with traces and pads as desired for the intended use of the die. A MEMS device is mounted to the die. The die is then mounted to a substrate of the same material as the die. The substrate is then mounted to a package. The die and/or the substrate may be flip-chip mounted.

Abstract: An embedded chip package includes a substrate having a dielectric interposer, a first metal foil on a first surface and a second metal foil on a second surface of the substrate, wherein the substrate has a cavity recessed into the first surface; a metal heatsink embedded within the cavity; a semiconductor die mounted on a flat bottom of the metal heatsink; a dielectric layer covering the first surface of the substrate; at least one built-up circuit trace layer on the dielectric layer; a solder resist layer on the built-up circuit trace layer and on the dielectric layer; a heat-dissipating metal layer on the second metal foil; and heat-dissipating plugs connecting the flat bottom of the metal heatsink and the heat-dissipating metal layer.

Abstract: The invention relates to a semiconductor device comprising through contacts through a plastic housing composition and a method for the production thereof. For this purpose, the wiring substrate has a solder deposit on which through contact elements are arranged vertically with respect to the wiring substrate and extend as far as the top side of the semiconductor device.

Abstract: A device for reducing the chance that a microelectromechanical systems (MEMS) device with moving parts will have those parts stick to a glass cover of the MEMS device, and a method for making the device. An example embodiment of the invention includes a MEMS device wafer, a substrate wafer, and a glass cover. The MEMS device wafer includes perforations corresponding to the location(s) of exposed glass on the cover. An example embodiment of a method of the invention includes applying metal layers to a glass cover, perforating a device wafer at locations corresponding to areas of exposed glass on the glass cover, mounting the device wafer to the substrate wafer, and anodically bonding the glass cover to the substrate wafer or to the device wafer.

Abstract: A power semiconductor module has a silicon nitride insulated substrate, a metal circuit plate made of Cu or a Cu alloy, which is disposed on one surface of the silicon nitride insulated substrate, a semiconductor chip mounted on the metal circuit plate, and a heat dissipating plate made of Cu or a Cu alloy, which is disposed on the other surface of the silicon nitride insulated substrate; a carbon fiber-metal composite made of carbon fiber and Cu or a Cu alloy is provided between the silicon nitride insulated substrate and the metal circuit plate; the thermal conductivity of the carbon fiber-metal composite in a direction in which carbon fiber of the carbon fiber-metal composite is oriented is 400 W/m·k or more. Accordingly, a power semiconductor module that has a low thermal resistance between the semiconductor chip and a heat dissipating mechanism and also has improved cooling capacity is provided.

Abstract: A printed circuit board, a memory module having the same, and a fabrication method thereof. The printed circuit board includes an interconnection substrate on which electronic components are mounted and in which a plurality of signal lines are arranged. The signal lines are electrically coupled to the electronic components. A heat sink is disposed on one surface of the interconnection substrate to dissipate heat of the electronic components, and in which no signal lines are arranged. The printed circuit board includes a bending substrate coupling the interconnection substrate to the heat sink, and formed of a flexible material configured to be bent.

Abstract: Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips. Electronic modules are designed such that high-performance (high power) IC chips are disposed in close proximity to the integrated cooling module (or cooling plate) for effective heat extraction. Moreover, electronic modules which comprise large surface area silicon carriers with multiple chips face mounted thereon are designed such that integrated silicon cooling modules are rigidly bonded to the back surfaces of such chips to increase the structural integrity of the silicon carriers.

Abstract: Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material.

Abstract: A microelectronic package with enhanced thermal management using an embedded heat spreader is disclosed. The microelectronic package comprises a die mounted on a substrate, a thermal interface material disposed in thermal conductive communication with the die and a heat spreader disposed in thermal conductive communication with the thermal interface material. A mold material is provided to enclose the die and the thermal interface material, and partially embedding the heat spreader to expose at least a surface of the heat spreader to an ambient environment. The heat spreader may include an anchor portion to reinforce coupling of the heat spreader to the mold material. If and when required, the heat spreader may be coupled in thermal communication with an external heat sink.

Abstract: An integrated circuit package system includes a base substrate having a base substrate cavity, attaching a junction integrated circuit package over the base substrate with a portion of the junction integrated circuit package in the base substrate cavity, and attaching a base integrated circuit over the junction integrated circuit package and the base substrate.

Abstract: Stackable integrated circuit devices include an integrated circuit die having interconnect pads on an active (front) side, the die having a front side edge at the conjunction of the front side of the die and a sidewall of the die, and a back side edge at the conjunction of back side of the die and the sidewall; the die further includes a conductive trace which is electrically connected to an interconnect pad and which extends over the front side edge of the die. In some embodiments the conductive trace further extends over the sidewall, and, in some such embodiments the conductive trace further extends over the back side edge of the die, and in some such embodiments the conductive trace further extends over the back side of the die. One or both of the die edges may be chamfered. Also, methods for making such a device. Also, assemblies including such a device electrically interconnected to underlying circuitry (e.g.

Abstract: Provided are a semiconductor package and a semiconductor package module including the same. The semiconductor package may include a plurality of semiconductor chips, a plurality of leads connected to pads of the semiconductor chips and externally exposed, wherein the plurality of leads may be classified into a plurality of pin groups, and the plurality of semiconductor chips may be classified into a plurality of chip groups, and the pads of the semiconductor chips of like chip groups may be connected to the leads of like pin groups.

Abstract: The present invention allows for direct chip-to-chip connections using the shortest possible signal path.

Abstract: A microelectronic substrate and a microelectronic package including the substrate and a die bonded thereto. The substrate includes a substrate panel having a die-side surface including a die-attach region; a system of interconnects extending through the substrate panel and adapted to allow a connection of the substrate to external circuitry; and a plurality of solder bumps including: die-attach solder bumps electrically coupled to the system of interconnects and disposed in the die-attach region; and barrier solder bumps isolated from the system of interconnects, the barrier solder bumps being disposed outside of the die-attach region and being adapted to substantially limit a flow of underfill away from the die-attach region.

Abstract: An integrated circuit package system that includes: providing an electrical interconnect system including an inner lead-finger system and an outer lead-finger system; stacking a first device, a second device, and a third device between and over the electrical interconnect system; connecting the first device and the second device to the inner lead-finger system; and connecting the third device to the outer lead-finger system.

Abstract: The invention discloses a novel package structure of integrate circuit or discrete device and packaging method, and includes the lead pins adjacent to the island; another metal layer formed at the bottom of the island; another metal layer formed at the bottom of lead pins; chip mounted on the island; wires bonded between the chip and the lead pins; the molded body encapsulating the top surface and side surface of the island and the lead pins, small protrusions of the island and the lead pins below the molded body; in the individual package, the number of the island can be one or more, lead pins can be arrayed at one side of the island, also can be arrayed at two sides or three sides of the island, one or two rows of lead pins can be located around the island. The invention provides strong welding, good quality, low cost, smooth production, wide applicability, flexible arrangement of the chips.

Abstract: There are provided the steps of forming a bump 104 on an electrode pad 103 provided on a semiconductor chip 101, forming a low-modulus insulating layer 120 on the semiconductor chip 101 and laminating, on the low-modulus insulating layer 120, a high-modulus insulating layer 121 having a higher elastic modulus than an elastic modulus of the low-modulus insulating layer 120, thereby forming a laminated insulating layer 105, exposing a part of the bump 104 from an upper surface of the laminated insulating layer 105, and forming a conductive pattern 106 connected to the bump 104.

Abstract: There are provided the steps of forming a bump 104 having a protruded portion 104B on an electrode pad 103 formed on a substrate 101A, forming an insulating layer 105 on the substrate 101A and exposing a part of the protruded portion 104B to an upper surface of the insulating layer 105, forming a first conductive pattern 107 by using a depositing process in the upper surface of the insulating layer 105 and an exposed part of the protruded portion 104B, carrying out electrolytic plating by using the first conductive pattern 107 as a feeding layer, thereby forming a second conductive pattern 108, and patterning the second conductive pattern 108 to form a conductive pattern 106 connected to the bump 104.

Abstract: The present invention provides a double-sided electrode package of a structure excellent in the reliability of connection and moisture resistance to another package, which is capable of being manufactured simply and at low cost. The present invention also provides a double-sided electrode package of a structure capable of forming inner wirings (electrode pads) in arbitrary layouts according to the number of pins of a semiconductor chip and the size thereof, which package is capable of being manufactured simply and at low cost. A copper foil is attached onto a core material formed with electrode pads, wirings, through electrodes, lands and a solder resist. The copper foil is wet-etched in several stages to form surface side terminals which stand on the wirings approximately vertically and each of which includes a plurality of protrusions (convex portions continuous in the circumferential direction) formed at their side faces over the full circumference along the circumferential direction.

Abstract: A semiconductor package includes a semiconductor chip having bonding pads formed on a top surface and a first via hole and a second via hole formed on both-side edges; a passive element formed within the first via hole; a via wiring formed within the second via hole; a first wiring connected to the bonding pad at one end and connected to the passive element and the via wiring on a top surface of the semiconductor chip; a second wiring formed on a back surface of the semiconductor chip and formed to connect with the passive element and the via wiring; a first passivation film formed in such a way to expose one portion of the first wiring on a top surface of the semiconductor chip; and a second passivation film formed in such a way to expose one portion of the second wiring on a bottom surface of the semiconductor chip.

Abstract: A chip package includes a patterned conductive layer, a first solder resist layer, a second solder resist layer, a chip, bonding wires and a molding compound. The patterned conductive layer has a first surface and a second surface opposite to each other. The first solder resist layer is disposed on the first surface. The second solder resist layer is disposed on the second surface, wherein a part of the second surface is exposed by the second solder resist layer. The chip is disposed on the first solder resist layer, wherein the first solder resist layer is disposed between the patterned conductive layer and the chip. The bonding wires are electrically connected to the chip and the patterned conductive layer exposed by the second solder resist layer. The molding compound encapsulates the pattern conductive layer, the first solder resist layer, the second solder resist layer, the chip and the bonding wires.

Abstract: Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. In one embodiment, the method comprises forming metal plug contacts through a hard mask and a premetal dielectric to transistors in the semiconductor. The method also includes etching a hole for a through-hole via through the hard mask to the semiconductor using a patterned photoresist process, removing the patterned photoresist and using a hard mask process to etch the hole to an amount into the semiconductor. The method further includes depositing a dielectric liner to isolate the hole from the semiconductor, depositing a gapfill metal to fill the hole, and planarizing the surface of the substrate to the hard mask. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.

Abstract: A contact to a semiconductor including sequential layers of Cr, Ti, and Al is provided, which can result in a contact with one or more advantages over Ti/Al-based and Cr/Al-based contacts. For example, the contact can: reduce a contact resistance; provide an improved surface morphology; provide a better contact linearity; and/or require a lower annealing temperature, as compared to the prior art Ti/Al-based contacts.

Abstract: A metal pad formation method and metal pad structure using the same are provided. A wider first pad metal is formed together with a first metal. A dielectric layer is then deposited thereon. A first opening and a second opening are formed in the dielectric layer to respectively expose the first metal and the first pad metal. Then, the first opening is filled by W metal to generate a first via. Finally, a second metal and a second pad metal are formed to respectively cover the first via and the first pad metal to generate the metal pad.

Abstract: Methods and apparatus to provide die backside metallization and/or surface activated bonding for stacked die packages are described. In one embodiment, an active metal layer of a first die may be coupled to an active metal layer of a second die through silicon vias and/or a die backside metallization layer of the second die. Other embodiments are also described.

Abstract: Methods and apparatuses for fabricating three-dimensional integrated circuits having through hole vias are provided. One aspect of the present invention is a method of gapfill for through hole vias for three-dimensional integrated circuits. The method comprises providing a semiconductor wafer having a plurality of holes for through hole vias and depositing a conformal metal layer to partially fill the holes to leave open voids. The method also includes purging the voids and cleaning the surface of the voids and using a dry deposition process to fill or close the voids. Another aspect of the present invention is an electronic device structure for a three-dimensional integrated circuit.

Abstract: A semiconductor device includes a carrier, a chip including a first face having a contact area, where the chip is attached to the carrier such that the contact area faces away from the carrier, a copper connector configured for attachment to the contact area, and a solder material configured to couple the copper connector to the contact area.

Abstract: A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure.

Abstract: Semiconductor devices and methods of fabricating the same are disclosed. An illustrated semiconductor device fabricating method includes forming a titanium and titanium-nitride (Ti/TiN) metal layer on a lower oxide layer; forming an aluminum metal layer on the Ti/TiN metal layer; forming an indium tin oxide (ITO) layer on the aluminum metal layer; and patterning the ITO layer, the aluminum metal layer, and the Ti/TiN metal layer by photolithography to form a metal layer pattern and to expose a surface of the lower oxide layer, thereby facilitating a process of filling inter-wiring spaces occurring between adjacent lines of a metal layer pattern by producing a metal layer pattern having a reduced aspect ratio.

Abstract: An interconnect structure is provided that has enhanced electromigration reliability without degrading circuit short yield, and improved technology extendibility. The inventive interconnect structure includes a dielectric material having a dielectric constant of about 3.0 or less. The dielectric material has at least one conductive material embedded therein. A noble metal cap is located directly on an upper surface of the at least one conductive region. The noble metal cap does not substantially extend onto an upper surface of the dielectric material that is adjacent to the at least one conductive region, and the noble cap material does not be deposited on the dielectric surface. A method fabricating such an interconnect structure utilizing a low temperature (about 300° C. or less) chemical deposition process is also provided.

Abstract: (a) A first Sn absorption layer (5) is formed on the principal surface of a first substrate (1), the first Sn absorption layer being made of metal absorbing Sn from AuSn alloy and lowering a relative proportion of Sn in the AuSn alloy. (b) A second Sn absorption layer (17) is formed on the principal surface of a second substrate (11) the second Sn absorption layer being made of metal absorbing Sn from AuSn alloy and lowering a relative proportion of Sn in the AuSn alloy. (c) A solder layer (7) made of AuSn alloy is formed at least on one Sn absorption layer of the first and second Sn absorption layers. (d) The first and second substrates are bonded together by melting the solder layer in a state that the first and second substrates are in contact with each other, with the principal surfaces of the first and second substrates facing each other.

Abstract: The present invention discloses a display device and a manufacturing method thereof by which a manufacturing process can be simplified. Further, the present invention discloses technique for manufacturing a pattern such as a wiring into a desired shape with good controllability. A method for forming a pattern for constituting the display device according to the present invention comprises the steps of forming a first region and a second region; discharging a composition containing a pattern formation material to a region across the second region and the first region; and flowing a part of the composition discharged to the first region into the second region; wherein wettability with respect to the composition of the first region is lower than that of the second composition.

Abstract: A method of forming a noble metal cap on a conductive material embedded in a dielectric material in an interconnect structure. The method includes the step of contacting (i) a conductive material having a bare upper surface partially embedded in a dielectric material and (ii) vapor of a noble metal containing compound, in the presence of carbon monoxide and a carrier gas. The contacting step is carried out at a temperature, pressure and for a length of time sufficient to produce a noble metal cap disposed directly on the upper surface of the conductive material without substantially extending into upper surface of the dielectric material or leaving a noble metal residue onto the dielectric material.

Abstract: A method of fabricating an integrated circuit including arranging a nanowire with a first end portion thereof at a first contact surface of a first electrical contact and with a second end portion sticking up from the first contact surface, and embedding at least part of the nanowire in dielectric material.

Abstract: A mounting substrate and a method of manufacturing the mounting substrate. The mounting substrate can include an insulation layer, a bonding pad buried in one side of the insulation layer in correspondence with a mounting position of a chip, and a circuit pattern electrically connected to the bonding pad. By utilizing certain embodiments of the invention, the process for stacking a solder resist layer can be omitted, as the bonding pads can be implemented in a form recessed from the surface of the insulation layer. In this way, the manufacturing process can be simplified and manufacturing costs can be reduced. Since the surface of the mounting-substrate on which to mount a chip can be kept flat without any protuberances, the occurrence of voids in the underfill can be minimized. This is correlated to obtaining a high degree of reliability, and leads to a greater likelihood of successful mounting.

Abstract: In example embodiment, there is an integrated circuit (IC) device (5) assembled in a package (5) having a plurality of die including a first device (20) and at least one additional device (30). The IC comprises a substrate (10). A first device die (20), having bonding pads including ground connections, is die attached to the substrate (10). An additional device die (30), having bonding pads including ground connections is disposed on top of the first device die (20). The additional device die is die attached to the first device die. The ground connections of the first device die are connected to the ground connections of the additional device die in order to minimize the electrical interference between the device dies. An additional feature of the embodiment is, ground connections of the first device are connected to the ground connections of the additional device with a conductive adhesive (25).

Abstract: A self-aligned wafer or chip structure including a substrate, at least one first concave base, at least one second concave base, at least one connecting structure and at least one bump is provided. The substrate has a first surface and a second surface, and at least one pad is formed on the first surface. The first concave base is disposed on the first surface and electrically connected to the pad. The second concave base is disposed on the second surface. The connecting structure passes through the substrate and disposed between the first and second concave bases so as to be electrically connected to the first and second concave bases. The bump is filled in the second concave base and protrudes out of the second surface.

Abstract: An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).