Abstract: Non-volatile memory devices and methods of fabricating the same are provided. The non-volatile memory devices may include a semiconductor substrate having a pair of sidewall channel regions extending from the semiconductor substrate and opposite to each other, and a floating gate electrode between the pair of sidewall channel regions and protruding from the semiconductor substrate. A control gate electrode may be formed on the semiconductor substrate and a portion of the floating gate electrode.

Abstract: A decease in reliability of a memory element having a floating gate is suppressed. The invention relates to a semiconductor device having an island-like semiconductor film, which is formed over an insulating surface and includes a channel formation region and a high-concentration impurity region, a tunneling insulating film formed over the island-like semiconductor film, a floating gate formed over the tunneling insulating film, a gate insulating film formed over the floating gate, a control gate formed over the gate insulating film, and a first insulating film formed between the tunneling insulating film and the floating gate. The first insulating film is formed of an oxide film of the material of the floating gate, so that the material of the floating gate is prevented from diffusing into the tunneling insulating film.

Abstract: A flash memory comprising a substrate, a stacked structure over the substrate, a source, a drain and a source-side spacer is provided. The stacked structure includes a tunneling oxide layer, a floating gate on the tunneling oxide layer, an inter-gate dielectric layer on the floating gate and a control gate on the inter-gate dielectric layer. The source and the drain are disposed in the substrate on the sides of the floating gate, respectively. The source-side spacer is disposed on a sidewall of the stacked structure near the source, thereby preventing the tunneling oxide layer and the inter-gate dielectric layer near the source from being re-oxidized, resulting in an increased thickness.

Abstract: A memory cell of a nonvolatile semiconductor memory includes a semiconductor region, source/drain areas arranged separately from each other in the semiconductor region, a tunnel insulating film arranged on a channel region between the diffusion areas, a floating gate electrode arranged on the tunnel insulating film, an inter-electrode insulator arranged on the floating gate electrode, and a control gate electrode arranged on the inter-electrode insulator. The inter-electrode insulator includes lanthanoid-based metal Ln, aluminum Al, and oxygen O, and a composition ratio Ln/(Al+Ln) between the lanthanoid-based metal and the aluminum takes a value within the range of 0.33 to 0.39.

Abstract: An EEPROM device includes a device isolation layer disposed at a predetermined region of a semiconductor substrate to define active regions, a pair of control gates crossing the device isolation layers and an active region, a pair of selection gates interposed between the control gates to cross the device isolation layers and the active region and a floating gate and an intergate dielectric pattern stacked sequentially between the control gates and the active region The EEPROM device further includes a gate insulation layer of a memory transistor interposed between the floating gate and the active region and a tunnel insulation layer thinner than the gate insulation layer of the memory transistor and a gate insulation layer of a selection transistor interposed between the selection gates and the active region. The tunnel insulation layer is aligned at one side adjacent to the floating gate.

Abstract: A semiconductor memory device and a method for its fabrication are provided. In accordance with one embodiment of the invention the method comprises the steps of forming a gate insulator and a gate electrode overlying a semiconductor substrate. The gate insulator is etched to form an undercut opening beneath an edge of the gate electrode and the undercut opening is filled with a layered structure comprising a charge trapping layer sandwiched between layers of oxide and nitride. A region of the semiconductor substrate is impurity doped to form a bit line aligned with the gate electrode, and a conductive layer is deposited and patterned to form a word line coupled to the gate electrode.

Abstract: A nonvolatile semiconductor memory device has a plurality of memory strings each including a plurality of electrically rewritable memory cells serially connected. The memory string includes a columnar semiconductor portion extending in the vertical direction from a substrate, a first charge storage layer formed adjacent to the columnar semiconductor portion and configured to accumulate charge, a first block insulator formed adjacent to the first charge storage layer, and a first conductor formed adjacent to the first block insulator.

Abstract: There is provided a method of manufacturing a semiconductor device, including the following steps: flowing a first precursor gas to the semiconductor substrate within a ALD chamber to form a first discrete monolayer on the semiconductor substrate; flowing an inert purge gas to the semiconductor substrate within the ALD chamber; flowing a second precursor gas to the ALD chamber to react with the first precursor gas which has formed the first monolayer, thereby forming a first discrete compound monolayer; and flowing an inert purge gas; forming a first dielectric layer to cover the discrete compound monolayer; forming a second third monolayer above first dielectric layer; and forming a second discrete compound monolayer; and forming a second dielectric layer to cover the second discrete compound monolayer above the first dielectric layer. There is also provided a semiconductor device formed by the ALD method.

Abstract: There is provided a method of manufacturing a semiconductor device, including the following steps: flowing a first precursor gas to the semiconductor substrate within the ALD chamber to form a first discrete monolayer on the semiconductor substrate; flowing an inert purge gas to the semiconductor substrate within the ALD chamber; flowing a second precursor gas to the ALD chamber to react with the first precursor gas which has formed the first monolayer, thereby forming a first discrete compound monolayer; and flowing an inert purge gas; and forming a second discrete compound monolayer above the semiconductor substrate by the same process as that for forming the first discrete compound monolayer. There is also provided a semiconductor device in which the charge trapping layer is a dielectric layer containing the first and second discrete compound monolayers formed by the ALD method.

Abstract: A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor layer has a thickness such that a sensitivity parameter relating an electrical interaction between the gate electrodes of the access device and the memory device is less than a predetermined value. The dual-gate memory cells can be used as building blocks for a non-volatile memory array, such as a memory array formed by NAND-strings.

Abstract: Disclosed are atomic layer deposition method and a semiconductor device including the atomic layer, including the steps: placing a semiconductor substrate in an atomic layer deposition chamber; feeding a first precursor gas to the semiconductor substrate within the chamber to form a first discrete monolayer on the semiconductor substrate; feeding an inert purge gas to the semiconductor substrate within the chamber to remove the first precursor gas which has not formed the first discrete monolayer on the semiconductor substrate; feeding a second precursor gas to the chamber to react with the first precursor gas which has formed the first discrete monolayer, forming a discrete atomic size islands; and feeding an inert purge gas to the semiconductor substrate within the chamber to remove the second precursor gas which has not reacted with the first precursor gas and byproducts produced by the reaction between the first and the second precursor gases.

Abstract: A non-volatile semiconductor storage device 10 has a plurality of memory strings 100 with a plurality of electrically rewritable memory transistors MTr1-MTr4 connected in series. The memory string 100 includes a columnar semiconductor CLmn extending in a direction perpendicular to a substrate, a plurality of charge accumulation layers formed around the columnar semiconductor CLmn via insulating films, and selection gate lines on the drain side SGD contacting the columnar semiconductor to configure transistors. The selection gate lines on the drain side SGD have lower selection gate lines on the drain side SGDd, each of which is arranged with an interval with a certain pitch, and upper selection gate lines on the drain side SGDu located on a higher layer than the lower selection gate lines on the drain side SGDd, each of which is arranged on gaps between the lower selection gate lines on the drain side SGDd.

Abstract: There is provided a semiconductor device having a drift layer with a pillar structure including first semiconductor layer portions of the first conduction type and second semiconductor layer portions of the second conduction type formed in pillars alternately and periodically on a semiconductor substrate. A device region includes a plurality of arrayed transistors composed of the first semiconductor layer portions and the second semiconductor layer portions. A terminal region is formed at the periphery of the device region without the transistors formed therein. The drift layer in the terminal region has a carrier lifetime lower than ? the carrier lifetime in the drift layer in the device region.

Abstract: A high-voltage metal-oxide-semiconductor (HV MOS) transistor is provided to form the decoder in a source driver of a display apparatus for substantially saving the layout area. The HV MOS transistor includes two doped regions with a first conductivity type disposed in a semiconductor substrate, and a gate region having a second conductivity type opposite to the first conductivity type on the semiconductor substrate and between the doped regions. Accordingly, the layout area could be substantially reduced.

Abstract: A semiconductor device includes a first first-conductivity-type semiconductor layer, a second first-conductivity-type semiconductor layer provided on a major surface of the first first-conductivity-type semiconductor layer; a third second-conductivity-type semiconductor layer being adjacent to the second first-conductivity-type semiconductor layer, provided on the major surface of the first first-conductivity-type semiconductor layer, and forming a periodic array structure in combination with the second first-conductivity-type semiconductor layer in a horizontal direction generally parallel to the major surface of the first first-conductivity-type semiconductor layer, and a sixth semiconductor layer located outside and adjacent to the periodic array structure of the second first-conductivity-type semiconductor layer and the third second-conductivity-type semiconductor layer, provided on the major surface of the first first-conductivity-type semiconductor layer, and having a lower impurity concentration than t

Abstract: A semiconductor device includes: a semiconductor substrate having a substrate surface; a spiral body constituted by a linear semiconductor layer on which a body region including a channel region, a first source/drain region disposed on the body region, and a second source/drain region disposed under the body region or in the semiconductor substrate around the linear semiconductor layer are formed, the linear semiconductor layer being formed on the substrate surface substantially in a spiral form viewed from the substrate surface in a plan view, formed substantially in a protrudent form in a cross-sectional view, and having a pair of sidewall portions; a gate insulating film formed on at least the pair of sidewall portions constituting the linear semiconductor layer; and a gate electrode that is adjacent to the pair of sidewall portions via the gate insulating film.

Abstract: A trench gate power MOSFET (1) includes: an n?-type epitaxial layer (12); a p-type body region (20) formed in the vicinity of an upper surface of the n?-type epitaxial layer (12); a plurality of trenches (14) formed so as to reach the n?-type epitaxial layer (12) from an upper surface of the p-type body region (20); and gates (18) formed in the trenches (14). In some regions facing the p-type body region (20) in the n?-type epitaxial layer (12), p-type carrier extracting regions (26a, 26b, 26c) are formed. According to the trench gate power MOSFET (1), holes generated in a cell region can be effectively collected through the p-type carrier extracting regions (26a, 26b, 26c) so as to further increase a speed of the switching operation.

Abstract: A nanotube field effect transistor and a method of fabrication are disclosed. The method includes electrophoretic deposition of a nanotube to contact a region of a conductive layer defined by an aperture.

Abstract: The method of forming a semiconductor structure in a substrate comprises, forming a first trench with a first width We and a second trench with a second width Wc, wherein the first width We is larger than the second width Wc, depositing a protection material, lining the first trench, covering the substrate surface and filling the second trench and removing partially the protection material, wherein a lower portion of the second trench remains filled with the protection material.

Abstract: A silicon (Si)-on-insulator (SOI) high voltage transistor is provided with an associated fabrication process. The method provides a SOI substrate with a Si top layer. A control channel and an adjacent auxiliary channel are formed in the Si top layer. A control gate overlies the control channel and an auxiliary gate overlies the auxiliary channel. A source region is formed adjacent the control channel, and a lightly doped drain (LDD) region is interposed between the auxiliary channel and the drain. An interior drain region is interposed between the control and auxiliary channels. Typically, the Si top layer has a thickness in the range of 20 to 1000 nm. In one aspect, the Si top layer in the source, control channel, interior drain, and auxiliary channel regions is thinned to a thickness in the range of 5 to 200 nm, and raised source, drain, LDD, and interior drain regions are formed.

Abstract: A LDD layer of the second conduction type locates in the surface of a semiconductor layer beneath a sidewall insulator film. A source layer of the second conduction type is formed in the surface of the semiconductor layer at a position adjacent to the LDD layer. A resurf layer of the second conduction type is formed in the surface of the semiconductor layer at a position sandwiching the gate electrode with the LDD layer. A drain layer of the second conduction type is formed in the surface of the semiconductor layer at a position adjacent to the resurf layer. The resurf layer is formed in depth to have peaks of a first and a second impurity concentration in turn from the surface of the semiconductor layer. The peak of the first impurity concentration is smaller than the peak of the second impurity concentration.

Abstract: A semiconductor device comprises a gate electrode on a semiconductor substrate, drift regions at opposite sides of the gate electrode, source and drain regions in the respective drift regions, and shallow trench isolation (STI) regions in the respective drift regions between the gate electrode and the source or drain region, wherein the drift regions comprise first and second conductivity-type impurities.

Abstract: A high voltage device includes a semiconductor substrate and a gate. The semiconductor substrate includes a first doped region having a first conductive type, a second doped region having a second conductive type, a third doped region having the second conductive type, a fourth doped region surrounding the third doped region and having the second conductive type, and a fifth doped region surrounding the third doped region and having the second conductive type. The gate is disposed between two spacers to separate the second doped region from the third doped region, so as to control the conduction of the second doped region and the third doped region. In the high voltage device, the fifth doped region surrounds the third doped region, so as to strengthen the coverage for the third doped region and improve the ion concentration uniformity on the bottom of the third doped region to reduce leakage current.

Abstract: A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region.

Abstract: Improved fin field effect transistor (FinFET) devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a field effect transistor device comprises the following steps. A substrate is provided having a silicon layer thereon. A fin lithography hardmask is patterned on the silicon layer. A dummy gate structure is placed over a central portion of the fin lithography hardmask. A tiller layer is deposited around the dummy gate structure. The dummy gate structure is removed to reveal a trench in the filler layer, centered over the central portion of the fin lithography hardmask, that distinguishes a fin region of the device from source and drain regions of the device. The fin lithography hardmask in the fin region is used to etch a plurality of fins in the silicon layer. The trench is filled with a gate material to form a gate stack over the fins.

Abstract: Embodiments of the present invention relate to the fabrication of three-dimensional multi-gate transistor devices with high aspect ratio semiconductor bodies through the use of a high K dielectric material layer which is selectively wet etched to from a high K gate dielectric. In one specific embodiment, the high K gate dielectric comprises hafnium oxide, the etch stop layer comprises silicon oxide, and the etchant comprise phosphoric acid conditioned with silicon nitride.

Abstract: An object is to provide a semiconductor device in which an antenna is not bent and electric waves can be transmitted and received even if a substrate is bent and in which a thin and flexible substrate can be used. The present invention relates to a semiconductor device characterized in that it has an antenna having a spiral shape, a zigzag shape, a comb shape, a lattice shape, a radial shape or a net shape, which is formed using a superelastic alloy material or a shape-memory alloy material over at least one entire surface of a flat and flexible substrate; and a circuit including a thin film transistor, which is connected to the antenna.

Abstract: A method of forming a semiconductor device may include forming an interlayer insulating layer on a semiconductor substrate, and the interlayer insulating layer may have a contact hole therein exposing a portion of the semiconductor substrate. A single crystal semiconductor plug may be formed in the contact hole and on portions of the interlayer insulating layer adjacent the contact hole opposite the semiconductor substrate, and portions of the interlayer insulating layer opposite the semiconductor substrate may be free of the single crystal semiconductor plug. Portions of the single crystal semiconductor plug in the contact hole may be removed while maintaining portions of the single crystal semiconductor plug on portions of the interlayer insulating layer adjacent the contact hole as a single crystal semiconductor contact pattern.

Abstract: A partial oxide film with well regions formed therebeneath isolates transistor formation regions in an SOI layer from each other. A p-type well region is formed beneath part of the partial oxide film which isolates NMOS transistors from each other, and an n-type well region is formed beneath part of the partial oxide film which isolates PMOS transistors from each other. The p-type well region and the n-type well region are formed in side-by-side relation beneath part of the partial oxide film which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region adjacent thereto. An interconnect layer formed on an interlayer insulation film is electrically connected to the body region through a body contact provided in the interlayer insulation film. A semiconductor device having an SOI structure reduces a floating-substrate effect.

Abstract: Disclosed is a method for forming a dual gate electrode of a semiconductor device, which may improve manufacturing productivity by simplifying a process of forming gate electrodes in PMOS and NMOS regions, respectively, and may provide improvement in performance by making the two gate electrodes have a different thickness and material state in a manner that one of the two gate electrodes has a single-layer structure and the other one has a two-layer structure.

Abstract: An electronic device can include a gated diode, wherein the gated diode includes a junction diode structure including a junction. A first conductive member spaced apart from and adjacent to the junction can be connected to a first signal line. A second conductive member, spaced apart from and adjacent to the junction, can be both electrically connected to a second signal line and electrically insulated from the first conductive member. The junction diode structure can include a p-n or a p-i-n junction. A process for forming the electronic device is also described.

Abstract: A semiconductor device comprises an N-type insulated-gate field-effect transistor including a first insulating layer that is provided along side walls of a gate electrode, has a negative thermal expansion coefficient, and applies a tensile stress to a channel region of the N-type insulated-gate field-effect transistor. The device also comprises a P-type insulated-gate field-effect transistor including a second insulating layer that is provided along side walls of a gate electrode, has a positive thermal expansion coefficient, and applies a compression stress to a channel region of the P-type insulated-gate field-effect transistor.

Abstract: A semiconductor system is provided including providing a semiconductor substrate; forming PMOS and NMOS transistors in and on the semiconductor substrate; forming a tensile strained layer on the semiconductor substrate; and relaxing the tensile strained layer around the PMOS transistor.

Abstract: A semiconductor device includes an n-type MIS (Metal Insulator Semiconductor) transistor and a p-type MIS transistor. The n-type MIS transistor includes a first gate insulating film, a first fully silicided (FUSI) gate electrode formed on the first gate insulating film and made of a first metal silicide film, and a first sidewall insulating film. The p-type MIS transistor includes a second gate insulating film, a second fully silicided (FUSI) gate electrode formed on the second gate insulating film and made of a second metal silicide film, and a second sidewall insulating film. A top surface of the first FUSI gate electrode is located lower than a top surface of the second FUSI gate electrode.

Abstract: A semiconductor device includes a dual gate CMOS logic circuit having gate electrodes with different conducting types and a trench capacitor type memory on a same substrate includes a trench of the substrate for the trench capacitor, a dielectric film formed in the trench, a first poly silicon film formed inside of the trench, and a cell plate electrode located above the dielectric film. The cell plate electrode includes a first poly silicon film formed on the dielectric film partially filling the trench, and a second poly silicon film formed on the first poly silicon film to completely fill the trench. The second poly silicon film includes a sufficient film thickness for forming gate electrodes, wherein the impurity concentration of the first poly silicon film is higher than the impurity concentration of the second poly silicon film.

Abstract: A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.

Abstract: The present invention discloses a semiconductor source/drain contact structure, which comprises a substrate, a source/drain region disposed in the substrate, at least one non-silicided conductive layer including a barrier layer disposed over and in contact with the source/ drain region, and one or more contact hole filling metals disposed over and in contact with the at least one non-silicided conductive layer, wherein a first contact area between the at least one non-silicided conductive layer and the source/drain region is substantially larger than a second contact area between the one or more contact hole filling metals and the at least one non-silicided conductive layer.

Abstract: A method for manufacturing a semiconductor device. The method comprises forming a metal layer on a silicon-containing layer located on a semiconductor substrate. The method also comprises reacting a portion of the metal layer with the silicon-containing layer to form a metal silicide layer. The method further comprises removing an unreacted portion of the metal layer on the metal silicide layer by a removal process. The removal process includes delivering a flow of an acidic solution to a surface of the unreacted portion of the metal layer, wherein the acidic solution delivered to the surface is substantially gas-free.

Abstract: A method of forming a line pattern array comprises the steps of setting a layout which includes first continuous line patterns arranged to have a first line width and a second continuous line pattern arranged to have a second line width larger than the first line width and positioned outside the first continuous line patterns; transferring the layout on a wafer; and inducing light scattering by changing an outermost pattern of the first continuous line patterns, which is most closely adjacent to the second continuous line patterns, into a plurality of dotted line patterns, wherein the plurality of the dotted patterns are arranged in a line form in order that a line pattern, which is different from the first continuous line patterns in line width, is formed based on a size of the dotted patterns.

Abstract: The present invention, in one aspect, provides a method of manufacturing a microelectronics device 100 that includes depositing a first gate dielectric layer 160 over a substrate 115, subjecting the first gate dielectric layer 160 to a first nitridation process, forming a second gate dielectric layer 165 over the substrate 115 and having a thickness less than a thickness of the first gate dielectric layer 160, and subjecting the first and second gate dielectric layers 160, 165 to a second nitridation process, wherein the first and second nitridation processes are different. The present invention also provides a microelectronics device 100 fabricated in accordance with the method.

Abstract: A semiconductor device including a semiconductor substrate; an element isolation region formed in the substrate including trenches formed at a first depth and being filled with an element isolation insulating film; an element forming region formed on the substrate and being surrounded by the trenches; a gate electrode formed along a first direction on the element forming region via a gate insulating film, the gate electrode extending over the element insulating film filled the trenches extending along a second direction; a source/drain region having a second depth less than the first depth formed in the element forming region beside the gate electrode and having an exposed surface exposed to a trench sidewall; wherein the upper surface of the element isolation insulating film exclusive of a portion underlying the gate electrode is located at a third depth greater than the second depth and less than the first depth.

Abstract: An integrated circuit having an active semiconductor device is formed comprising a trench defined by conductor lines previously formed.

Abstract: A power metal-oxide-semiconductor field effect transistor (MOSFET) cell includes a semiconductor substrate. A first electrode is disposed on the semiconductor substrate. A voltage sustaining layer is formed on the semiconductor substrate. A highly doped active zone of a first conductivity type is formed in the voltage sustaining layer opposite the semiconductor substrate. The highly doped active zone has a central aperture and a channel region that is generally centrally located within the central aperture. A terminal region of the second conductivity type is disposed in the voltage sustaining layer proximate the highly doped active zone. The terminal region has a central aperture with an opening dimension generally greater than an opening dimension of the central aperture of the highly doped zone. An extension region is disposed in the voltage sustaining region within the central aperture of the highly doped active zone.

Abstract: Dopants are implanted at relatively high energies into an unmasked first region of a semiconductor substrate through a thin layer of gate electrode material and a gate dielectric layer. Lower energy dopants are then implanted into the thin layer of gate electrode material. The first region is then masked off, and the process is repeated in a previously masked, but now unmasked, second region of the semiconductor substrate. A second (and usually thicker) layer of gate electrode material is then formed over the thin layer of gate electrode material. The layer of thick gate electrode material, the layer of thin gate electrode material and the layer of gate dielectric material are patterned to form one or more gate structures over the doped regions of the substrate. Source and drain regions are formed in the substrate regions adjacent to the gate structures to establish one or more MOS transistors.

Abstract: An integrated circuit includes a first and second diode connected in parallel. The first diode has a first breakdown voltage and has first P type region and first N type region adjacent to each other at the surface of the substrate of a substrate to form a lateral diode. The second diode has a second breakdown voltage less than the first breakdown voltage and has a second P type region and second N type region lateral adjacent to each other in the substrate to form a lateral diode below the surface The first and second N type regions overlap and the first and second P type region being electrically connected whereby the first and second diodes are in parallel.

Abstract: A sacrificial, self-aligned polysilicon interconnect structure is formed in a region of insulating material adjacent to an active region location and underlying a semiconductor device of a substrate assembly in order to electrically connect the active region and the semiconductor device. A preexisting geometry of the active region is maintained during etching of an interconnect structure hole in which the interconnect structure is formed and saves process steps. Under the method, a region of insulating material is formed immediately adjacent the active region location. A nitride layer is formed over the active region and protects the active region while an interconnect structure hole is etched partially into the region of insulating material adjacent the active region location with an etching process that is selective to the nitride layer. The interconnect structure hole is filled with polysilicon, the surface of the substrate assembly is planarized, and the nitride layer is removed.

Abstract: An ultrasound monitoring system. In one embodiment, an array of transducer cells is formed along a first plane and an integrated circuit structure, formed along a second plane parallel to the first plane, includes an array of circuit cells. A connector provides electrical connections between the array of transducer cells and the array of circuit cells, and an interconnection structure is connected to transfer signals between the circuit cells and processing and control circuitry. The integrated circuit structure includes a semiconductor substrate and a plurality of conductive through-die vias formed through the substrate to provide Input/Output (I/O) connections between the transducer cells and the interconnection structure. The monitoring system may be configured as an imaging system and the processing and control circuitry may be external to the probe unit.

Abstract: A micromechanical component has a substrate, a first intermediate layer which is situated thereupon, and a first layer which is situated thereupon and is structured down to the first intermediate layer. A second intermediate layer is situated above the first layer. A second layer is situated on the former, at least one movable micromechanical structure being structured into the second layer. The second intermediate layer is removed in a sacrificial zone beneath the movable micromechanical structure and the first intermediate layer is partially removed in zones beneath the first layer. The movable micromechanical structure is provided with at least one stop surface on a bottom face, this stop surface being contactable with a zone of the first layer which is supported by the first intermediate layer by deflection of the movable micromechanical structure. A method for producing such a micromechanical component is also described.

Abstract: A substrate-level assembly having a device substrate of semiconductor material with a top face and housing a first integrated device, including a buried cavity formed within the device substrate, and with a membrane suspended over the buried cavity in the proximity of the top face. A capping substrate is coupled to the device substrate above the top face so as to cover the first integrated device in such a manner that a first empty space is provided above the membrane. Electrical-contact elements electrically connect the integrated device with the outside of the substrate-level assembly. In one embodiment, the device substrate integrates at least a further integrated device provided with a respective membrane, and a further empty space, fluidically isolated from the first empty space, is provided over the respective membrane of the further integrated device.

Abstract: A low-temperature inorganic dielectric ALD film (e.g., Al2O3 and TiO2) is deposited on a packaged or unpackaged chip device so as to coat the device including any exposed electrical contacts. Such a low-temperature ALD film generally can be deposited without damaging the packaged chip device. The ALD film is typically deposited at a sufficient thickness to provide desired qualities (e.g., hermeticity for the entire packaged chip device, passivation for the electrical contacts, biocompatibility, etc.) but still allow for electrical connections to be made to the electrical contacts (e.g., by soldering or otherwise) directly through the ALD film without having to expose the electrical contacts.