Abstract: A photodetector comprising: at least one electron transporting organic material; and at least one hole transporting material, wherein said at least one electron transporting organic material has an ionization potential of more than 5.5 eV.

Abstract: An organic semiconductor device includes a channel forming region including an organic semiconductor thin film which is composed of an organic semiconductor material having an oxidation or reduction mechanism in units of two-?-electrons and a two- or three-dimensional conduction path. It is thus possible to provide an organic semiconductor device including an organic semiconductor thin film based on an organic semiconductor thin film composed of an organic semiconductor material which can be dissolved in an organic solvent at a low temperature (e.g., room temperature) and is suitable for use in a coating process.

Abstract: Improved processing methods for enhanced properties of conjugated polymer films are disclosed, as well as the enhanced conjugated polymer films produced thereby. Addition of low molecular weight alkyl-containing molecules to solutions used to form conjugated polymer films leads to improved photoconductivity and improvements in other electronic properties. The enhanced conjugated polymer films can be used in a variety of electronic devices, such as solar cells and photodiodes.

Abstract: In a thin film depositing apparatus, a first reaction gas, a second reaction gas, and a non-volatile gas are supplied to a reaction chamber in order to form a protective layer, in which an organic layer and an inorganic layer are alternately stacked, on a process substrate. The first reaction gas is supplied to the reaction chamber only while the inorganic layer is formed on the process substrate, and the second reaction gas and the non-volatile gas are supplied to the reaction chamber through while the inorganic and organic layers are formed on the process substrate. Thus, the discontinuous surfaces may be prevented from being formed between the organic layer and the inorganic layer, thereby preventing the peeling of the organic and inorganic layers and increasing light transmittance.

Abstract: An organic light emitting diode (OLED) display device and a method of fabricating the same capable of minimizing the number of process operations and a decrease in aperture ratio. The OLED display device includes a compensation circuit to compensate for a threshold voltage of a driving transistor. A pixel circuit of the OLED display device can be stably driven, can minimize a threshold voltage of a driving transistor using a minimized structure, and can increase an aperture ratio of the display device.

Abstract: This invention provides an organic thin film transistor, which can realize the modification of the surface of a gate insulating layer not only the case where the gate insulating layer is formed of an oxide, but also the case where the gate insulating layer is formed of a material other than the oxide and consequently can significantly improve transistor characteristics, and a method for surface modification of a gate insulating layer in the organic thin film transistor. In an organic thin film transistor comprising a gate insulating layer, an organic semiconductor layer stacked on the gate insulating layer, and an electrode provided on the organic semiconductor layer, a polyparaxylylene layer formed of a continuous polyparaxylylene film is formed on the surface of the gate insulating layer, between the gate insulating layer and the organic semiconductor layer, so as to face and contact with the organic semiconductor layer.

Abstract: An n-type TFT and a p-type TFT are realized by selectively changing only a cover coat without changing a TFT material using an equation for applying the magnitude of a difference in the Fermi energy between an interface of semiconductor and an electrode and between an interface of semiconductor and insulator. At this time, in order to configure a predetermined circuit, the process is performed, as a source electrode and a drain electrode of the p-type TFT and a source electrode and a drain electrode of the n-type TFT being connected all, respectively, and an unnecessary interconnection is cut by irradiating light using a scanning laser exposure apparatus or the like.

Abstract: An embodiment of the invention provides an integrated circuit having an organic field effect transistor (OFET) with a dielectric layer. The dielectric layer is prepared from a polymer formulation comprising: about 100 parts of at least one crosslinkable base polymer, from about 10 to about 20 parts of at least one di- or tribenzyl alcohol compound as an electrophilic crosslinking component, from about 0.2 to about 10 parts of at least one photo acid generator, and at least one solvent. Another embodiment provides a semiconductor fabrication method. The method comprises applying the polymer formulation to a surface of a substrate, drying the polymer formulation, crosslinking the polymer formulation after drying, and baking the polymer formulation after crosslinking.

Abstract: Provided is a zinc (Zn) oxide-based thin film transistor that may include a gate, a gate insulating layer on the gate, a channel including zinc oxide and may be on a portion of the gate insulating layer, and a source and drain contacting respective sides of the channel. The zinc (Zn) oxide-based thin film transistor may further include a recession in the channel between the source and the drain, and a zinc oxide-based etchant may be used to form the recession.

Abstract: Oxide semiconductors and thin film transistors (TFTs) including the same are provided. An oxide semiconductor includes Zn atoms and at least one of Ta and Y atoms added thereto. A thin film transistor (TFT) includes a channel including an oxide semiconductor including Zn atoms and at least one of Ta and Y atoms added thereto.

Abstract: A method for monitoring a semiconductor fabrication process creates a wafer of semiconductor chips. Each chip has a one or more diodes. Each diode is addressable as part of an array, corresponds to a physical location of the chip, and is connected in series to a stack. The stack is composed of one ore more vertical interconnects and metal contacts. The diode and associated stack of vertical interconnects is addressed, and the current through each of the stacks of vertical interconnects in an array is measured.

Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

Abstract: A semiconductor apparatus includes: a substrate of single crystal silicon; a first device formed in a first region of a surface of the substrate; a first interlayer insulating film formed on the substrate; a polycrystalline silicon layer formed in a second region on the first interlayer insulating film; a second device formed in the polycrystalline silicon layer; a second interlayer insulating film formed on the first interlayer insulating film, the second interlayer insulating film covering the polycrystalline silicon layer; and a pad formed in a third region on the second interlayer insulating film. The second region includes at least part of a directly overlying zone of the first region. The third region includes at least part of a region which is the directly overlying zone of the first region and a directly overlying zone of the second region.

Abstract: An image sensor and a manufacturing method thereof are provided. The sensor includes a substrate, a bottom electrode, an intrinsic layer and a first conductive layer formed over the substrate, a diffusion barrier film formed over the first conductive layer, and an upper transparent electrode formed over the diffusion barrier film. Therefore, a vertical integration of a transistor circuitry and a photodiode can be provided. Further, the leakage current is prevented and the photosensitivity is increased by performing the plasma treatment on the first conductive layer. Due to the vertically integrated transistor circuitry and photodiode, the fill factor can approach 100%, and higher sensitivity compared with the related art having the same pixel size can be provided. The sensitivity of each unit pixel is not reduced, even though more complex circuitry is realized on the image sensor.

Abstract: A thin film transistor manufacturing method includes the steps of: forming a gate electrode, gate insulating film and amorphous silicon film in succession on an insulating substrate; forming a channel protective film only in the region which will serve as a channel region of the amorphous silicon film; and forming an n-plus silicon film and metal layer on top of the channel protective film and amorphous silicon film in succession. The method further includes the step of patterning the amorphous silicon film and n-plus silicon film to selectively leave the region associated with source and drain electrodes, using the channel protective film as an etching stopper to selectively remove the region of the n-plus silicon film and metal layer associated with the channel region so as to form source and drain regions from the n-plus silicon film and also form source and drain electrodes from the metal layer.

Abstract: Oxide semiconductors and thin film transistors (TFTs) including the same are provided. An oxide semiconductor includes Zn atoms and at least one of Hf and Cr atoms added thereto. A thin film transistor (TFT) includes a channel including an oxide semiconductor including Zn atoms and at least one of Hf and Cr atoms added thereto.

Abstract: An object of the present invention is to reduce an adverse effect of an atmosphere in a heat treatment device used in production of an electronic device, imparted on characteristics of the produced electronic device. To attain the object, an inner surface of the heat treatment device is covered with an oxide passive-state film and bringing the surface roughness of the inner surface to 1 ?m or less in terms of a central mean roughness Ra. According to this type of heat treatment device, in curing a heat curable resin, deterioration in the heat curable resin caused by decomposition or dissociation of the heat curable resin, can be reduced.

Abstract: A resin material having a small relative dielectric constant is used as a layer insulation film 114. The resin material has a flat surface. A black matrix or masking film for thin film transistors is formed thereon using a metal material. Such a configuration prevents the problem of a capacity generated between the masking film and a thin film transistor.

Abstract: Disclosed herein is a TFT substrate which exhibits good characteristic properties despite the omission of the barrier metal layer to be normally interposed between the source-drain electrodes and the semiconductor layer in the TFT. The TFT substrate permits sure and direct connection with the semiconductor layer of the TFT. The thin film transistor substrate has a substrate, a semiconductor layer and source-drain electrodes. The source-drain electrodes are composed of oxygen-containing layers and thin films of pure copper or a copper alloy. The oxygen-containing layer contains oxygen such that part or all of oxygen combines with silicon in the semiconductor layer. And, the thin films of pure copper or a copper alloy connect with the semiconductor layer of the thin film transistor through the oxygen-containing layers.

Abstract: Improves the electric current driving capability of a thin film transistor without the yield being decreased due to a defective leak between a source electrode/drain electrode and a gate electrode or due to a decrease in an off-characteristic. A thin film transistor according to the present invention includes a gate electrode; an insulating film covering the gate electrode; a semiconductor layer provided on the insulating film; and a source electrode and a drain electrode provided on the insulating film and the semiconductor layer. The insulating film is a multiple layer insulating film including a first insulating layer and a second insulating layer provided on the first insulating layer. The multiple layer insulating film has a low stacking region excluding the first insulating layer and a high stacking region in which the first insulating layer and the second insulating layer are stacked. The first insulating layer is provided so as to cover at least an edge of the gate electrode.

Abstract: It is an object of the present invention to prevent an influence of voltage drop due to wiring resistance, trouble in writing of a signal into a pixel and trouble in gray scales, and provide a display device with higher definition, represented by an EL display device and a liquid crystal display device. In the present invention, a wiring including Cu is provided as an electrode or a wiring used for the display device represented by the EL display device and the liquid crystal display device. Besides, sputtering is performed with a mask to form the wiring including Cu. With such structure, it is possible to reduce the voltage drop and a deadened signal.

Abstract: Shrinking the dimensions of PMOS or NMOS thin film transistors is limited by dopant diffusion. In these devices an undoped or lightly doped channel region is interposed between heavily doped source and drain regions. When the device is built with very short gate length, source and drain dopants will diffuse into the channel, potentially shorting it and ruining the device. A suite of innovations is described which may be used in various combinations to minimize dopant diffusion during fabrication of a PMOS or NMOS polycrystalline thin film transistor, resulting in a highly scalable thin film transistor. This transistor is particularly suitable for use in a monolithic three dimensional array of stacked device levels.

Abstract: A method of fabricating a polycrystalline silicon (poly-Si) layer includes providing a substrate, forming an amorphous silicon (a-Si) layer on the substrate, forming a thermal oxide layer to a thickness of about 10 to 50 ? on the a-Si layer, forming a metal catalyst layer on the thermal oxide layer, and annealing the substrate to crystallize the a-Si layer into the poly-Si layer using a metal catalyst of the metal catalyst layer. Thus, the a-Si layer can be crystallized into a poly-Si layer by a super grain silicon (SGS) crystallization method. Also, the thermal oxide layer may be formed during the dehydrogenation of the a-Si layer so that an additional process of forming a capping layer required for the SGS crystallization method can be omitted, thereby simplifying the fabrication process.

Abstract: [Problem] A TFT is manufactured using at least five photomasks in a conventional liquid crystal display device, and therefore the manufacturing cost is high. [Solving Means] By performing the formation of the pixel electrode 127, the source region 123 and the drain region 124 by using three photomasks in three photolithography steps, a liquid crystal display device prepared with a pixel TFT portion, having a reverse stagger type n-channel TFT, and a storage capacitor can be realized.

Abstract: Affords a Group III nitride semiconductor device having a structure that can improve the breakdown voltage. A Schottky diode (11) consists of a Group III nitride support substrate (13), a gallium nitride region (15), and a Schottky electrode (17). The Group III nitride support substrate (13) has electrical conductivity. The Schottky electrode (17) forms a Schottky junction on the gallium nitride region (15). The gallium nitride region (15) is fabricated on a principal face (13a) of the Group III nitride support substrate (13). The gallium nitride region (15) has a (10 12)-plane XRD full-width-at-half-maximum of 100 sec or less.

Abstract: A GaN-based semiconductor layer is stacked on a GaN-based single-crystal substrate. The GaN-based single-crystal substrate forms an electron transit layer, and the GaN-based semiconductor layer forms an electron supply layer. A principal growth plane of the GaN-based single-crystal substrate is an m-plane, and a principal growth plane of the GaN-based semiconductor layer formed on the GaN-based single-crystal substrate is also an m-plane. With such a layer structure, no piezoelectric field is generated since the m-plane is a nonpolar plane. This suppresses generation of a two-dimensional electron gas layer at the time when no gate voltage is applied and consequently enables achievement of a normally-off configuration.

Abstract: A SiC device includes: a substrate; a drift layer; a base region; a source region; a channel layer connecting the drift layer and the source region; a gate oxide film on the channel layer and the source region; a gate electrode on the gate oxide film; an interlayer insulation film with a contact hole having a barrier layer and a BPSG insulation film on the gate electrode; a source electrode having upper and lower wiring electrodes on the interlayer insulation film and in the contact hole for connecting the base region and the source region; and a drain electrode on the substrate. The barrier layer prevents a Ni component in the lower wiring electrode from being diffused into the BPSG insulation film.

Abstract: One embodiment of the present invention provides a method for fabricating a group III-V p-type nitride structure. The method comprises growing a first layer of p-type group III-V material with a first acceptor density in a first growing environment. The method further comprises growing a second layer of p-type group III-V material, which is thicker than the first layer and which has a second acceptor density, on top of the first layer in a second growing environment. In addition, the method comprises growing a third layer of p-type group III-V material, which is thinner than the second layer and which has a third acceptor density, on top of the second layer in a third growing environment.

Abstract: A method for making an electroluminescent PN junction includes molecular bonding a face in a crystalline semiconducting material doped with a first type of a first element with a face in a crystalline semiconducting material doped with a second type opposite to the first type, of a second element, at a bonding interface. The semiconducting material has an indirect forbidden band. The crystalline lattices shown by the faces are shifted in rotation by a predetermined angle so as to at least cause formation of a network of screw type dislocations at the bonding interface.

Abstract: Standard solderless connectors extend from a molded package body supporting at least one high power LED. The package includes a relatively large metal slug extending completely through the package. The LED is mounted over the top surface of the metal slug with an electrically insulating ceramic submount in-between the LED and metal slug. Electrodes on the submount are connected to the package connectors. Solderless clamping means, such as screw openings, are provided on the package for firmly clamping the package on a thermally conductive mounting board. The slug in the package thermally contacts the board to sink heat away from the LED. Fiducial structures (e,g., holes) in the package precisely position the package on corresponding fiducial structures on the board. Other packages are described that do not use a molded body.

Abstract: A semiconductor module (A1) comprises a semiconductor device (10) provided with a semiconductor chip, and a conductive cover (6) for electromagnetic shielding bonded to the semiconductor device (10) via an adhesive coat (8). The conductive cover (6) includes a surface facing the adhesive coat (8), and the surface is formed with a convex portion (6a) protruding toward the adhesive coat (8). Around the convex portion (6a), a space (7) is formed for filling in adhesive to form the adhesive coat (8).

Abstract: The present invention improves the efficiency of conversion from a non-radiation two-dimensional electron plasmon wave into a radiation electromagnetic wave, and realizes a wide-band characteristic. A terahertz electromagnetic wave radiation element of the present invention comprises a semiinsulating semiconductor bulk layer, a two-dimensional electron layer formed directly above the semiconductor bulk layer by a semiconductor heterojunction structure, source and drain electrodes electrically connected to two opposed sides of the two-dimensional electron layer, a double gate electrode grating which is provided in the vicinity of and parallel to the upper surface of the two-dimensional electron layer and for which two different dc bias potentials can be alternately set, and a transparent metal mirror provided in contact with the lower surface of the semiconductor bulk layer, formed into a film shape, functioning as a reflecting mirror in the terahertz band, and being transparent in the light wave band.

Abstract: This invention relates to a solid-state light source (100) comprising a first active region (110) for emitting an excitation light (102) and a second active region (120) for emitting a primary light (104), and a conversion element (130) for substantially converting the excitation light (102) into a secondary light (104). The primary light (104) and the secondary light (106) are mixed to produce light of a desired color point, in particular white light, with a predetermined color temperature.

Abstract: An exemplary illuminator includes a first electrode, a second electrode, and a light-emitting chip. The light-emitting chip includes light-emitting layers arranged three-dimensionally. The first and second electrodes are configured for providing different voltages to the light-emitting chip, and the light-emitting chip is capable of emitting light simultaneously along all dimensional axes.

Abstract: A light emitting diode (LED) light source device includes a plurality of LED modules, a base and a clip. The base has a first base body, a second base body, and a third base body. The second base body and the third base body extend from two sides of the first base body and are corresponding to each other. The LED modules are provided at inside surfaces of the first base body, the second base body and the third base body. The clip holds the LED modules and fastens the second base body and the third base body to enable the LED modules to be tightly assembled at the base.

Abstract: In one embodiment of an epitaxial LED device, a buffer layer (e.g. dielectric layer) between the current spreading layer and the substitute substrate comprises a plurality of vias and has a refractive index that is below that of the current spreading layer. A reflective metal layer between the buffer layer and the substitute substrate is connected to the current spreading layer through the vias in the buffer layer. The buffer layer separates the current spreading layer from the reflective metal layer. In yet another embodiment, stress management is provided by causing or preserving stress, such as compressive stress, in the LED so that stress in the LED is reduced when it experiences thermal cycles.

Abstract: A method of fabricating a nitride-based semiconductor device capable of reducing contact resistance between a nitrogen face of a nitride-based semiconductor substrate or the like and an electrode is provided. This method of fabricating a nitride-based semiconductor device comprises steps of etching the back surface of a first semiconductor layer consisting of either an n-type nitride-based semiconductor layer or a nitride-based semiconductor substrate having a wurtzite structure and thereafter forming an n-side electrode on the etched back surface of the first semiconductor layer.

Abstract: A semiconductor light emitting device and a method of manufacturing the same are provided. The semiconductor light emitting device comprises a substrate, a mask seed layer formed on the substrate and comprising a TI group element, a nitride layer formed on the mask seed layer and comprising a III group element, a first conductive semiconductor layer on the nitride layer, an active layer on the first conductive layer, and a second conducive semiconductor layer on the active layer.

Abstract: Provided is a light emitting device comprising a first conductive type semiconductor layer, an active layer, a semiconductor layer comprising Al, a high-concentration semiconductor layer, a low-mole InxGa1?xN layer, and a second conductive type semiconductor layer. The active layer is on the first conductive type semiconductor layer and emits light. The semiconductor layer comprising Al is on the active layer. The high-concentration semiconductor layer is on the semiconductor layer comprising Al. The low-mole InxGa1?xN layer is on the high-concentration semiconductor layer. The second conductive type semiconductor layer is on the low-mole InxGa1?xN layer.

Abstract: Provided are a light emitting device and a method of fabricating the same, The light emitting device comprises: a first conductive semiconductor layer; an active layer comprising an InGaN well layer and a GaN barrier layer on the first conductive semiconductor layer; and a second conductive semiconductor layer on the active layer. The GaN barrier layer comprises an AlGaN layer.

Abstract: Provided are a semiconductor light emitting device and a method of manufacturing the same. The semiconductor light emitting device comprises a p-type substrate, a p-type semiconductor layer, an active layer, and an n-type semiconductor layer. The p-type semiconductor layer is formed on the p-type substrate. The active layer is formed on the p-type semiconductor layer. The n-type semiconductor layer is formed on the active layer.

Abstract: A light emitting diode structure including a substrate, a strain-reducing seed layer, an epitaxial layer, a first electrode and a second electrode is provided. The strain-reducing seed layer having a plurality of clusters is disposed on the substrate, and the material of the clusters is selected from a group consisting of aluminum nitride, magnesium nitride and indium nitride. The epitaxial layer includes a first type doped semiconductor layer, a light emitting layer and a second type doped semiconductor layer. The first electrode is disposed on the exposed first type doped semiconductor layer and electrically connected thereto. The second electrode is disposed on the second type doped semiconductor layer and electrically connected thereto.

Abstract: A light-emitting diode arrangement is disclosed, comprising at least one light-emitting diode (LED) chip with a radiation decoupling surface through which a large portion of the electromagnetic radiation generated in the LED chip exits in a main direction of emission; a housing laterally surrounding the LED chip; and a reflective optic disposed after the radiation decoupling surface in the main direction of emission. The LED arrangement is particularly well suited for use in devices such as camera-equipped cell phones, digital cameras or video cameras.

Abstract: Low profile, side-emitting LEDs are described that generate white light, where all light is emitted within a relatively narrow angle generally parallel to the surface of the light-generating active layer. The LEDs enable the creation of very thin backlights for backlighting an LCD. In one embodiment, the LED emits blue light and is a flip chip with the n and p electrodes on the same side of the LED. Separately from the LED, a transparent wafer has deposited on it a red and green phosphor layer. The phosphor color temperature emission is tested, and the color temperatures vs. positions along the wafer are mapped. A reflector is formed over the transparent wafer. The transparent wafer is singulated, and the phosphor/window dice are matched with the blue LEDs to achieve a target white light color temperature. The phosphor/window is then affixed to the LED.

Abstract: Disclosed herein is an electrical light-emitting device including a transparent conductive nanorod type electrode, in which transparent conductive nanorods grown perpendicular to a light-emitting layer are used as the electrode. Hence, light is not absorbed by the electrode, and tunneling easily occurs due to nanocontact of the nanorods, thus increasing current injection efficiency, and also, total internal reflections decrease. Thereby, the light-emitting device according to this invention has light-emitting properties and luminous efficiency superior to conventional light-emitting devices, including metal electrodes or thin film type transparent electrodes.

Abstract: An electronic component package, includes a package substrate portion constructed by a silicon substrate in which a through hole is provided, an insulating layer formed on both surface sides of the silicon substrate and an inner surface of the through hole, and a through electrode filled in the through hole, and a frame portion provided upright on a peripheral portion of the package substrate portion to constitute a cavity on the silicon substrate, wherein an upper surface of the through electrode in the cavity is planarized such that a height of the through electrode is set equal to a height of the insulating layer. The frame portion is joined to the package substrate portion by the low-temperature joining utilizing the plasma process after the through electrode is planarized.

Abstract: A light source of the present invention includes: a semiconductor light emitting device which has a light emitting face and emits light from part of the light emitting face; a container which has a light transmitting window for transmitting the light and accommodates the semiconductor light emitting device; and a gettering portion for performing gettering of a material containing at least one of carbon and silicon. The gettering portion is positioned, in the container, in a region other than the part of the light emitting face of the semiconductor light emitting device.

Abstract: A light-generating semiconductor region is grown on a substrate of electroconductive silicon or like light-absorptive material. An anode is placed atop the light-generating semiconductor region, and a cathode under the substrate. The light-generating semiconductor region and the substrate are encapsulated in an epoxy envelope. In order to prevent the substrate from absorbing the light that has been radiated from the light-generating semiconductor region and reflected back from the envelope, the substrate has its side surfaces covered by a reflector layer. The reflector layer has its surfaces roughened, as a result of the roughening of the underlying substrate surfaces by dicing, for scattering the incident light.

Abstract: Provided is a semiconductor light emitting device. The semiconductor light emitting device comprises a first conductive type semiconductor layer, an active layer, a second conductive type super lattice layer, and a second conductive type semiconductor layer. The active layer is formed on the first conductive type semiconductor layer. The second conductive type super lattice layer comprises a second conductive type nitride layer and an undoped nitride layer on the active layer. The second conductive type semiconductor layer is formed on the second conductive type super lattice layer.

Abstract: New combinations of semi-conductor devices in conjunction with optically active materials are set forth herein. In particular, light emitting semiconductors fashioned as diodes from indium gallium nitride construction are combined with high-performance optically active Langasite La3GasSi0i4 crystalline materials. When Langasite is properly doped, it will respond to the light output emissions of the diode by absorbing high energy photons therefrom and reemitting light of longer wavelengths. High-energy short wavelength light mixes with the longer wavelengths light to produce a broad spectrum which may be perceived by human observers as white light. Langasite, a relatively new material, enjoying great utility in frequency control and stabilization schemes has heretofore never been used in combination with optical emission systems.