Abstract: A testing device (1) for lighting means (3) operated at a nominal voltage (Vn) and at a nominal frequency (fn), having a capacitive coupling of a test voltage (Vp) at a testing frequency of (fp) to the lighting means (3), wherein a coupled test voltage (Vpa) corresponds to the nominal voltage (Vn), and a coupled test frequency (fpa) corresponds to the nominal frequency (fn).

Abstract: A detection apparatus for detecting the presence of a sample, the detection apparatus comprising a chamber, ports for introducing a sample within the chamber, an actuation unit for establishing a controllable electromagnetic field in the chamber; and a sensing unit for sensing changes in the electromagnetic field due to the presence of the sample within the chamber. The sensing unit comprises a sensor device comprising a source and a drain embedded in a FET a gate for the FET, in which the gate is formed of a material whose conductivity is related to the electromagnetic field established in a nonconductive medium in contact with the gate.

Abstract: A method and apparatus for operating a multi-hot-cathode ionization gauge is provided to increase the operational lifetime of the ionization gauge in gaseous process environments. In example embodiments, the life of a spare cathode is extended by heating the spare cathode to a temperature that is insufficient to emit electrons but that is sufficient to decrease the amount of material that deposits on its surface or is optimized to decrease the chemical interaction between a process gas and a material of the at least one spare cathode. The spare cathode may be constantly or periodically heated. In other embodiments, after a process pressure passes a given pressure threshold, plural cathodes may be heated to a non-emitting temperature, plural cathodes may be heated to a lower emitting temperature, or an emitting cathode may be heated to a temperature that decreases the electron emission current.

Abstract: Inventive subject matter described herein includes an induction coil resistance tester, comprising: a base effective for absorbing vibration; a mechanism for moving a sample in x, y, and z directions; a scale for measuring weight of the sample; and an ohmmeter for measuring resistance of the sample.

Abstract: A loopback connector for a system can include a connector arrangement connectable to connector of a system component and/or a cable. The loopback connector can include loopback logic for simulating cable and/or system component functionality. In an example implementation the loopback connector can also operate to protect a system component and/or cable connector during shipping.

Abstract: An image display device includes a black spot defect position determination circuit which determines a position of a black-spot defective pixel of a self-luminous display panel. A detection-use current source in the black spot defect position determination circuit is connected to pixels during a period separate from a display period of data signals thus determining a black spot defect. The position of the black spot defect is stored in a storing circuit and is transmitted to a display and detection control circuit. The display and detection control circuit corrects the data signals to the pixels around the defective pixel based on a black spot defect position, and drives a data line drive circuit based on the corrected data signals thus visually correcting the black spot defect.

Abstract: A Transmission Line Pulse (TLP) testing system is disclosed that has a negative pulse inverter circuit that prevents large negative reflections which typically occur after the initial TLP pulse is applied to a low impedance device under test (DUT). Avoiding repetitive reflections, which naturally occur in TLP systems, prevents inducing DUT damage and confusing testing results. The pulse inverter circuit reduces reflections to lower levels than prior art TLP configurations, and can also be combined with known techniques to further reduce reflections for different impedance DUTs.

Abstract: A method of testing for shorts between nodes of a circuit assembly includes parsing circuit design data to identify positional data for nodes of a circuit assembly, and using the positional data to classify ones of the nodes as members of a supernode, where each member of the supernode is unlikely to be shorted to any other member of the supernode. Tests for shorts in a set of nodes that includes the supernode and a plurality of other nodes of the circuit assembly are then conducted, by iteratively i) stimulating a particular one of the set of nodes, and ii) while stimulating the particular node, grounding at least one other node in the set of nodes and monitoring a current flow through the particular node. When stimulating or grounding a supernode, all of the nodes that are members of the supernode are stimulated or grounded. If a current flow is detected through one of the stimulated nodes, the circuit assembly is indicated to be defective. Other embodiments are also disclosed.

Abstract: A contact and a connecting apparatus are provided to enable miniaturization and shortening and cost reduction in response to further miniaturization and finer pitch of inspection objects. The contact is one electrically for contacting a terminal of a wire and includes a one-side plunger portion, an other-side plunger portion, and an elastic deformation portion provided between the plunger portions. The elastic deformation portion is made of an annular and conductive elastic member integrally connected to the one-side plunger portion and the other-side plunger portion. The plurally arranged elastic deformation portions are disposed in a zigzag shape in the up-down direction with their adjacent heights different from each other. The connecting apparatus includes the plurality of contacts electrically contacting terminals disposed on an inspection object and a contact plate for integrally supporting the respective contacts to make the contacts contact with the respective terminals of the inspection object.

Abstract: The invention relates to a testing adapter suitable for testing a wireless telecommunication device. The testing adapter comprises a first contact member and a second contact member, the first contact member and the second contact member having at least one degree of freedom relative to each other and arranged to provide an attachable and detachable mechanical coupling with a surface of a component recess of the wireless telecommunication device on the basis of the at least one degree of freedom.

Abstract: There is provided a test method for detecting the presence or absence of a defect in a spark plug insulator, including a reference voltage determination process, a test area determination process, a test voltage determination process and a current detection process. In the reference voltage determination process, a reference voltage VF is determined. In the test area and voltage determined processes, test area and voltage are determined so as not to incur a flashover on the basis of a reference insulator of the same material, shape and size as the spark plug insulator when the reference insulator is placed in position between first and second test electrodes. In the current detection step, the test voltage is applied between the first and second test electrodes to detect an electric current between the first and second test electrodes.

Abstract: A system and technique for measuring the mutual inductance in a switched reluctance machine (SRM). In a first example embodiment of the technique, a voltage pulse is applied to primary coil when the machine is stationery. By measuring current in the primary coil and measuring induced voltages in adjacent open circuited coils mutual inductance may be determined. In another example embodiment, a voltage pulse is applied to the primary coil when the machine is stationery. The secondary coil is allowed to freewheel current through the phase. By measuring time taken by the primary phase to reach a preset value, the mutual inductance for the known position of a rotor can be determined.

Abstract: Inventive subject matter described herein includes an induction coil resistance tester, comprising: a base effective for absorbing vibration; a mechanism for moving a sample in x, y, and z directions; a scale for measuring weight of the sample; and an ohmmeter for measuring resistance of the sample.

Abstract: Methods, systems, and computer program products are disclosed for acquiring test data from an electronic circuit by mounting a probe adjacent to a capture point on an electronic circuit board, capturing by the probe an electronic signal of the electronic circuit, digitizing by the probe the captured signal, and transmitting by the probe the digitized signal from the probe through a data communications connection to a remote device. Acquiring test data from an electronic circuit also includes storing by the probe the digitized signal in the probe. Acquiring test data from an electronic circuit may include processing by the probe the digitized signal. Acquiring test data from an electronic circuit also may include synchronizing acquisition of test data by the probe with acquisition of test data by one or more other probes.

Abstract: A test apparatus for testing a semiconductor device having contact pads on its top and its back, and to a method for testing the semiconductor device is disclosed. In one embodiment, the test apparatus has a test socket which is mounted on a test printed circuit board. Internal through-contact elements of the test socket can be used to test contact pads on the top of the semiconductor device. The contact pads on the back of the semiconductor device can be connected for the purpose of testing the semiconductor device using external through-contact elements which are arranged outside of the locating seat.

Abstract: A test socket assembly is for use in testing integrated circuits. A single piece socket is formed substantially of an insulating material and having a plurality of holes formed therein configured to receive a plurality of electrically conductive springs. Each hole of the single piece socket has therein a separate one of the electrically conductive springs. A test socket includes a plurality of pins configured to receive leads of an integrated circuit, the pins of the test socket extending into the plurality of holes of the single piece socket with each pin engaging a spring, wherein the single piece socket is positioned on a circuit board with the plurality of holes being in alignment with electrical contacts on the circuit board such that the plurality of springs are electrically interconnecting the contacts and the plurality of pins. The single -piece socket is comprised substantially of a high-temperature insulating material, such as ceramic.

Abstract: The present invention provides a multilayer wiring board in which resistive elements each of whose error from a desired value is smaller than in a conventional case are built, a method for manufacturing the same, and a probe apparatus utilizing the multilayer wiring board. The present invention is based on a basic concept of forming a flat surface on a surface of a multilayer wiring layer on which a resistive element material is to be deposited and depositing the resistive element material on the flat surface.

Abstract: A test device to be connected to a multi-card slot of an electronic apparatus performs test for connection between a card inserted into the multi-card slot and the multi-card slot with a plurality of connection terminals. The test device includes a test card and a connection unit. The test card includes a plurality of contact portions to be connected to all of the plurality of connection terminals of the multi-card slot and is inserted into the multi-card slot. The connection unit includes the plurality of cards and connects the plurality of cards to the test card.

Abstract: A method is disclosed for measurement of wafers and other semiconductor components in a probe station, which serves for examination and testing of electronic components. The device under test is held by a chuck and at least one electric probe by a probe support and the device under test and the probe are selectively positioned relative to each other by a positioning device with electric drives and the device under test is contacted. The drive of the positioning device remains in a state of readiness until establishment of contact and is switched off after establishment of contact and before measurement of the device under test.

Abstract: A probe card registration method is for registering a probe card for use in inspecting electrical characteristics of a target object in a probe apparatus for performing the inspecting. The probe card registration method includes detecting a height of a load sensor provided at a mounting table for mounting thereon the target object by using a first imaging unit disposed above the mounting table; contacting the load sensor with a probe by moving the load sensor by the mounting table; and stopping the movement of the load sensor when the load sensor starts to make contact with the probe. The method further includes calculating a height of a needle of the probe based on a height of the load sensor and a stop height thereof.

Abstract: The present invention provides an electrical connecting apparatus that does not cause lack of mechanical strength in a probe board. The electrical connecting apparatus comprises a probe board spaced from a support member and arranged with its one surface opposed to the support member. On one surface of the probe board is provided a fixed portion having an opened screw hole at its top portion, and on the other surface are provided probes that are connected to a tester. The electrical connecting apparatus comprises a cylindrical spacer keeping a distance from the support member to a top surface of the fixed portion and a male screw member screwed in the screw hole for the purpose of tightening the support member and the probe board at a distance in accordance with the length of the spacer.

Abstract: A system is provided that facilitates locating long dangling metal routes in a semiconductor chip design. The system includes mechanisms for partitioning metal features of the chip design to discover dangling metal routes that could be potential violations. The system further comprises mechanisms for determining if the dangling metal routes of the chip design exceed a length limit that could result antenna violations, undesired noise in the circuit, circuitry breakdown or the like. The system enables excessively long dangling metal routes to be allowed as exceptional cases. Machine learning is provided to receive feedback to refine the exceptional cases and enable more efficient fault detection.

Abstract: An electronic circuit includes an output terminal and at least a first measuring FET. The second drain-source terminals of a plurality of FETS to be tested are interconnected with the first drain-source terminal of the first measuring FET and the output terminal. The second drain-source terminal of the first measuring FET is interconnected with a first biasing terminal. The first drain-source terminals of the FETS to be tested are interconnected with a second biasing terminal. A state machine is coupled to the gates of the FETS to be tested and the gate of the first measuring FET. The state machine is configured to energize the gate of the first measuring FET and to sequentially energize the gates of the FETS to be tested, so that an output voltage appears on the output terminal. Circuitry to compare the output voltage to a reference value is also provided.

Abstract: Each sensor of a linear array of sensors includes, in part, a sensing electrode and an associated feedback circuit. The sensing electrodes are adapted to be brought in proximity to a flat panel having formed thereon a multitude of pixel electrodes in order to capacitively measure the voltage of the pixel electrodes. Each feedback circuit is adapted to actively drive its associated electrode via a feedback signal so as to maintain the voltage of its associated electrode at a substantially fixed bias. Each feedback circuit may include an amplifier having a first input terminal coupled to the sensing electrode and a second input terminal coupled to receive a biasing voltage. The output signal of the amplification circuit is used to generate the feedback signal that actively drives the sensing electrode. The biasing voltage may be the ground potential.

Abstract: A method of detecting a malfunction of an encoder used in a vehicle drive system includes determining an error of a motor speed based on an estimated motor speed, wherein the estimated motor speed is a function of measured current over a predetermined interval of time. The method further includes determining a maximum allowable error of the motor speed at the measured current. Yet further, the method includes comparing the error of the motor speed with the maximum allowable error of the motor speed, thereby detecting the malfunction of the encoder.

Abstract: An indicator rod responsive to environmental variations is disclosed. A handle defines an elongated cavity having a linear axis. A pin is received within the cavity substantially along the linear axis, and is adapted to rotate about the linear axis. An indicator member is secured to the pin such that the pin extends in a substantially non-parallel orientation from the indicator member.

Abstract: In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.

Abstract: According to an aspect of an embodiment, a logic circuit includes a first master latch included in one of the master-slave flip-flop circuits, the first master latch having a first scan data input for receiving scan data, the first master latch latching the scan data and outputting latched scan data, a second master latch included in another of the master-slave flip-flop circuits, the second master latch having a second scan data input operatively connected to receive an output of the first master latch, the second master latch latching the scan data inputted into the second scan data input and outputting latched scan data and a slave latch included in one of the master-slave flip-flop circuits, the slave latch having a scan data input operatively connected to receive an output of the second master latch.

Abstract: An apparatus for measuring an on-die termination (ODT) resistance includes an ODT controller and a driver. The ODT controller receives a plurality of decoding signals, a first test mode signal, and a second test mode signal to generate a plurality of pull-up signals and a plurality of pull-down signals. The pull-up signals are enabled in response to the decoding signals and the first test mode signal, and the pull-down signals are enabled in response to the decoding signals and the second test mode signal. The driver receives the pull-up signals and the pull-down signals to drive a data terminal. At least one of the decoding signals is enabled by a mode register set (MRS) for setting an ODT mode.

Abstract: A data transmission device may include a transmission chip, a plurality of reception chips and/or a pair of transmission lines. The transmission chip may transmit data and the reception chips may receive the data from the transmission chip. One of the plurality of reception chips may provide a corresponding terminal resistance when it receives the data. The transmission lines may be coupled between the transmission chip and the reception chips, and the transmission lines may have a daisy-chain configuration. Therefore, a data transmission device may provide a fixed terminal resistance in impedance matching and increase a transmission speed.

Abstract: When a plurality of output buffer circuits are provided, chip layout size, power consumption, and number of pins of an LSI circuit are reduced. A voltage generation circuit generates reference voltages corresponding respectively to the output buffer circuits. A comparison circuit compares the reference voltages with an output voltage of a dummy buffer circuit. A counter counts a clock signal until a comparison result of the comparison circuit matches. The dummy buffer circuit adjusts output impedance corresponding respectively to the output buffer circuits based on a count value of the counter. Adjustment value holders hold respective count values when a comparison result of the comparison circuit, obtained based on respective corresponding reference voltages, matches. The output buffer circuits respectively adjust output impedances based on respectively held count values.

Abstract: A memory controller for controlling integrated circuit memory devices that have on-die termination. The memory controller includes an output driver to output a first data signal onto a data line, and termination control circuitry to output termination control signals to integrated circuit memory devices coupled to the data line. The termination control signals control coupling and decoupling of termination elements to the data line according to which of the plurality of integrated circuit memory devices is selected to receive the first data signal.

Abstract: Methods, devices, and systems for programmable computing arrays have been described. One or more embodiments include programming both a first and a second floating gate of a combined memory and logic element to one of at least two states, wherein programming the floating gates to one of the at least two states causes the combined memory and logic element to operate as a first logic gate type. One or more embodiments also include programming both the first and the second floating gates of the combined memory and logic element to another of the at least two states, wherein programming the floating gates to another of the at least two states causes the combined memory and logic element to operate as a second logic gate type, the second logic gate type being different from the first logic gate type.

Abstract: A thin-film logic circuit, which can be fabricated entirely of TFTs of the same conductivity type, includes a logic stage connected to a supply voltage and a level shifter connected to a wider voltage range provided by the supply voltage and ground. The logic circuit produces output signals with full rail-to-rail signal range from ground to the supply voltage and can implement or include a basic logic component such as an inverter, a NAND gate, or a NOR gate or more complicated circuits in which many basic logic components are cascaded together. Such logic circuits can be fabricated directly on flexible structures or large areas such as in flat panel displays.

Abstract: A number of logic state catching circuits are described which use a logic circuit with a first input, a second input, and an output. The logic circuit is configured to respond to a change in state of a data value coupled to the first input causing a representative value of the data value to be generated on the output. The second input receives a latched version of the data value to hold the representative value on the output after the data value has returned to its original state. A latching element is configured to respond to the change in state of the data value by latching the data value and to couple the latched version of the data value to the second input. A reset element is configured to respond to a change in state of a clock input by resetting the latching element.

Abstract: A signal encoder and a signal decoder involves the signal encoder for receiving a data signal and a clock signal, including a first code output terminal and a second code output terminal. When the data signal is logic one, the signal encoder outputs a modulated signal through the first code output terminal, and outputs a fixed level signal through the second code output terminal. When the data signal is logic zero, the signal encoder outputs the fixed level signal through the first code output terminal, and outputs the modulated signal through the second code output terminal. The signal decoder converts the modulated signal and the fixed level signal output from the signal encoder into the data signal and the clock signal.

Abstract: A digital frequency detector and a digital phase locked loop (PLL) are provided. The digital frequency detector includes a first conversion unit which outputs a first frequency as first frequency information of a digital type using a first ring oscillator that operates in a high-level period of the first frequency, a second conversion unit which outputs a second frequency as second frequency information of a digital type using a second ring oscillator that operates in a high-level period of the second frequency, and an operation unit which outputs a digital frequency for the first frequency by calculating a ratio of the first frequency information to the second frequency information.

Abstract: Briefly, in accordance with one or more embodiments, an offset compensated comparator is capable of being utilized for higher speed, lower voltage use. The comparator comprises a cross-coupled latch comprising n type devices and p type devices. The threshold mismatch between n type devices is captured on capacitors coupled to the gates of the n type devices to capture the mismatch between the devices. After the threshold mismatch is captured, the comparator can be used as a typical cross coupled latch.

Abstract: An interface such a PCI-E interface may comprise a transmitter and a compensation circuit. In one embodiment, the transmitter may comprise a transmit driver, which may use a push-pull configuration. The transmit driver may require stable voltages such as (Vdd/2+0.25) and (Vdd/2?0.25) Volts. The compensation circuit may comprise a voltage generator circuit and a dummy driver circuit. The dummy driver may be a replica of the transmit driver. A correction module may generate correction factors based on the deviation of the voltages generated by the dummy driver from the voltages generated by the voltage generator. The voltages provided to the transmit driver are corrected based on the correction factors to compensate for the deviation.

Abstract: A differential comparator is provided. The comparator receiving two differential signals and generating a comparison result represented by an output signal on one of two output terminals respectively on two current paths. The comparator comprises two pairs of latch transistors respectively disposed on the two current paths and two pairs of input transistors respectively disposed on the two current paths, wherein gates of the latch transistors on one of the current paths are commonly coupled to the output terminal between the latch transistors on the other current path, gates of the input transistors on one of the current paths respectively receives an input signal of one of the differential signals and a reference signal of the other differential signal and each of the input transistors is disposed between the output terminal and one of the latch transistors on the current path thereof.

Abstract: An apparatus includes a regulator circuit that generates a voltage in response to an input current being supplied to an input terminal and functional circuitry, powered by the voltage generated by the regulator circuit. The functional circuitry, e.g., an oscillator, generates a signal using the generated voltage, the signal indicative that the current is being supplied to the apparatus. The signal can be provided over an isolation link to provide a control signal for controlling a high voltage driver circuit.

Abstract: Disclosed is a frequency synthesizer. The frequency synthesizer includes a phase frequency detector for generating an up signal and a down signal by detecting frequency and phase differences between a reference signal and a comparison signal, a charge pump for outputting a control signal according to the up signal and the down signal, a voltage controlled oscillator for outputting an oscillation output signal according to the control signal, a duty cycle correction circuit connected with the voltage controlled oscillator to compensate for a duty cycle of the oscillation output signal, and a feedback divider for providing the comparison signal to the phase frequency detector by dividing a frequency of the oscillation output signal.

Abstract: A frequency adjusting apparatus includes a frequency control signal generating unit that generates a multi-bit frequency control signal, which is changed in level bit by bit, in response to a reference clock signal, and a frequency adjusting unit that adjusts the frequency of the reference clock signal in response to the multi-bit frequency control signal.

Abstract: An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels.

Abstract: A duty cycle correcting circuit for an integrated circuit memory automatically corrects the duty cycle of an input clock by measuring the relative difference between the high time and low time of the input signal and using this measurement to achieve a same-frequency, duty cycle adjusted output signal. The duty cycle correcting circuit includes a duty cycle adjust circuit that uses two series-connected N-channel transistors to control the pull-up slew rate of a signal and another N-channel transistor to control the pull-down slew rate of the same signal, two dual-slope integrator circuits, and input and output signal buffering.

Abstract: A system and method for generating a correction signal for correcting duty cycle error of a first clock signal relative to a second complementary clock signal. Changes to a time difference between high- and low-portions of the first clock signal are detected and the correction signal is generated in response to and accordance with the detected changes.

Abstract: A semiconductor integrated circuit has an active mode and a sleep mode. The semiconductor integrated circuit is constructed by alternately connecting a plurality of combinational logic circuits and a plurality of flip-flops. The flip-flops include a retention flip-flop that is supplied with electric power and retains the data in the sleep mode, and a non-retention flip-flop that is not supplied with electric power during the sleep mode. The non-retention flip-flop includes an initializing circuit that initializes the non-retention flip-flop when the semiconductor integrated circuit is switched from the sleep mode to the active mode.

Abstract: A flip-flop includes a functional latch and a retention latch. The functional latch is configured to maintain a logic state of the flip-flop in a power-up mode and the retention latch is configured to maintain the logic state of the flip-flop in a power-down mode. The retention latch is selectively coupled to the functional latch and the retention latch is configured to maintain the logic state in the power-down mode irrespective of a level of an associated clock signal when the power-down mode is entered. A clock pulse that clocks the flip-flop is derived from the associated clock signal.

Abstract: A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.

Abstract: The invention relates to an integrated circuit (1) which comprises a novel bidirectional mixed signal single-wire interface (6) via which the circuit receives command information from a host and transmits conditioned analog signals to the host. In order to implement the mixed signal interface, the integrated circuit is provided with means for analog signal conditioning (2), command detection (3), and digital control (4). In a preferred embodiment of the invention, current detectors are used for command detection and respond to the current flowing through the interface connection (6) so that commands can be given even when analog signals are present on the bus. The invention relates to several methods of operation, especially methods for operating a plurality of the integrated circuits on the same mixed signal bus, and methods for the compatible operation with conventional integrated circuits.