Abstract: The invention relates to a digital acquisition device for an amplitude modulation signal of a carrier. The acquisition device digitally acquires a useful signal. The useful signal modulates the amplitude of a carrier HF1 which has a frequency and a phase that are known. A modulation of the amplitude of the carrier by the useful signals forms a signal to be processed. According to the invention, the device has a summing device for creating an aggregate signal from a sum of the signal to be processed and a neutralizing signal. The neutralizing signal is a product of the carrier HF1 and of a neutralizing coefficient that can evolve over time, produced by a controlled-gain amplifier device. A load amplifier device amplifies the aggregate signal and produces an amplified aggregate signal. A quadrant comparison device QC is provided for the signal of the amplified aggregate signal and the sign of the carrier which delivers a comparison signal. A sampling device produces a bitstream from the comparison signal.

Abstract: Various aspects are described, such as a method for operating a level shifter, in which the level shifter is coupled to a first supply voltage and a second supply voltage different from the first supply voltage. The method may include detecting whether the first supply voltage is present, and decoupling an input of the level shifter from an output of the level shifter responsive to detecting that the first supply voltage is not present.

Abstract: An apparatus for generating an internal voltage in a semiconductor integrated circuit includes a first voltage generating unit configured to detect a feedback voltage level of a first internal voltage and perform a pumping operation, thereby generating a first internal voltage, and a second voltage generating unit configured to generate a second internal voltage by detecting a feedback voltage level of the second internal voltage, performing level shifting on the detected feedback voltage level, receiving the first internal voltage, and generating the second internal voltage based on the level shifted feedback voltage signal and the received first internal voltage.

Abstract: A level shifting circuit, satisfying a requirement of a high tolerated dV/dt level, and a highly reliable inverter circuit, wherein a set pulse signal and a reset pulse signal, both of which are level-shifted to a potential side taking as reference a reference potential of a gate control terminal of a switching terminal, are obtained differentially and integrated, and, in case these pulse signals equal or exceed stipulated integrated values, are transmitted as regular control signals controlling the on/off state.

Abstract: An anti-exponential amplifier produces an output signal that is an exponential/anti-logarithmic function of an input signal. The amplifier includes three function generators and a low-pass filter. The first function generator produces a periodic exponential waveform based upon a resistor-capacitor time constant, with the magnitude of the periodic exponential waveform exponentially increasing to a maximum value in each period. A second function generator produces a ramp waveform from the exponential waveform. The ramp waveform has a period and maximum amplitude substantially equal to those of the exponential signal. The third function generator produces a hybrid waveform with a first portion and a second portion, with the duration of the first period determined in response to the ramp waveform. A low pass filter produces the anti-logarithmic output signal as a function of the hybrid waveform. The resulting amplifier could be useful in a brightness or other parameter control for a display.

Abstract: A method of mixing a first digital data having a first sampling rate and a second digital data having a second sampling rate includes converting the second digital data, by using a first coefficient obtained by multiplying a sampling coefficient with a volume coefficient for the second digital data, to produce a converted second digital data which has the same sampling coefficient as the first digital data, converting the first digital data, by using a volume coefficient for the first digital data, to produce a converted first digital data and mixing the converted second digital with the converted first digital data.

Abstract: The description is of a flat substrate with an electrically conductive structure integrated inside the flat substrate or applied to a surface of the flat substrate and/or with a technically improved surface. The invention is characterised in that at least one sensor is integrated inside the flat substrate or applied to a surface of the flat substrate, which generates sensor signals according to deformations occurring inside the flat substrate, at least one actuator is integrated inside the flat substrate or applied to the surface of the flat substrate, which enables the flat substrate to mechanically deform when activated, and a signal unit connected to the at least one sensor and to the at least one actuator is provided, which, on the basis of the sensor signals, generates actuator signals for activating the actuator, so that deformations occurring inside the flat substrate are reduced.

Abstract: In a method of reducing or undoing progressive threshold shift in a thin-film-transistor (TFT) circuit, first and second voltages applied to source and gate terminals of a first transistor cause the first transistor to conduct and apply the first voltage to the gate terminal of the second transistor. The first voltage applied to the gate terminal of the second transistor coacts with a reference voltage coupled to the source terminal of the second transistor via an LED element to cause the second transistor to not conduct whereupon the LED element does not receive electrical power. After a first predetermined period of time sufficient to reduce or undo a progressive threshold shift in the second transistor, the application of the first voltage to the gate terminal of the second transistor is terminated.

Abstract: An anti jitter circuit for reducing time jitter in an input pulse train comprises an integrator, a DC removal circuit and a comparator. The anti jitter circuit also has a feedback loop effective to suppress phase deviation of the output pulse train in response to jitter.

Abstract: A spatially-fed high-power amplifier comprises one or more shaped reflectors to reflect an initial wavefront, and an active array amplifier to amplify the reflected wavefront to generate a high-power planar wavefront. The shaped reflectors provide the reflected wavefront with substantially uniform amplitude when incident on the active array amplifier. The initial wavefront may be a substantially spherical wavefront, and the shaped reflectors may compensate for any amplitude taper of the initial wavefront to provide the reflected wavefront with substantially uniform amplitude components for incident on the active array amplifier. In some embodiments, the shaped reflectors may also contour the illumination to fit the shape of the active array amplifier to help minimize spillover.

Abstract: A pulse-width modulation (PWM) amplifier comprises a feedback loop for reshaping the pulses of the PWM input signal to correct timing and amplitude errors in the class D output stage of the amplifier by means of an error correction signal. In such an amplifier the feedback loop gives a substantial amount of base-band noise when the pulse-period of the PWM input signal is not constant, which is especially the case when the PWM signal originates from a noise shaper. The invention reduces this noise by modifying the reshaping gain of the amplifier with a pulse-period proportional signal.

Abstract: Multiple-Input-Single-Output (MISO) amplification and associated VPA control algorithms are provided herein. According to embodiments of the present invention, MISO amplifiers driven by VPA control algorithms outperform conventional outphasing amplifiers, including cascades of separate branch amplifiers using conventional power combiner technologies. MISO amplifiers can be operated at enhanced efficiencies over the entire output power dynamic range by blending the control of the power source, source impedances, bias levels, outphasing, and branch amplitudes. These blending constituents are combined to provide an optimized transfer characteristic function.

Abstract: In a controller-assisted device for determining a characteristic of a compensation element in a level control circuit, the compensation element is serially mounted inside the level control circuit for a high-frequency signal (S<SB>HF</SB>) in a signal channel with respect to said signal channel. The characteristic of the compensation element has a characteristic which the inverse of the non-linear transmission characteristic of the signal channel in the event of ideal compensation. In the controller-assisted method for the determination of a characteristic of the compensation element in a level control circuit, each ordinate value of the characteristic of the compensation element arises, in the event of a bridged compensation element, from the corrective signal value (Pastel) which is adjusted at a signal level of the level reference signal (Pref) in the adjusted level control circuit, corresponding to the associated abscissa value of the characteristic of the compensation element.

Abstract: Circuit architecture is disclosed that includes one or more half bridges, the one or more half bridges including signal processing circuitry including first and second inputs and one or more outputs. The circuit architecture also includes a driver stage coupled to the one or more outputs of the signal processing circuitry and configured to create at least one output, one of the at least one outputs suitable to couple to a load. The circuit architecture further includes a first feedback loop coupling the at least one output of the driver stage to a first input of the signal processing stage, and includes a second feedback loop coupling the at least one output of the driver stage to a second input of the signal processing stage, where signals on the first and second feedback loops have inverted polarity. Methods and computer-readable media are also disclosed.

Abstract: An improved VGA design offering a purely ratiometric mechanism for controlling gain by current-steering. A control loop delivers a reference voltage to a control amplifier that steers current and match the common mode output voltage (CMOV) with said predefined reference voltage. The VGA is designed so that, although the absolute gain varies over process, voltage, and temperature (PVT), the gain steps retain their values. Moreover, a method for controlling the gain in a VGA in a way that is insensitive to PVT is also disclosed. First, a voltage representing the required gain of the VGA in injected to the outputs of the VGA. Then, the CMOV of the VGA is sampled. Finally, the CMOV is subtracted by a predefined reference voltage and is fed back as bias to bases of the transistors of the VGA, thus controlling it gain, until the CMOV and the reference voltage become equal.

Abstract: Integrated circuit devices include a pair of field effect transistors having shared source terminals, shared drain terminals and shared gate terminals, which may be treated herein as being electrically coupled in parallel. A switch circuit is also provided, which is configured to drive a body terminal of a first one of the pair of field effect transistors with an alternating sequence of first and second unequal body voltages. This alternating sequence is synchronized with a first clock signal. The switch circuit is also configured to drive a body terminal of a second one of the pair of field effect transistors with an alternating sequence of third and fourth unequal body voltages, which is synchronized with a second clock signal. The first and third body voltages may have equivalent magnitudes and the second and fourth body voltages may have equivalent magnitudes. The first and second clock signals may have 50% duty cycles and may be 180 degrees out-of-phase relative to each other.

Abstract: A differential amplifier includes an output stage, a first common mode feedback circuit; and a current source. The output stage includes first and second complimentary output terminals. The first common mode feedback circuit is operable to determine an average voltage across the first and second complimentary output terminals. The current source is coupled to the output stage, and the common mode feedback circuit is operable to control the current source based on the average voltage. A method includes determining an average voltage across a positive output terminal and a negative output terminal of a differential amplifier output stage and controlling current injected into the output stage based on the average voltage.

Abstract: A power amplifier system including a power terminal, a ground terminal, an output terminal, a ripple terminal, a control terminal to which a control signal is supplied from outside, a power amplifier circuit connected between the power terminal and the ground terminal, a negative potential detection circuit connected to the output terminal, and a bias circuit which supplies a bias voltage to the power amplifier circuit, and a bias start-up circuit controlling the startup operation of the bias circuit.

Abstract: There is provided a variable gain mixer capable of controlling a gain at a low source voltage in a wide range without additional current consumption. The mixer includes: mixers constructed with variable gain amplifiers having two transistor pairs Qp+/Qp? and Qn+/Qn? to have a predetermined gain by using LO+ and LO? signals; and LO bias circuits connected to have bias voltages different from each other with respect to the LO+ and LO? signals of the mixers and share an input signal. Accordingly, by integrating the variable gain amplifiers into the mixers, a gain change can be obtained at a low source voltage in a wide range without connecting a number of variable gain amplifiers.

Abstract: Methods to implement low cost, high efficiency, low loss power combiner with novel matching circuits are disclosed. A narrow band power combiner enables a high power and high efficiency radio frequency power amplifier to be realized using multiple low voltage CMOS transistors or micro power amplifiers. The power combiner may be printed on a package substrate and realized either using single layer substrate through edge coupling or multiple layers substrate through broadside coupling. The micro power amplifiers may be fabricated using low voltage CMOS technology and electrical connections between the outputs from the micro power amplifiers and the power combiner may be provided through stud bumps in a flip chip technology. With the tunable matching circuits, the present invention allows the narrow band power combiner to be tuned to different frequencies.

Abstract: A new Class L amplifier which dynamically switches between multiple pairs of power rails, and has the ability to select the most advantageous combination of rails for the minimization of power dissipation in the amplifier. In one embodiment, a bridged amplifier system includes two Class L amplifiers to drive a load.

Abstract: Saturation handling for preventing a power amplifier from going into a saturation condition is disclosed.

Abstract: An ultra wideband low noise amplifier (UWB LNA) and amplification method thereof, providing a substantially achieved bandwidth extension by pole-zero cancellation and utilized to transform input impedance matching up to 50 ohm for gaining low noise figure. The ultra-wideband low noise amplifier is composed of a capacitive-feedback amplifier, a resistive-feedback amplifier, an inductive-feedback amplifier, and a buffer amplifier.

Abstract: According to one embodiment, a phase-locked loop circuit comprises a phase difference detection unit which detects a phase error between a reproduced binary data and extracted clock and generates phase error pulse signals each having an amplitude corresponding to the phase error, a phase sifter sensitivity adjusting unit which generates a first adjustment pulse signal produced by adjusting the phase error pulse signal, and a loop filter unit which generates a pulse train signal for feedback control to generate the extracted clock from the first adjustment signal, wherein the phase shifter sensitivity adjusting unit comprises a first pulse doubler unit which generates an expanded pulse signal which doubles a time width of the phase error pulse signal, and a first amplifying unit which amplifies the amplitude of the expanded pulse signal and generates the first adjustment pulse signal.

Abstract: A new all digital PLL (ADPLL) circuit and architecture and the corresponding method of implementation are provided. The ADPLL processes an integer and a fractional part of the phase signal separately, and achieves power reduction by disabling circuitry along the integer processing path of the circuit when the ADPLL loop is in a locked state. The integer processing path is automatically enabled when the loop is not in lock. Additional power savings is achieved by running the ADPLL on the lower-frequency master system clock, which also has the effect of reducing spur levels on the signals.

Abstract: An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A programmable filter is connected to receive the phase error samples and connected to provide a filtered output having a gain and a phase margin to the controllable oscillator. The programmable filter includes a proportional loop gain control having a programmable loop gain coefficient (alpha-?) and an integral loop gain control having a programmable loop gain coefficient (rho-?).

Abstract: A system, apparatus and method for providing phase lock conditions detection such as a quality of phase lock and loss of lock detection. A phase locked loop (PLL) circuit may comprise an oscillator for providing an output frequency, as well as a detector for detecting the output frequency of the oscillator, comparing the output frequency with a reference signal and outputting a first and second signals as a function of the comparison. The PLL circuit may further include an amplifying circuit for receiving the first and second signals, monitoring a deviation of the first and second signals from a predetermined threshold, and generating a third signal as a function of the deviation. The PLL circuit may further comprise a comparison circuit for receiving the third signal, comparing the third signal to a window threshold, and generating a fourth signal as a function of the comparison.

Abstract: An apparatus for providing oscillator frequency stability is disclosed. The apparatus includes an internally ovenized oscillator module having an oscillator and an inner heater to maintain the oscillator at a first temperature during operation. The apparatus also includes a thermally conductive cover for forming a first compartment to contain the internally ovenized oscillator module along with multiple heaters. The heaters are in thermal communication with the thermally conductive cover and the substrate to form an oven to keep the internally ovenized oscillator module at a stable second temperature during operation. In addition, the apparatus includes a thermally insulative cover for forming a second compartment to contain the first compartment.

Abstract: A clock synthesis circuit includes a delta sigma modulator that receives a divide ratio and generates an integer portion and a digital quantization error (a fractional portion). A fractional-N divider divides a received signal according to a divide control value corresponding to the integer portion and generates a divided signal. A phase interpolator adjusts a phase of the divided signal according to the digital quantization error to thereby reduce noise associated with the fractional-N divider.

Abstract: A tunable active inductor and a voltage controlled oscillator (VCO) are provided. The tunable active inductor includes a first current source coupled to a power source, a first metal-oxide semiconductor (MOS) transistor including a drain coupled to the first current source and a gate coupled to a first bias voltage, a second MOS transistor including a drain coupled to the power source and a gate coupled to the drain of the first MOS transistor, the gate of the second MOS and the drain of the first MOS being coupled to a second bias voltage, a resonator coupled to a source of the second MOS transistor, and a second current source coupled to the resonator. The VCO employs the tunable active inductor to freely vary the oscillation range of the VCO in a high frequency band.

Abstract: A third overtone crystal oscillator has an oscillator IC and a crystal element accommodated in a container. The IC includes transistor grounded at its emitter, a first capacitor connected to the base of the transistor via a DC blocking capacitor and to the ground potential, and a second capacitor connected between the collector of the transistor and the ground potential. Both ends of the crystal element are connected to non-grounded ends of the first and second capacitors, respectively. A spiral inductor forming a parallel resonant circuit together with the first capacitor, is provided at the container, using a printing process, for example, being independent of the IC. The parallel resonant frequency of the parallel resonant circuit is set higher than the oscillation frequency at the fundamental wave of the crystal element, and lower than the oscillation frequency at the third overtone of the crystal element.

Abstract: An oscillation circuit induces a first inverter, a second inverter, a first inductive load, a second inductive load and a capacitive load. A first inverter and a second inverter receive a first signal and a second signal, and invert the first and the second signal to output a first inverted signal and a second inverted signal respectively. An output end of the first inverter is electrically connected to a first inductive load, and an output end of the second inverter is electrically connected to a second inductive load. Further, a capacitive load is electrically connected to the output end of the first inverter and the output end of the second inverter, so as to receive the first and the second inverted signal respectively. The capacitance of the capacitive load changes with a control signal.

Abstract: Pulse-width modulation (PWM) finds wide use in many applications including motor control, communication systems, music synthesizers, power supplies, class-D and digital amplifiers, among others. The Fourier series expansion of each period of a pulse waveform includes an additive term that is a function of the pulse width in that period. As the pulse width is varied, this additive term varies, which can be problematic in many applications. In an embodiment, a single-pulse per period pulse width modulated waveform comprising a zero d.c. term in each period regardless of pulse width is generated. In various realizations these waveforms may be generated by electronic circuitry without the use of capacitive coupling or may be generated by algorithms. Further aspects include “through-zero” pulse width modulation and zero-centered asymmetric triangle waveforms and use in instrumentation for measurement of a phase angle of an exogenous system or phenomena.

Abstract: A high-frequency composite component for selectively switching a GSM-system signal path and a DCS-system signal path for a signal transmitted to or received from an antenna terminal by a diplexer. Transmission-side input terminals and reception-side balanced output terminals to be switched by high-frequency switches are included in the GSM and the DCS systems. Matching elements include inductors and capacitors that are inserted between the reception-side balanced output terminals and the output side of surface acoustic wave filters.

Abstract: A waveguide correlation unit and a method for manufacturing the same are disclosed. The waveguide correlation unit includes stacked first and second waveguide plates having an identical configuration, wherein a central coupling plate is disposed therebetween. Due to the identical configuration of the first and second waveguide plates, mechanical uncertainties may significantly be reduced, since both plates may be formed in a common process without the repositioning activities during the manufacturing process.

Abstract: It is disclosed that a lamppost (2) can comprise a low pass filter (17) for preventing the creation of undesirable electromagnetic fields. The low pass filter passes a first signal (11) and prevents a second signal (12) to enter further into the lamppost (2). The first signal (11) can be a power signal that is transported via a powerline (10) to lampposts (1, 2). The second signal (12) can be a telecommunication signal that is transported via the powerline (10) to or form telecommunication equipment (7) that is present in one or more lampposts (1). The low pass filter (17) can be comprised by a second fuse (8?). There also can be a switch (18) comprised by the second fuse (8?) via which switch it is possible to activate and deactivate the low pass filter (17).

Abstract: A device and method for attenuating high frequency signals on a power line carrying power is provided. In one embodiment the device may include a toroid shaped core formed of magnetically permeable material and having an inner surface to be disposed substantially around the entire circumference of the power line and a winding formed of a conductor that encircles the toroid. The conductor may include a first spiral coil comprised of a plurality of insulated loops such as concentric loops. The first coil is configured to act as an impedance to high frequency signals traversing the conductor and to allow signals below one hundred hertz to traverse the conductor substantially unimpeded to thereby prevent saturation of the core by the power carried by the power line.

Abstract: A transducer includes an acoustic track in which an acoustic wave can be propagated, the acoustic track having a transversal fundamental mode, the acoustic track being subdivided in a transversal direction into an excitation area and two peripheral areas. The transducer also includes a first outside area and a second outside area bordering the acoustic track such that the acoustic track is arranged in the transversal direction between the first and second outside area. The transducer also includes peripheral areas configured such that the longitudinal phase velocity vRB of the acoustic wave in the respective peripheral area is greater than the longitudinal phase velocity vMB of the wave in the excitation area.

Abstract: A surface acoustic wave filter includes a piezoelectric substrate including lithium niobate, a series resonator including a first interdigital transducer electrode provided on the piezoelectric substrate, and a parallel resonator including a second interdigital transducer electrode provided on the piezoelectric substrate and being electrically connected to the series resonator. An apodized weighting factor of the first interdigital transducer electrode is smaller than an apodized weighting factor of the second interdigital transducer electrode. This surface acoustic wave filter has a small loss.

Abstract: The present invention relates to a mechanical compensating device for a waveguide (1). More precisely, the present invention provides a technology for ensuring phase stability in a waveguide (1) subject to expansions and contractions owing to temperature changes. To do this, actuators, which may consist of pairs of prongs (8-9, 10-11), connected to longitudinal ribs (2, 3) cut in the body of the waveguide (1) and integral therewith, cause, because of a large difference between the respective coefficients of thermal expansion of the waveguide (1) and of the actuators, a rotation of the longitudinal ribs (2, 3) about themselves, deforming the short sides (4, 5) of the waveguide (1) when said waveguide (1) expands or contracts according to the changes in temperature.

Abstract: Provided is a signal transmission circuit capable of realizing the same effects as those in a conventional manner that employs a complicated circuit by using no complicated circuit, that is, by a simple circuit. The signal transmission circuit includes: a transmission path having a first impedance; a terminating resistor having a predetermined resistance; a transmission path having a second impedance, which is connected to the transmission path and the terminating resistor, the second impedance being higher than both of the first impedance and the predetermined resistance; and an input buffer for receiving a signal at a connection portion of the transmission path and the transmission path.

Abstract: Embodiments of the present invention provide a trapped acoustic wave system and a method of assembling such a system. The system may include a substrate having an acoustic wave cavity and a transducer mounted on the substrate. The transducer is configured to resonate the acoustic wave cavity. An acoustically transmissive adhesive secures a first portion of the transducer to the substrate. An additional adhesive, which is separate and distinct from the acoustically transmissive adhesive, anchors at least a second portion of the transducer to the substrate.

Abstract: A transmission structure having high propagation velocity and a low effective dielectric loss. The structure comprises a dielectric, a first reference conductor disposed below the dielectric, a signal conductor disposed above the dielectric, and a second reference conductor disposed over the signal conductor. The second reference conductor has a recess portion facing the signal conductor, the recess portion defining a gap between the second reference conductor and the signal conductor. The gap may be filled with air which has a relative dielectric constant approximately equal to one (1). Because of the physical and dielectric constant characteristics of the gap, the structure concentrates an electric field in the gap resulting in an effective dielectric constant approximately (approaching) one (1) and an effective dielectric loss approximately equal to zero (0). Thus, the structure exhibits a propagation velocity approximately equal to the speed of light.

Abstract: A method and apparatus for constructing, repairing and operating modular electronic systems utilizes peripheral half-capacitors (i.e., conductive plates on the outside of the modules) to communicate non-conductively between abutting modules. Such systems provide lower cost, improved testability/reparability and greater density than conventional modular packaging techniques, such as printed circuit boards and multi-chip modules. The non-conductive interconnection technique of the invention can be applied to all levels in the packaging hierarchy, from bare semiconductor dies to complete functional sub-units.

Abstract: A waveguide quick disconnect clamp includes a first arm and a second arm, both arms having a first end, a second end, and a jaw pivotally connected to the second end. Each of the first and second arm jaws has a generally flat engaging face defining two generally parallel elongated sections and a waveguide receiving recess therebetween. The second arm second end is pivotally connected to the first arm at a position intermediate the first arm first and second ends, and a threaded nut is pivotally connected to the first arm first end. The waveguide quick disconnect clamp also has an adjustment screw having a first end, a second end, and a threaded portion therebetween. The adjustment screw first end pivotally engages the second arm at a point intermediate the second arm first and second ends, and the threaded portion of the screw engages the threaded nut.

Abstract: The present invention comprises a micro-electromechanical system (MEMS) micro-switch array based current limiting enabled circuit interrupting apparatus. The apparatus comprising an over-current protective component, wherein the over-current protective component comprises a switching circuit, wherein the switching circuit comprises a plurality of micro-electromechanical system switching devices. The apparatus also comprises a circuit breaker or switching component, wherein the circuit breaker or switching component is in operable communication with the over-current protective component.

Abstract: The present invention relates to a high voltage transformer with high magnetic leakage and dual high voltage output, comprising a base and a core set, wherein the base contains a hollow support into which a first core of the core set pierces, and primary coils are wound on both sides of the hollow support, while a plurality of isolation channels is installed for winding first and second secondary coils on external sides of primary coils. First and second slots are opened between the primary coils and the first and second secondary coils respectively, and both slots cut into an internal through hole. When a second core of the core set is placed at one end of the hollow support, extensions at both ends of the second core go through both sides of the first core, together with first and second protrusive parts between the two extensions that are installed within the first and second slots and combined with the first core to form multiple magnetic paths.

Abstract: An embodiment of a coupled-inductor core includes first and second members and first and second forms extending between the first and second members. The first form has a parameter (e.g., length) of a first value, and is operable to conduct a first magnetic flux having a first density that depends on the first value of the parameter. The second form is spaced apart from the first form, has the parameter (e.g., length) of a second value different from the first value, and is operable to conduct a second magnetic flux having a second density that depends on the second value of the parameter. Because two or more of the forms of such a core may have different values for the same parameter, the core may be suitable for use in a multiphase power supply where the currents through the phases are unbalanced.

Abstract: The present invention relates to a safety device for preventing propagation when a ceramic element is failed. An angle is formed such that elastic terminals contacted at both faces of the ceramic element do not face each other and an elastic terminal of one lateral face of the ceramic element is formed without one leg so as not to be contacted with the ceramic element, and therefore when an unsustainable force is applied to the ceramic element by an excessive thermal stress or an excessive current caused by an external abnormal power supply is applied to the ceramic element, the ceramic element performs an immediate failure and thus a rapid cut-off capability of circuit.

Abstract: The invention relates to a thermal tripping device which is heated indirectly by means of a heating winding and which comprises a release strip made of thermostatic bimetal, a form memory alloy or similar. An insulating intermediate layer is arranged between the heating winding and the release strip and one of the ends of the heating winding is connected to a supply conductor. The heating winding is embodied in an identically meandering manner for all current intensities and is folded about the insulating intermediate layer. In order to modify the resistance of the heating winding for other current intensities, the discharge is connected to a wiring point between the ends of the heating windings.