Abstract: A flexible printed circuit board includes a flexible base, a working trace region, and at least one reinforcement trace. The working trace region and the at least one reinforcement trace are formed on the flexible base. The working trace is formed by a number of working traces. In the flexible base, the at least one reinforcement trace is disposed at a periphery of the working trace region.

Abstract: This metal housing (2) is particularly intended to contain electronic or similar components. It includes a side wall (8) furnished with a ledge (20) having a bore (16) to receive a fixing screw (6). The side wall (8) has, at the bore (16), a recessed zone (10) whose concavity is oriented toward the outside of the housing (2), the ledge (20) intended to receive the screw (6) overhanging the recessed zone (10).

Abstract: A digital broadcast tuner includes a circuit board and a plurality of terminals. The circuit board has long sides and short sides. The terminals are arranged along one of the short sides of the circuit board. This reduces the length of the long sides of the circuit board and makes it smaller and more inexpensive, while reducing the length of the connection lines between a digital signal decoder circuit and the terminals, thus realizing high performance.

Abstract: In a circuit board device having an electronic component mounted on an electrode land on a board by reflow soldering, voids that adversely affect the solder joint in various ways are prevented from forming. The electrode land corresponding to a component electrode for the electronic component is divided into a plurality of land regions by solder resist having a prescribed width. The component electrode is laid above the solder resist so as to form a clearance communicating with the outside of the component electrode, so that gas generated by vaporization of a flux component contained in the solder during reflow-heating is passed through the clearances and let out of the component electrode. In this way, voids in the solder part can more readily be prevented from forming without increasing the number of person hours as compared to the conventional method.

Abstract: According to one embodiment, first to fourth pads are arranged on a surface mounting area of a printed circuit board along one side of the mounting area, with a preset gap defined between each pair of adjacent ones of the pads. The first to third pads form a first land, and the second to fourth pads form a second land. When a first three-terminal regulator IC is mounted on the first land, a radiator-side terminal pin incorporated in the regulator IC is connected to a first radiator pad and a common radiator pad. When a second three-terminal regulator IC is mounted on the second land, a radiator-side terminal pin incorporated in the regulator IC is connected to a second radiator pad and the common radiator pad.

Abstract: An enclosure for compact computer boards is described that allows a user to easily configure, or reconfigure, a microserver stack using an interchangeable common bus as a data and power backbone. One application requiring robust and rigorous design constraints is use within an aircraft.

Abstract: Multiple fully buffered DIMM circuits or instantiations are presented in a single module. In a preferred embodiment, memory integrated circuits (preferably CSPs) and accompanying AMBs are arranged in two ranks in two fields on each side of a flexible circuit. The flexible circuit has expansion contacts disposed along one side. The flexible circuit is disposed about a supporting substrate or board to place one complete FB-DIMM circuit or instantiation on each side of the constructed module. In alternative but also preferred embodiments, the ICs on the side of the flexible circuit closest to the substrate are disposed, at least partially, in what are, in a preferred embodiment, windows, pockets, or cutaway areas in the substrate. Other embodiments may only populate one side of the flexible circuit or may only remove enough substrate material to reduce but not eliminate the entire substrate contribution to overall profile.

Abstract: A circuit module is provided in which at least one secondary substrate and preferably two such secondary substrates are populated with integrated circuits (ICs). A rigid core substrate for the circuit module is comprised of a structural member and a connective member. In a preferred embodiment, the structural member is comprised of thermally conductive material while the connective member is comprised of conventional PWB material. The secondary substrate(s) are connected to the connective member with a variety of techniques and materials while, in a preferred embodiment, the connective member exhibits, in a preferred embodiment, traditional module contacts which provide an edge connector capability to allow the module to supplant traditional DIMMs.

Abstract: A circuit board shielding assembly includes an electrically conductive fabric over foam gasket that forms part of a circuit board card guide in a computer system. As a user inserts a circuit board assembly into the card guide of the computer system, a carrier tray of the circuit board assembly contacts the electrically conductive fabric of the gasket. The fabric over foam gasket also deforms to follow the geometric contours of the edges of the carrier tray. As such, the fabric over foam gasket forms a substantially continuous electrical contact with the carrier tray and forms part of a Faraday cage to provide EMI shielding to the circuit board. Additionally, the electrically conductive fabric includes certain material properties that cause the fabric to be substantially resistant to flaking electrically conductive fragments when as a user inserts the circuit board assembly within the card guide and generates a shear force relative to the electrically conductive fabric.

Abstract: Disclosed herein is a constant voltage circuit for a power adapter which is capable of varying an output voltage with loads so as to reduce the charging time of a system battery.

Abstract: A technique performed by a transformer-coupled DC-DC converter is described for recovering energy, due to leakage inductance in the transformer. A main power supply, providing a power supply voltage to a Vin terminal, is intermittently coupled to the primary winding of the transformer by a switching transistor. When the switching transistor is turned off, creating a voltage spike in the primary winding due to leakage inductance, the spike is conducted by a forward biased diode and filtered by a capacitor. The voltage at the capacitor (Vc) is then applied as an input voltage to a small pulse width modulated (PWM) regulator. The output of the PWM regulator is coupled to the Vin terminal along with the main power supply. The PWM regulator regulates the input voltage Vc to be a predetermined amount above the power supply voltage. Since the voltage spike energy is used to create the input voltage for the PWM regulator, and the output of the PWM regulator is fed back into the Vin terminal, the energy is recovered.

Abstract: A modification of a control loop of a primary side sensing power control system that uses a different and unique relationship to accomplish the constant current control while attenuating the affects of a ripple voltage.

Abstract: A high voltage charging circuit is provided with the ability of rapid charging. The circuit is composed of a turn-on control circuit, a turn-off control circuit and a transistor. The turn-on control circuit is adopted to set a turn-on time of a transistor such that the transformer may store magnetic energy, while the turn-off control circuit is used to set a turn-off time of the transistor such that the transformer may release the magnetic energy to charge a high voltage capacitor. Smaller inductance reduces the turn-on time of the power transistor owing to the maximum current of the primary side of the transformer. Therefore, a small-sized transformer may be employed to reduce the volume of the charging circuit with nonoccurrence of saturation.

Abstract: A system for limiting AC inrush current to a power supply. The system comprises first, second, and third windings magnetically coupled to a core of a transformer of the power supply. The system also comprises a first low-voltage contactor and a second low-voltage contactor. The system further comprises a first low-voltage impedance element connected between the first low-voltage contactor and the first winding, a second low-voltage impedance element connected between the second low-voltage contactor and the first winding, a third low-voltage impedance element connected between the first low-voltage contactor and the second winding, and a fourth low-voltage impedance element connected between the second low-voltage contactor and the second winding.

Abstract: Self-powered supplies are presented for powering a power converter switch driver with power obtained from an associated snubber circuit, in which a supply circuit and a snubber circuit are connected in a series path across the switch terminals with the supply circuit receiving electrical power from the snubber and providing power to the switch driver.

Abstract: A switching power supply apparatus generates a first output voltage with a reversed polarity of an input voltage and a second input voltage of double the input voltage with the reversed polarity, and then outputs them from the first output terminal and the second output terminal. A driver circuit includes a control unit and a first switch to a sixth switch. The driver circuit repeats three charging periods in a time-division manner. The three charging periods are a first charging period during which a flying capacitor is charged with the input voltage, a second charging period in which a low-potential-side terminal of the flying capacitor is connected to a ground terminal and a first output capacitor is charged with a voltage appearing at the other end of the flying capacitor, and a third charging period in which a high-potential-side of the flying capacitor is connected with the first output terminal and a second output capacitor is charged with a voltage appearing at the other end of the flying capacitor.

Abstract: System and method for providing switching to power regulators. According to an embodiment, the present invention provides system for providing switching. The system includes a first voltage supply that is configured to provide a first voltage. The system also includes a second voltage supply that is configured to provide a second voltage. The second voltage being independent from the first voltage. The system additionally includes a controller component that is electrically coupled to the first voltage supply. For example, the controller component being configured to receive at least a first input signal and to provide at least a first output signal. Additionally, the system includes a gate driver component that is electrically coupled to the second voltage supply. The gate driver component is configured to receive at least the first output signal and generated a second output signal in response to at least the second voltage and the first output signal.

Abstract: Systems for converting single phase power to three phase power are well known, however, these systems may be noisy and wasteful of electrical power because they are prone to being left on for long periods of time when three phase power is not required. To overcome these disadvantages, these converters would be manually started and stopped as necessary. This invention solves these problems by providing a system that automatically controls a three phase converter based on electrical characteristics of the connected three phase load. The invention may detect when a three phase load requires power to operate and enables a three phase converter to provide the required power. Upon completion of the requirement of power, the system of the invention may shut down the converter. Additionally, the system of the invention may signal other electrical devices based on various electrical conditions of the connected three phase load.

Abstract: A low power matchline sensing scheme where power is distributed according to the number of mismatching bits occurring on a matchline is disclosed. In particular, match decisions involving a larger number of mismatched bits consume less power compared to match decisions having a lesser number of mismatched bits. The low power matchline sensing scheme is based upon a precharge-to-miss sensing architecture, and includes a current control circuit coupled to each matchline of the content addressable memory array for monitoring the voltage level of the matchline during a search operation. The current control circuit provides a voltage control signal to the current source of the matchline to adjust the amount of current applied to the matchline in response to the voltage of the matchline. In otherwords, matchlines that are slow to reach the match threshold voltage due to the presence of one or more mismatching bits will receive less current than matchlines having no mismatching bits.

Abstract: A non-volatile memory device according to one embodiment comprises a plurality of memory cells each comprising a magneto resistive element and a selection transistor; wherein at least some of the memory cells are arranged into a two dimensional array; a first interconnect line extending in a first direction of the memory array and functioning as a gate electrode of a selection transistor included in each memory cell; a second interconnect line extending in the first direction of the memory array; a third interconnect line extending in a second direction; wherein the magneto resistive element of at least some of the memory cells is sandwiched between the second and third interconnect lines, wherein the second interconnect line extends at least partially along all magneto resistive elements in a particular one of the memory cells.

Abstract: A high speed sensing scheme for a non-volatile memory array is disclosed. The memory array includes non volatile memory cells arranged in a complementary bitline configuration includes precharge circuits for precharging the bitlines to a first voltage level such as VSS, a reference circuits for applying a reference charge on the reference bitlines of the complementary bitline pairs, and bitline sense amplifiers for sensing a voltage differential between the complementary bitline pairs. A voltage on the data bitline being changed when a programmed non-volatile memory cell connected to an activated wordline couples the wordline voltage to the data bitline.

Abstract: The present invention relates to a memory device with a hierarchy bit line. In a FeRAM with folded bit lines and opened bit lines, it has a hierarchy bit line where bit line signals in two or more columns commonly share one global bit line signal. In the hierarchy bit line, cell array blocks with the folded bit lines transferred with cell data of FeRAM cells are arranged between a pair of global bit lines in two or more columns, each of sense amps is arranged on the upper and lower edges of each of the cell array blocks, each of the sense amps is shared in the folded bit lines of the top cell array block and the folded bit lines of the bottom cell array block while being alternatively arranged in the neighboring columns, and the sense amps share the pair of global bit lines.

Abstract: A PCRAM cell has a high resistivity bottom electrode cap to provide partial heating near the interface between the cell and the bottom electrode, preventing separation of the amorphous GST region from the bottom electrode, and reducing the programming current requirements.

Abstract: A semiconductor memory device comprises a array of memory cells arranged in a matrix, each memory cell connected to one end of a variable resistor element where the electric resistance is shifted from the first state to the second state by applying the first writing voltage and from the second state to the first state by applying the second writing voltage, and the source or drain of the selecting transistor. The second writing time for the second writing action of shifting the electric resistance of the variable resistor element from the second state to the first state is longer than the first writing time of shifting the same reversely. The second number of the memory cells subjected to the second writing action at once is greater than the first memory cell number subjected to the first writing action at once, and at least the second number is two or more.

Abstract: The possibility of the loss of information stored in a memory cell which is caused by repeating the reading action on the same memory cell comprising a variable resistance element and a select transistor can significantly be reduced. A voltage applying circuit for selecting one or more of the memory cells from a memory cell array and applying voltages to the word lines, bit lines, and source lines for programming, erasing, and reading information applies a voltage between the bit line and the source line connected to the selected memory cell so that the voltage applied between the two ports of the variable resistance element in the selected memory cell during the reading action is equal in the polarity to one of the voltages applied between the two ports of the variable resistance element for the programming action and the erasing action respectively whichever is greater in the absolute value.

Abstract: The present invention relates to a memory device with a hierarchy bit line. In a DRAM with folded bit lines and opened bit lines, it has a hierarchy bit line where bit line signals in two or more columns commonly share one global bit line signal. In the hierarchy bit line, cell array blocks with the folded bit lines transferred with cell data of DRAM cells are arranged between a pair of global bit lines in two or more columns, each of sense amps is arranged on the upper and lower edges of each of the cell array blocks, each of the sense amps is shared in the folded bit lines of the top cell array block and the folded bit lines of the bottom cell array block while being alternatively arranged in the neighboring columns, and the sense amps share the pair of global bit lines.

Abstract: A static random access memory (SRAM) cell includes a first load device, a first pull-down transistor, and a switch-box coupled between the first load device and the first pull-down transistor. The switch-box is configured to receive a switch control signal to turn off a first connection between the first load device and the first pull-down transistor during read operations of the SRAM cell and to turn on the first connection during write operations.

Abstract: This invention relates to an improved microelectronic RAM memory device, provided with 4T or 6T cells made using the double gate technology and each associated with two word lines.

Abstract: An integrated circuit device is provided which includes a heat source disposed in a substrate, and a Magnetic Tunnel Junction (“MTJ”) temperature sensor disposed over the heat source.

Abstract: A spin-injection magnetic random access memory according to an embodiment of the invention includes a magnetoresistive element having a magnetic fixed layer whose magnetization direction is fixed, a magnetic recording layer whose magnetization direction can be changed by injecting spin-polarized electrons, and a tunnel barrier layer provided between the magnetic fixed layer and the magnetic recording layer, a bit line which passes spin-injection current through the magnetoresistive element, the spin-injection current being used for generation of the spin-polarized electrons, a writing word line through which assist current is passed, the assist current being used for the generation of an assist magnetic field in a magnetization easy-axis direction of the magnetoresistive element, and a driver/sinker which determines a direction of the spin-injection current and a direction of the assist current.

Abstract: There is provided a magnetic memory device including a first magnetoresistive element which takes a high-resistance-state when receiving a write current in a first direction, takes a low-resistance-state having a resistance value lower than that in the high-resistance-state when receiving a write current in a second direction opposite to the first direction, and receives a read current in a read operation, a second magnetoresistive element which takes one of the high-resistance and low-resistance-states in accordance with a magnetization state thereof, is fixed to the low-resistance-state when a direction of the read current is the same as the first direction, and is fixed to the high-resistance-state when the direction of the read current is the same as the second direction, and a control circuit which is connected to the first and second elements, and makes a read voltage applied to the first element equal to that applied to the second element.

Abstract: A phase change memory device comprises a memory cell array and a write driver circuit. The memory cell array comprises a plurality of memory cells, and the write driver circuit comprises a set current driver and a reset current driver. The set current driver is adapted to provide a set current to a selected memory cell among the plurality of memory cells and the reset current driver is adapted to provide a reset current to a selected memory cell among the plurality of memory cells.

Abstract: A carrier storage node such as a floating gate is formed on a moving electrode with a control gate to form a suspended gate non-volatile memory, reducing floating gate to floating gate coupling and leakage current, and increasing data retention.

Abstract: In an improved EASB programming scheme for a flash device (e.g. a NAND flash device), the number of word lines separating a selected word line (to which a program voltage is applied) and an isolation word line (to which an isolation voltage is applied) is adjusted as a function (e.g. inverse function) of distance of the selected word line from the drain side select gate to reduce program disturb due to high vertical and lateral electric fields at or near the isolation transistor when programming word lines closer to the drain side select gate. The selected and isolation word lines are preferably separated by two or more word lines to which intermediate voltage(s) are applied.

Abstract: A method for minimizing program disturb in Flash memories. To reduce program disturb in a NAND Flash memory cell string where no programming from the erased state is desired, a local boosted channel inhibit scheme is used. In the local boosted channel inhibit scheme, the selected memory cell in a NAND string where no programming is desired, is decoupled from the other cells in the NAND string. This allows the channel of the decoupled cell to be locally boosted to a voltage level sufficient for inhibiting F-N tunneling when the corresponding wordline is raised to a programming voltage. Due to the high boosting efficiency, the pass voltage applied to the gates of the remaining memory cells in the NAND string can be reduced relative to prior art schemes, thereby minimizing program disturb while allowing for random page programming.

Abstract: A semiconductor memory device includes a memory cell array with memory cells arranged therein, each memory cell being settable to have one of plural physical quantity levels, simultaneously selected two memory cells constituting a pair cell serving as a data storage unit, wherein each memory cell is set to have one in N (where N is an integer equal to three or more) physical quantity levels, and each pair cell is set to have different physical quantity levels in two memory cells therein, thereby storing M-value data defined by M=2n (where M>N and “n” is an integer equal to two or more), the M-value data being defined by such M combination states that differences of the physical quantity levels in the two memory cells are different from each other.

Abstract: A non-volatile memory device, and method of forming the same, increases or maximizes the performance of an ultramicro-structured device.

Abstract: A nonvolatile semiconductor memory device includes a nonvolatile memory cell including an odd number of MIS transistor pairs, each of which stores one-bit data by creating an irreversible change of transistor characteristics in one of the two paired MIS transistors, latches equal in number to the odd number of MIS transistor pairs to store the odd number of one-bit data recalled from the MIS transistor pairs, the recalling of the one-bit data of a given MIS transistor pair being performed by sensing a difference in the transistor characteristics between the two paired MIS transistors of the given MIS transistor pair, and a majority decision circuit configured to make a majority decision based on the odd number of one-bit data to determine a bit value of the nonvolatile memory cell.

Abstract: A memory unit is provided herein. The present invention utilizes two non-volatile devices having a split gate structure to save a logic state of the memory unit. Thus, even when a power supply for the memory unit is shut down, the non-volatile devices can still save the logic state. The memory unit not only has the advantage of high speed operation of a static random access memory, but also functions as a non-volatile memory for saving data.

Abstract: A semiconductor memory device includes an array having memory cells arranged in rows and columns; a clock-to-address converter for counting an external clock signal to generate an address for accessing the array based on the counted value, during a test operation mode; and a redundancy circuit for storing the address generated by the clock-to-address converter.

Abstract: A non-volatile memory device includes a memory cell array and a voltage control unit. The memory cell array includes a plurality of memory blocks each including a plurality of cell strings. Each of the cell strings includes a first selection transistor, a second selection transistor, and at least one memory cell transistor serially connected between the first selection transistor and the second selection transistor.

Abstract: A non-volatile memory device includes a memory cell block, a first switching block, and a second switching block. A plurality of memory cells are arranged in the memory cell block and each of the memory cells includes a memory transistor having a floating gate and a control gate and is connected to a local bit line and includes a selection transistor connected to the memory transistor in series that is connected to a source line. The first switching block selectively connects a global bit line to the local bit line and the second switching block controls the memory cells in the memory cell block in units of a predetermined number of bits. The first switching block includes at least two switching devices connected in parallel between the global bit line and the local bit line.

Abstract: A semiconductor memory device includes a memory cell, a word line, a bit line, a column gate, and a power supply decode circuit. The memory cell has a first MOS transistor including a charge accumulation layer and a control gate. The bit line is connected to a drain of the first MOS transistor and is applied with first voltage at the test operation time and at data program operation time. The column gate includes a second MOS transistor having current path connected to the bit line to transfer the first voltage to the bit line at the test operation time. The power supply decode circuit applies a second voltage to a gate of the second MOS transistor at the program operation time and applies a third voltage lower than the second voltage at the test operation time.

Abstract: A string of nonvolatile memory cells are formed with control gates extending between floating gates, control gates and floating gates separated by tunnel dielectric layers. Electron tunneling between control gates and floating gates is used for programming. A process for forming a memory array forms odd numbered floating gates from a first layer and even numbered floating gates from a second layer.

Abstract: There is provided a non-volatile memory which enables high accuracy threshold control in a writing operation. In the present invention, a drain voltage and a drain current of a memory transistor are controlled to carry out a writing operation of a hot electron injection system, which is wherein a charge injection speed does not depend on a threshold voltage. FIGS. 1A and 1B are views of a circuit structure for controlling the writing. In FIGS. 1A and 1B, an output of an operational amplifier 103 is connected to a control gate of a memory transistor 101, a constant current source 102 is connected to a drain electrode, and a source electrode is grounded. The constant current source 102 and a voltage Vpgm are respectively connected to two input terminals of the operational amplifier 103.

Abstract: A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors having drain electrodes and source electrodes respectively coupled to bit lines and source lines and gate electrodes coupled to word lines and storing information based on a difference between threshold voltages to a word line select level in read operation, and the nonvolatile memory has a low power consumption mode. In the low power consumption mode, a second voltage lower than a circuit ground voltage and higher than a first negative voltage necessary for read operation is supplied to the well regions and word lines. When boost forming a rewriting negative voltage therein, a circuit node at a negative voltage is not the circuit ground voltage in the low power consumption mode.

Abstract: A programming circuit and method to apply a controlled or predetermined voltage pulse for charge transfer to or from the floating gate of a non-volatile memory cell in an incremental manner to control the overall voltage across the gate oxide. Voltage above a transfer threshold voltage, such as above a tunneling threshold voltage, is applied in a stepwise charge transfer manner to or from the floating gate up to a voltage limit that is below the thin oxide damage threshold. Controlling the overall voltage avoids oxide breakdown and enhances reliability.

Abstract: A method for programming one or more reference cells is described. The reference cell is programmed a predetermined amount, its program state is sensed relative to a prescribed cell on the same die (e.g., a memory cell or a golden bit cell), and the programming process continues until the reference cell fails a preselected read operation. In one preferred embodiment, the memory cell used during the reference cell programming process is the cell in the memory array having the highest native threshold value. In another preferred embodiment, the memory cell used during the reference cell programming process is a native cell that is on-board the die containing the memory array, but not a cell within the memory array.

Abstract: Provided is a voltage regulator of a flash memory device. Embodiments of the invention provide a voltage regulator that is configured to regulate either an internal pumping voltage or an external high voltage. In embodiments of the invention, the voltage regulator includes two switches having different switching current characteristics: when regulating the internal pumping voltage, the voltage regulator is configured to activate a switch having a relatively high switching current to output the regulated voltage; but when regulating the high external voltage, the voltage regulator is configured to activate a switch having a relatively low switching current to output the regulated voltage during at least a set-up time. In an embodiment of the invention, the voltage regulator may be configured to activate both switches to regulate the high external voltage after the set-up time.

Abstract: A method of reading data in a non-volatile memory device includes providing a plurality of blocks and a plurality of bit lines, each block having a plurality of memory cells, each block coupled to at least one bit line. First and second bit lines are discharged to be at a low level, the first bit line coupled to a first block, the second bit line coupled to a second block. A read voltage is applied to a first word line coupled to a memory cell to be read in the first block. A pass voltage is applied to a second word line coupled to a memory cell not to be read in the first block. The first bit line coupled to the memory cell to be read is precharged to a high level after applying the read voltage to the first word line and the pass voltage to the second word line. A voltage level of the first bit line is evaluated. Data stored in the memory cell to be read is sensed in accordance with the evaluated voltage level of the first bit line.