Abstract: Providing a duplicate test signal of an output signal under test in an integrated circuit including selecting through a multiplexer an output signal under test, the output signal under test selected from a plurality of output signals of the integrated circuit; providing through the multiplexer a duplicate signal of the selected output signal under test; adding a high impedance load on the duplicate signal thereby reducing the amplitude of the duplicate signal; and amplifying the reduced duplicate signal thereby creating the duplicate test signal.

Abstract: To improve field effect mobility of an inverted-staggered TFT using amorphous silicon. In an inverted-staggered TFT, a thin amorphous semiconductor layer which is made to have n-type conductivity is formed between a gate insulating film and an amorphous semiconductor layer. By depositing an amorphous semiconductor layer after a substrate over which up to a gate insulating film is formed is exposed to an atmosphere which contains a phosphine gas in a small amount, an amorphous semiconductor layer which contains phosphorus is formed during the early stage of deposition of the amorphous semiconductor layer. The thus obtained amorphous semiconductor layer has the concentration peak of phosphorus around the surface of the gate insulating film.

Abstract: Pixel auxiliary capacitors (10) and pixel TFTs, which are thin-film elements, are formed on a substrate a lower electrode (Si) (3), insulating film, and an upper electrode (GE) (5) in this order. Each upper electrode (GE) (5) opposing to the corresponding lower electrode (Si) (3) is entirely enclosed within the outline of the lower electrode (Si) (3) in a plane view. Thus, it is possible to provide thin-film elements, which are not affected by edges of the lower electrode (Si) (3), a display device and a memory cell using the thin-film elements, and their fabrication methods.

Abstract: A thin film transistor array panel for a flat panel display includes a substrate, a first signal line formed on the substrate, a second signal line intersecting and insulated from the first signal line, a switching element having a first terminal connected to the first signal line, a second terminal connected to the second signal line, and a third terminal, a pixel electrode connected to the third terminal of the switching element, and first and second light blocking members extending parallel to the second signal line, each being disposed on an opposite side of and partially overlapping an respective edge of the second signal line, an interval between the first and second light blocking members being in a range of from more than 1.5 ?m to less than 4 ?m. The array panel prevents light leakage from the display and improves its transmittance, aperture ratio and color reproducibility.

Abstract: A substrate having a gate electrode layer, a gate insulating layer, and a silicon layer thereon is provided. These layers are patterned into a gate area, a gate line and a gate line wiring area. A passivation layer is formed on the entire substrate and patterned to form two contact holes in the passivation layer on the silicon layer at the gate area, and partions of the passivation layer at the gate line and at the gate line wiring areas are removed. An ion implanting layer and a metal layer are formed on the substrate and patterned to form a source region, a drain region, a data line, a data line wiring area and a second layer of the gate line wiring area. A pixel electrode is formed on the passivation layer and electrically coupled to the drain region. Therefore, the TFT array can be fabricated by only four masks.

Abstract: A method and a dual-gate memory device having a memory transistor and an access transistor are provided to allow multiple bits to be stored in the dual-gate memory device. The memory transistor and the access transistor each have a channel region formed in a mobility enhanced material crystallized from an amorphous semiconductor material. The amorphous semiconductor material may include, for example, silicon. Mobility enhancement may be achieved by: (a) Excimer laser annealing; (b) lateral crystallization; (c) metal-induced lateral crystallization; (d) a combination of laser annealing and metal-induced laterally crystallization steps; or (e) solid-phase, epitaxially growth.

Abstract: A transparent semiconductor thin film 40 having low carrier concentration and a large energy band gap is produced by forming a thin film which contains indium oxide and an oxide of a positive divalent element, and then oxidizing or crystallizing the thin film.

Abstract: A thin film transistor with excellent electric characteristics, a display device having the thin film transistor, and methods for manufacturing the thin film transistor and the display device are proposed. The thin film transistor includes a gate insulating film formed over a gate electrode, a microcrystalline semiconductor film formed over the gate insulating film, a pair of buffer layers formed over the microcrystalline semiconductor film, a pair of semiconductor films to which an impurity element imparting one conductivity type is added and which are formed over the pair of buffer layers, and wirings formed over the pair of semiconductor films to which the impurity element imparting one conductivity type is added. A part of the gate insulating film or the entire gate insulating film, and/or a part of the microcrystalline semiconductor or the entire microcrystalline semiconductor includes the impurity element which serves as a donor.

Abstract: A thin film transistor with excellent electric characteristics, a display device having the thin film transistor, and a method for manufacturing the thin film transistor and the display device are proposed. The thin film transistor includes a gate insulating film formed over a gate electrode, a microcrystalline semiconductor film formed over the gate insulating film, a buffer layer formed over the microcrystalline semiconductor film, a pair of semiconductor films to which an impurity element imparting one conductivity type is added and which are formed over the buffer layer, and wirings formed over the pair of semiconductor films to which the impurity element imparting one conductivity type is added. A part of the gate insulating film or the entire gate insulating film, and/or a part of the microcrystalline semiconductor or the entire microcrystalline semiconductor includes an impurity element which serves as a donor.

Abstract: A GaN single-crystal substrate has a substrate surface in which polarity inversion zones are included. The number density of the polarity inversion zones in the substrate surface is not more than 20 cm?2. A GaN single crystal production method includes introducing group III and V raw material gases on a substrate, and growing a GaN single crystal on the substrate. The growth temperature is within the range of not less than 1100° C. and not more than 1400° C., the group V to III raw material gas partial pressure ratio (V/III ratio) is within the range of not less than 0.4 and not more than 1, and the number density of polarity inversion zones in a surface of the substrate is not more than 20 cm?2.

Abstract: A heterojunction between thin films of NCD and 4H—SiC was developed. Undoped and B-doped NCDs were deposited on both n? and p? SiC epilayers. I-V measurements on p+ NCD/n? SiC indicated Schottky rectifying behavior with a turn-on voltage of around 0.2 V. The current increased over eight orders of magnitude with an ideality factor of 1.17 at 30° C. Ideal energy-band diagrams suggested a possible conduction mechanism for electron transport from the SiC conduction band to either the valence band or acceptor level of the NCD film.

Abstract: A semiconductor device includes a silicon carbide substrate having a channel region formed on a surface thereof; a silicon layer formed on the channel region; a gate insulation film formed on the silicon layer; and a gate electrode formed on the gate insulation film. A method of producing a semiconductor device includes the steps of: forming a silicon layer on a surface of a silicon carbide substrate; forming a gate insulation film on the silicon layer to form a laminated structure of the silicon layer and the gate insulation film; and forming a gate electrode on the gate insulation film.

Abstract: A silicon carbide semiconductor device is disclosed. The silicon carbide semiconductor device includes a substrate; a drift layer having a first conductivity type and located on a first surface of the substrate; and a vertical type semiconductor element. The vertical type semiconductor element includes: an impurity layer having a second conductivity type, and located in a surface portion of the drift layer; and a first conductivity type region located in the drift layer, spaced away from the impurity layer, located closer to the substrate than the impurity layer, and having an impurity concentration higher than the drift layer.

Abstract: A nitride semiconductor light emitting diode (LED) comprises an n-type nitride semiconductor layer; an electron emitting layer formed on the n-type nitride semiconductor layer, the electron emitting layer being composed of a nitride semiconductor layer including a transition element of group III; an active layer formed on the electron emitting layer; and a p-type nitride semiconductor layer formed on the active layer.

Abstract: Provided are a method of manufacturing a gallium nitride-based compound semiconductor light-emitting device with a low driving voltage (Vf) and high light outcoupling efficiency, a gallium nitride-based compound semiconductor light-emitting device, and a lamp. In the method of manufacturing the gallium nitride-based compound semiconductor light-emitting device, a transparent conductive oxide film 15 including a dopant is laminated on a p-type semiconductor layer 14 of a gallium nitride-based compound semiconductor device 1. The transparent conductive oxide film 15 is subjected to a laser annealing process using a laser after the lamination of the transparent conductive oxide film 15.

Abstract: A semiconductor light-emitting device and method for manufacturing the semiconductor light-emitting device includes a mask layer etching process on first and second mask layers provided on a Group-III nitride-based compound semiconductor substrate, the mask layer with a higher etching rate being closer to the p-type semiconductor layer; a semiconductor layer etching process; a side-etching process that selectively etches the side of the mask layer with the high etching rate to define a groove portion with a portion of the p-type semiconductor layer exposed; a ZrO2 film forming process that forms a ZrO2 film so as to cover the exposed p-type semiconductor layer; an Al2O3 film forming process that forms an Al2O3 film so as to cover the ZrO2 film; a mask layer removing process; and an electrode layer forming process.

Abstract: Methods and apparatuses for forming optical packages, and intermediate structures resulting from the same are disclosed, which provide an optical element over a device. The optical element is formed by applying a force to lateral portions of a liquid material layer formed below an elastomeric material layer such that the liquid material layer has a radius of curvature sufficient to direct light to a light sensitive portion of the device, after which the liquid material layer is exposed to conditions which maintain the radius of curvature after the lateral force is removed.

Abstract: There are a silicon laser device having a IV-group semiconductor such as silicon or germanium equivalent to the silicon as a basic constituent element on a substrate made of the silicon, and the like by a method capable of easily forming the silicon laser device by using a general silicon process, and a manufacturing method thereof.

Abstract: A solid state light emitting device includes a laminated substrate structure (120), an LED chip (30), a transparent capsulation material (50) and an electric component (40). The laminated substrate structure includes a first substrate (10) and a second substrate (20) attached to each other by a sintering process. The first substrate has a mounting surface (100) and a receiving through hole (11) defined in the mounting surface thereof. The LED chip is mounted on the mounting surface of the first substrate. The transparent capsulation material envelops the LED chip therein. The electric component is received in the receiving hole and mounted on the second substrate. The electric component is located below the mounting surface of the first substrate.

Abstract: A structure of light emitted diode package including a lead frame, a holder coupled on an end of the lead frame, a LED chip disposed on the holder, a lower sealing portion made by injection molding a first resin material to grab one end of lead frame with the LED chip in order to hold the lead frame and an upper sealing portion made by casting by a second resin material to dispose on the top of the lower sealing portion.

Abstract: Provided are: a light emitting module capable of ensuring a high heat-dissipating property and mountable in any of sets in various shapes; and a method for manufacturing the light emitting module. The light emitting module mainly includes: a metal substrate; an insulating layer covering the upper surface of the metal substrate; a conductive pattern formed on the upper surface of the insulating layer; and a light emitting element fixedly attached to the upper surface of the metal substrate and electrically connected to the conductive pattern. Furthermore, a groove is formed in the metal substrate, and then the metal substrate is bent. Thus, a bent portion is formed in the metal substrate.

Abstract: A light-emitting diode (LED) chip includes a substrate, a first semiconductor layer, an active layer, a second semiconductor layer and a groove. The first semiconductor layer, active layer and second semiconductor layer are formed on the substrate in sequence. The groove is formed in the first semiconductor layer, the active layer and the second semiconductor layer.

Abstract: A manufacturing method of an epitaxial substrate includes the steps of: forming a sacrificial layer, which has a first micro/nano structure, on a substrate; and forming a buffer layer on the sacrificial layer. The sacrificial layer comprises a plurality of micro/nano particles, and the first micro/nano structure is formed after the plurality of micro/nano particles are removed. An epitaxial substrate and a manufacturing method of a light emitting diode (LED) apparatus are also disclosed.

Abstract: The invention discloses a semiconductor light-emitting device and a method of fabricating the same. The semiconductor light-emitting device according to the invention includes a substrate, a buffer layer, a corrosion-resistant film, a multi-layer structure, and an ohmic electrode structure. The buffer layer is grown on an upper surface of the substrate. The corrosion-resistant film is deposited to overlay the buffer layer The multi-layer structure is grown on the corrosion-resistant film and includes a light-emitting region. The buffer layer assists the epitaxial growth of a bottom-most layer of the multi-layer structure. The corrosion-resistant film prevents the buffer layer from being corroded by a gas during the epitaxial growth of the bottom-most layer. The ohmic electrode structure is deposited on the multi-layer structure.

Abstract: A structure and method for improving UV LED efficiency is described. The structure utilizes a tunnel junction to separate a P-doped layer of the LED from a n-doped contact layer. The n-doped contact layer allows the use of a highly reflective, low work function metal, such as aluminum, for the p-side contact. The reflectivity at the contact can be further improved by including a phase matching layer in some areas between the contact metal (The metal above the phase matching layer does not necessarily need to have a low work function because it does need to form an ohmic contact with the n-contact layer) and the n-doped contact layer.

Abstract: A strained Si-SOI substrate, and a method for producing the same are provided, wherein the method includes the steps of growing a SiGe mixed crystal layer 14 on an SOI substrate 10 having an Si layer 13 and a buried oxide film 12; forming protective films 15, 16 on the surface of the SiGe mixed crystal layer 14; implanting light element ions into a vicinity of the interface between the Si layer 13 and the buried oxide film 12; performing a first heat treatment at a temperature in the range of 400 to 1000° C.; performing a second heat treatment at a temperature not lower than 1050° C. under an oxidizing atmosphere; performing a third heat treatment at a temperature not lower than 1050° C. under an inert atmosphere; removing the Si oxide film 18 formed on the surface; and forming a strained Si layer 19.

Abstract: A method for manufacturing a field effect transistor, includes: forming a mask of an insulating film on a semiconductor layer containing Si formed on a semiconductor substrate; forming the semiconductor layer into a mesa structure by performing etching with the use of the mask, the mesa structure extending in a direction parallel to an upper face of the semiconductor substrate; narrowing a distance between two sidewalls of the mesa structure and flattening the sidewalls by performing a heat treatment in a hydrogen atmosphere, the two sidewalls extending in the direction and facing each other; forming a gate insulating film covering the mesa structure having the sidewalls flattened; forming a gate electrode covering the gate insulating film; and forming source and drain regions at portions of the mesa structure, the portions being located on two sides of the gate electrode.

Abstract: A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant then the buffer layer.

Abstract: Provided is an electric field head including a resistance sensor to read information recorded on a recording medium. The resistance sensor includes a first semiconductor layer including a source and a drain, and a second semiconductor layer that is heterogeneously combined with the first semiconductor layer. Also, the electric field head further includes a channel between the source and the drain, in a junction region of the first and second semiconductor layers.

Abstract: Example embodiments provide a unit pixel, an image sensor containing unit pixels, and a method of fabricating unit pixels. The unit pixel may include a semiconductor substrate, photoelectric transducers formed within the semiconductor substrate, multi-layered wiring layers formed on a frontside of the semiconductor substrate, inner lenses formed on a backside of the semiconductor substrate corresponding to the photoelectric transducers, and microlenses formed above the inner lenses.

Abstract: A method for fabricating a semiconductor structure uses a volumetric change ion implanted into a volumetric change portion of a gate electrode that is located over a channel region within a semiconductor substrate to form a volume changed portion of the gate electrode located over the channel region within the semiconductor substrate. The volume changed portion of the gate electrode is typically bidirectionally symmetrically graded in a vertical direction. The volume-changed portion of the gate electrode has a first stress that induces a second stress different than the first stress into the channel region of the semiconductor substrate.

Abstract: A semiconductor structure is provided that includes a spacer directly abutting a topographic edge of at least one patterned material layer. The spacer is a non-removable polymeric block component of a self-assembled block copolymer. A method of forming such a semiconductor structure including the inventive spacer is also provided that utilizes self-assembled block copolymer technology.

Abstract: A semiconductor device is provided, which includes a first insulating layer over a first substrate, a transistor over the first insulating layer, a second insulating layer over the transistor, a first conductive layer connected to a source region or a drain region of the transistor through an opening provided in the second insulating layer, a third insulating layer over the first conductive layer, and a second substrate over the third insulating layer. The transistor comprises a semiconductor layer, a second conductive layer, and a fourth insulating layer provided between the semiconductor layer and the second conductive layer. One or plural layers selected from the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer have a step portion which is provided so as not to overlap with the transistor.

Abstract: Aimed at providing a highly reliable semiconductor device appropriately increased in stress at the channel region so as to improve carrier injection rate, thereby dramatically improved in transistor characteristics, and made adaptable also to recent narrower channel width, and a method of manufacturing the same, and a method of manufacturing the same, a first sidewall composed of a stress film having expandability is formed on the side faces of a gate electrode, a second sidewall composed of a film having smaller stress is formed on the first sidewall, and a semiconductor, which is a SiC layer for example, is formed as being positioned apart from the first sidewall while placing the second sidewall in between.

Abstract: A wiring structure includes a substrate, a copper oxide layer having 16˜39 at % oxygen on the substrate and a copper layer on the copper oxide layer. The copper oxide layer has a thickness of 10-1000 ? and the copper layer has a thickness of 300-8000 ?. The copper layer and the copper oxide layer further have an alloy element less than 10 wt % and the alloy element is selected from the group of Ag, Ni, Mg, Zr, N.

Abstract: A solid-state imaging device of the present invention includes: a semiconductor substrate including a first region of a first conductivity type; a signal accumulation region of a second conductivity type formed within the first region; a gate electrode formed above the first region; a drain region of a second conductivity type formed on the first region; an isolation region having insulation properties, which is formed to surround a region where the signal accumulation region, the gate electrode, and the drain region are formed; a first conductivity type dopant doping region formed in contact with a side face and a bottom face of the isolation region, the first conductivity type dopant doping region having a higher dopant concentration than the first region; and a second conductivity type dopant doping region formed in the first is region, under an end of the gate electrode in a gate width direction.

Abstract: Provided is an image sensor and a method of fabricating the image sensor. The image sensor can comprise: a semiconductor substrate comprising a photodiode; a metal wiring layer disposed on the semiconductor substrate and comprising a metal wiring and an interlayer dielectric; a trench formed in the interlayer dielectric to correspond to the photodiode; and a color filter formed in the trench. Accordingly, the distance between the photodiode and the color filter can be significantly reduced by forming the color filter in the trench.

Abstract: A pixel and imager device, and method of forming the same, where the pixel has a transfer transistor gate associated with a photoconversion device and is isolated in a substrate by shallow trench isolation. The transfer transistor gate does not overlap the shallow trench isolation region.

Abstract: A DRAM cell includes a substrate, a transistor, and a magnetic capacitor. The substrate is composed of semiconductor material with a main surface, the transistor is formed at the main surface, and the magnetic capacitor is formed in a metal layer. The transistor includes a source region and a drain region formed at the main surface of the substrate. The transistor also includes a control gate placed between the source region and the drain region, and separated from the substrate by a thin control dielectric. The magnetic capacitor includes a first electrode layer, a dielectric layer formed on the surface of the first electrode layer, and a second electrode layer formed on the surface of the dielectric layer. The DRAM cell increases the density, simplifies the manufacturing process, and reduces or eliminates the refresh rate. A DRAM cell with the magnetic capacitor formed in multiple layers is also provided.

Abstract: A semiconductor device includes a substrate having a first area and a second area, a first active structure disposed in the first area, a second active structure disposed in the second area, a first transistor disposed in the first area and a second transistor disposed in the second area. The second active structure may have a height substantially the same as a height of the first active structure. The first transistor includes a first gate structure enclosing an upper portion of the first active structure, a first impurity region formed at a lower portion of the first active structure, and a second impurity region formed at the upper portion of the first active structure. The second transistor includes a second gate structure formed on the second active structure and third impurity regions formed at an upper portion of the second active structure.

Abstract: In a semiconductor device comprising a capacitive element, an area of the capacitive element is reduced without impairing performance, and further, without addition of an extra step in a manufacturing process.

Abstract: A semiconductor device includes: an active region insulated by an element-isolation insulating film embedded on a semiconductor substrate; multiple element forming sections that are provided in the active region; a semiconductor element that is formed in each of the element forming sections; and a channel stopper that is provided in the active region to insulate the element forming sections from each other. The channel stopper comprises: a fin that protrudes between grooves provided in the element-isolation insulating film and on both sides of the active region; a dummy-gate insulating film that covers the fin; and a dummy gate electrode that straddles the fin.

Abstract: Methods, devices, modules, and systems providing semiconductor devices in a stacked wafer system are described herein. One embodiment includes a first wafer for NMOS transistors in a CMOS architecture and a second wafer for PMOS transistors in the CMOS architecture, with the first wafer being bonded and electrically coupled to the second wafer to form at least one CMOS device. Another embodiment includes a number of DRAM capacitors formed on a first wafer and support circuitry associated with the DRAM capacitors formed on a second wafer, with the first wafer being bonded and electrically coupled to the second wafer to form a number of DRAM cells. Another embodiment includes a first wafer having a number of vertical transistors coupled to a data line and a second wafer having amplifier circuitry associated with the number of vertical transistors, with the first wafer being bonded and electrically coupled to the second wafer.

Abstract: A semiconductor structure including a capacitor having increased capacitance and improved electrical performance is provided. The semiconductor structure includes a substrate; and a capacitor over the substrate. The capacitor includes a first layer including a first capacitor electrode and a second capacitor electrode, wherein the first capacitor electrode is formed of a metal-containing material and is free from polysilicon. The semiconductor structure further includes a MOS device including a gate dielectric over the substrate; and a metal-containing gate electrode on the gate dielectric, wherein the metal-containing gate electrode is formed of a same material, and has a same thickness, as the first capacitor electrode.

Abstract: A device, such as a nonvolatile memory device, and methods for forming the device in an integrated process tool are provided. The method includes depositing a tunnel oxide layer on a substrate, exposing the tunnel oxide layer to a plasma so that the plasma alters a morphology of a surface and near surface of the tunnel oxide to form a plasma altered near surface. Nanocrystals are then deposited on the altered surface of the tunnel oxide.

Abstract: Embodiments of the present invention disclose a memory device having an array of flash memory cells with source contacts that facilitate straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions that isolate a plurality of memory cell columns. A source column is implanted with n-type dopants after the formation of a tunnel oxide layer and a first polysilicon layer. The implanted source column is coupled to a plurality of common source lines that are coupled to a plurality of source regions associated with memory cells in the array. A source contact is coupled to the implanted source column for providing electrical coupling with the plurality of source regions. The source contact is collinear with a row of drain contacts that are coupled to drain regions associated with a row of memory cells. The arrangement of source contacts collinear with the row of drain contacts allows for straight word line formation.

Abstract: Memory elements, switching elements, and peripheral circuits to constitute a nonvolatile memory are integrally formed on a substrate by using TFTs. Since semiconductor active layers of memory element TFTs are thinner than those of other TFTs, impact ionization easily occurs in channel regions of the memory element TFTs. This enables low-voltage write/erase operations to be performed on the memory elements, and hence the memory elements are less prone to deteriorate. Therefore, a nonvolatile memory capable of miniaturization can be provided.

Abstract: A FLASH device including a substrate having a protrusive portion integrally formed thereon, two floating gates, a control gate and a dielectric layer is provided. The two floating gates are disposed on two sides of the protrusive portion and respectively covering a portion of the protrusive portion. The control gate is disposed on top of the protrusive portion and sandwiched between the two floating gates. The dielectric layer is disposed between each of the two floating gates and the control gate. Because the control gate of the FLASH device is disposed on the protrusive portion, an elevated channel can be formed. Moreover, because of the position of the two floating gates, an effective floating gate (FG) length can be increased without impacting the cell density.

Abstract: Provided is a flash memory device and a method of manufacturing the same. In the method, a tunnel oxide layer pattern and a first polysilicon pattern are formed on a semiconductor substrate. A first dielectric layer including a first oxide layer, a first nitride layer, a second oxide layer, a second nitride layer and a third oxide layer is formed on the semiconductor substrate including the first polysilicon pattern. A second polysilicon pattern is formed on the dielectric layer pattern. The flash memory device includes a tunnel oxide layer pattern and a first polysilicon pattern on a semiconductor substrate; a dielectric layer on the first polysilicon pattern, including a first oxide layer pattern, a first nitride layer pattern, a second oxide layer pattern, a second nitride layer pattern and a third oxide layer pattern; and a second polysilicon pattern on the dielectric layer pattern.

Abstract: A mask ROM is provided with a plurality of memory cells each including first and second nodes, and a transistor having a source and drain connected to the first and second nodes, respectively. A first memory cell out of the plurality of memory cells further includes a first resistive interconnection which provides an electrical connection between the first and second nodes. The resistance of the first resistive interconnection is adjusted depending on data stored onto the first memory cell.