Abstract: A universal serial bus (USB) memory is disclosed. The USB memory includes a housing having a plurality of orientated indentations and a plurality of concave props, wherein the plurality of orientated indentation facilitates the USB memory to be connected while the USB memory is inserted into a female USB socket; a print circuit board assembly (PCBA) disposed in the housing, wherein the PCBA is fixed by means of pressing of the plurality of concave props; and a LED module having a LED indicator disposed in the housing and a LED module controller disposed on the PCBA, wherein a space is formed between the housing and the PCBA for disposing the LED module.

Abstract: A shielding arrangement for an electronic component mounted on a circuit board includes a shield formed by a frame sidewall arranged to be oriented upstanding from the circuit board and surrounding the electronic component mounted on the circuit board. A first cover portion substantially closes the surrounding sidewall, enclosing the electronic component on the circuit board. A conductive layer, formed by vacuum deposition covers an inside surface of the surrounding sidewall and an inside surface of the first cover portion, continuously. As an alternative to the conductive layer, the frame can be composed of an electrically conductive plastic. The first cover portion can be a stamped metal plate integrated with the frame by overmolding.

Abstract: One embodiment of the present invention provides an apparatus that reduces voltage noise for an integrated circuit (IC) device. This apparatus includes an interposer, which is configured to be sandwiched between the IC device and a circuit board. This interposer has a bottom surface, which is configured to receive electrical connections for power, ground and other signals from the circuit board, and a top surface, which is configured to provide electrical connections for power, ground and the other signals to the IC device. A plurality of bypass capacitors are integrated into the interposer and are coupled between the power and ground connections for the IC device, so that the plurality of bypass capacitors reduce voltage noise between the power and ground connections for the IC device.

Abstract: In respect to an electrical connection between a control circuit board 20 and bus bars 14 interbonded together, it is an object to enhance stability in quality and reliability in connection. As a solution for achieving the object, the control circuit board 20 is provided with a conductor segment 26 to be electrically connected to a specific one of the bus bars 14 on the opposite side of a rear surface thereof bonded to the bus bars 14, and a through-hole 24 penetrating a main body thereof at a position adjacent to the conductor segment 26 so as to expose the specific bus bar 14 therethrough. Further, an electrically-connecting member 70 is disposed to bridge over the through-hole 24 and the conductor segment 26, and soldered onto the conductor segment 26 and the bus bar portion located in the through-hole 24.

Abstract: A multi-service network element is configurable for use in various types of communications networks. The network element has a service interface card, a service interface electrical connector for receiving the service interface card, an I/O electrical connector for receiving an I/O module, and a backplane. The backplane has a first side, an opposite side, a first means for electrically connecting the service interface electrical connector to the first side, and a second means for electrically connecting the I/O electrical connector to either side of the backplane. The backplane is partitioned into columns and rows of electrical connectors. Each column corresponds to a card slot for receiving a circuit pack and each row corresponds to a section of the backplane having traces for carrying a particular type of electrical signals between circuit packs.

Abstract: An apparatus and method that permits signal traces of different widths and the same impedance to be placed on the same layer of a printed circuit board (PCB). Alternatively, signal traces of different impedances but the same width may be placed on the same layer of the PCB. Ground and power planes are paired on adjacent layers of the PCB with a portion of the power plane relative to the ground plane removed. Signal traces of the same width and different impedances or vice-versa can be placed on the same layer because each signal trace is referenced to different planes.

Abstract: An apparatus for regulating a power converter with multiple operating modes includes a switch coupled to an energy transfer element coupled between an input and an output of the power converter. A control circuit is also included, which is coupled to the switch to control the switch. The control circuit includes first and second duty cycle control modes to regulate power delivered to the output of the power converter. A transition between the first and second duty cycle control modes is responsive to a magnitude of a current flowing in the switch reaching a current threshold value.

Abstract: DC/DC converter has a transformer having primary coils connected to an input side and secondary coils connected to an output side. Each primary coil connects a full-bridge circuit comprising two switches on two legs, the primary coil being connected between the switches on each leg, each full-bridge circuit being connected in parallel wherein each leg is disposed parallel to one another, and the secondary coils connected to a rectifying circuit. An outer loop control circuit that reduces ripple in a voltage reference has a first resistor connected in series with a second resistor connected in series with a first capacitor which are connected in parallel with a second capacitor. An inner loop control circuit that reduces ripple in a current reference has a third resistor connected in series with a fourth resistor connected in series with a third capacitor which are connected in parallel with a fourth capacitor.

Abstract: A digital high voltage generating apparatus and a method thereof are provided where a switching block controls voltage generated in a second side coil of a power transformer, a digital interface block provides a communication interface, and a digital controlling block controls intermittence of the switching block. The digital controlling block includes a switching section width computing unit for computing a switching section width of the switching block, a frequency counting unit for computing a count value corresponding to a half period of an output voltage of the digital controlling block, and a switching time point determining unit for determining a switching time point of the switching block based on the computed switching section width and the count value. Improved protection of a switch from damage, by a reduction in heat-generation quantity in the switch, is one of the achieved advantages.

Abstract: In a fly-back voltage converter that includes a transformer to transform a primary current to a secondary current and a switch serially coupled to the primary winding to switch the primary current in response to a control signal, a detection signal is produced by comparing the secondary current with two threshold values after the primary current is switched off to trigger the next on-time cycle of the switch. Once the secondary current is detected to be greater than a first threshold value, it is determined that the secondary current has been switched on, and until the secondary current is detected to be lower than a second threshold value, it is determined that the secondary current is to be switched off. The hysteresis range of the threshold values prevents error detection of the secondary current.

Abstract: Techniques are disclosed to regulate an output of a power converter. One example power converter controller circuit includes a line sense input to be coupled to receive a signal representative of an input voltage of a power converter. A feedback input to be coupled to receive a feedback signal representative of an output of the power converter is also included. A drive signal generator is also included to generate a drive signal coupled to control switching of a switch to provide a regulated output parameter at the output of the power converter in response to the feedback signal. The drive signal generator is coupled to receive a plurality of inputs including the line sense input and the feedback input. The drive signal generator is coupled to latch the power converter into an off state in response to a detection of a fault condition in the power converter as detected by the plurality of inputs if the power converter input voltage is above a first threshold level.

Abstract: A frequency converter in which the inductance is reduced by enlarging the forms of bus bars which connect a P phase, an N phase of an inverter part and a positive electrode or a negative electrode of smoothing capacitors and the form of a wiring bus bar which connects an intermediate layer of capacitors which are connected in series to enlarge areas where they overlap each other, and by making currents flow in the opposite directions to each other.

Abstract: An auxiliary circuit for reducing low order current harmonics in a three-phase drive system driving a single-phase load, the three-phase drive system including a three-phase source voltage connected to a rectifier system connected to a DC link choke inductor connected to a three-phase current source inverter system.

Abstract: A semiconductor integrated circuit is electrically connected to first to fourth capacitors and includes first to eleventh switches. A tenth switch has a first terminal electrically connected to a second terminal of the second capacitor, and a second terminal electrically connected to a first terminal of the third capacitor. An eleventh switch has a first terminal electrically connected to a second terminal of the first capacitor, and a second terminal electrically connected to the first terminal of the third capacitor. A second terminal of the third capacitor is connected to a node at a fixed potential.

Abstract: A method for operation of a converter circuit is specified, wherein the converter circuit has a converter unit with a multiplicity of drivable power semiconductor switches and an LCL filter which is connected to each phase connection of the converter unit, in which method the drivable power semiconductor switches are driven by means of a drive signal which is formed from reference voltages. The reference voltages are formed by subtraction of damping voltages from reference-phase connection voltages, with the damping voltages being formed from filter capacitance currents, weighted with a variable damping factor of the LCL filter. An apparatus for carrying out the method is also specified.

Abstract: A distributed power system delivers DC power to a plurality of loads. The distributed power system includes a plurality of power converter modules having an associated DC to DC power conversion operation. Each of the modules includes a power regulation section for receiving a distributed input power from a distributed power line to generate a DC output by controlling the operation of the switching pulse generator. A processing section within the module interfaces with a data communications line for interfacing with the commands. The processing section is capable of operating in both a slave mode to receive commands from said data communication bus and a master mode for generating the commands. In at least one of the modules operating in the master mode, the processing section generates the commands for transmission over the data communications line to an address of one of the other modules.

Abstract: In one embodiment, a power converter system includes a first input terminal and a second input terminal operable to connect to an alternating current (AC) power source, and an output terminal at which an output voltage can be provided to a load. A first inductor and a first diode are connected in series between the first input terminal and the output terminal. A second inductor and a second diode are connected in series between the second input terminal and the output terminal. A first switch is connected to the first inductor and the first diode, and a second switch is connected to the second inductor and the second diode. The first switch and the second switch alternately function as a boost switch and a synchronous rectifier for charging and discharging the first and second inductors during operation of the power converter system.

Abstract: A switching pre-regulator for a bulk capacitor filter followed by a series pass regulator has a switching element controller that relies upon a large desirable leakage inductance in a main secondary winding of a power transformer acting as a swinging choke input to the bulk capacitive filter. This desirable leakage inductance limits inrush current and supplies some filtering. However, the effective value of the swinging choke is a function of load conditions, and introduces a varying phase shift that would potentially disturb the zero crossing detection used in properly activating the switching element.

Abstract: A content-addressable random access memory having magnetic tunnel junction-based memory cells and methods for making and using same. The magnetic tunnel junction has first and second magnetic layers and can act as a data store and a data sense. Within each cell, registered data is written by setting a magnetic orientation of the first magnetic layer in the magnetic tunnel junction via current pulses in one or more current lines. Input data for comparison with the registered data can be similarly set through the magnetic orientation of the second magnetic layer via the current lines. The data sense is performed by measuring cell resistance, which depends upon the relative magnetic orientation of the magnetic layers. Since data storage, data input, and data sense are integrated into one cell, the memory combines higher densities with non-volatility. The memory can support high speed, reduced power consumption, and data masking.

Abstract: In a semiconductor memory device the power level of which is strengthened by using data input/output pads in a no connection state, and a method of strengthening the power of the semiconductor memory device at a stabilized power level, the semiconductor memory device comprises: a plurality of data input/output drivers; and a plurality of data input/output pads, each connected to a corresponding one of the plurality of data input/output drivers. A first subset of the data input/output pads are connected to respective data input/output pins of a package, and several or all of a remaining subset of the data input/output pads that are not connected to data input/output pins of the package are connected to power pins of the package.

Abstract: A method of providing optimal fuse programming conditions by which an integrated circuit chip customer may program electronic fuses in the field, i.e., outside of the manufacturing test environment. An optimal fuse programming identifier, which is correlated to optimal fuse programming conditions, may be provided to the customer in readable fashion on the customer's IC chip. Accessing the optimal fuse programming identifier on the customer's IC chip, the customer may apply a fuse programming process in the field according to one or more correlated optimal fuse programming conditions.

Abstract: A memory capable of reducing the memory cell size is provided. This memory includes a plurality of memory cells including diodes, a plurality of bit lines and a first conductive type first impurity region arranged to intersect with the bit lines for functioning as first electrodes of the diodes included in the memory cells and a word line. The first impurity region is divided every bit line group formed by a prescribed number of bit lines along a direction intersecting with the extensional direction of the first impurity region.

Abstract: A first ferroelectric memory cell and a second ferroelectric memory cell each include a ferroelectric capacitor and a transistor and each store one set of information. A word-line is shared by the first and second ferroelectric memory cells. A first plate line is connected to the first ferroelectric memory cell and a second plate line is connected to the second ferroelectric memory cell. A selection transistor has one end connected to the first and second ferroelectric memory cells and the other end connected to a bit-line.

Abstract: A memory device and method of operating the same. In one embodiment, the memory device includes a resistive memory cell including a resistive memory element wherein the resistive memory element is designed to acquire a low resistance state when applying a programming voltage and acquire to a high resistance state when applying an erasing voltage; and wherein the writing time for changing the resistance state of the resistive memory element can be relatively reduced.

Abstract: In a semiconductor memory device including resistance change memory devices, when a resistance change memory device is in standby mode, the two terminals of the resistance change memory device, i.e., a bit line and a source line, are set at a precharge potential Vp, respectively. At the time of a set operation, the bit line is set to a set voltage Vd, which is higher than the precharge potential Vp, while the source line is grounded. At the time of a reset operation, bit line is grounded, while the source line is set to the set voltage Vd. At the time of a data-read operation, the source line is grounded by a read bias generation circuit, while the potential of the bit line is kept at the precharge potential Vp.

Abstract: A set bit in a phase change memory may be programmed to a reset bit using a series of pulses of increasing amplitude. An initial start pulse is applied. After the start pulse is applied, a check determines whether the bit has been reset. If not, a higher amplitude pulse is applied. Each time the pulse amplitude is to be incremented, a check determines whether a maximum safe pulse amplitude has been exceeded. The pulse amplitude is continually incremented until either the maximum is reached or all the bits to be programmed have been programmed into the correct reset state.

Abstract: This invention provides novel high density memory devices that are electrically addressable permitting effective reading and writing, that provide a high memory density (e.g., 1015 bits/cm3), that provide a high degree of fault tolerance, and that are amenable to efficient chemical synthesis and chip fabrication. The devices are intrinsically latchable, defect tolerant, and support destructive or non-destructive read cycles. In a preferred embodiment, the device comprises a fixed electrode electrically coupled to a storage medium having a multiplicity of different and distinguishable oxidation states wherein data is stored in said oxidation states by the addition or withdrawal of one or more electrons from said storage medium via the electrically coupled electrode.

Abstract: A magneto-resistive element according to an aspect of the present invention includes a free layer whose magnetized state changes and a pinned layer whose magnetized state is fixed. The free layer comprises first and second ferromagnetic layers and a non-magnetic layer which is arranged between the first and second ferromagnetic layers. An intensity of exchange coupling between the first and second ferromagnetic layers is set so that an astroid curve in a hard axis direction opens.

Abstract: A magnetoresistive element includes a first ferromagnetic layer having a first magnetization, the first magnetization having a first pattern when the magnetoresistive element is half-selected during a first data write, a second pattern when the magnetoresistive element is selected during a second data write, and a third pattern of residual magnetization, the first pattern being different from the second and third pattern, a second ferromagnetic layer having a second magnetization, and a nonmagnetic layer arranged between the first ferromagnetic layer and the second ferromagnetic layer and having a tunnel conductance changing dependent on a relative angle between the first magnetization and the second magnetization.

Abstract: A method for operating an electrically erasable programmable read only memory (EEPROM) array includes providing an array including a multiplicity of memory cells, wherein each memory cell is connected to a word line and to two bit lines, selecting one of the memory cells, and erasing a bit of the selected memory cell while applying an inhibit word line voltage to a gate of an unselected memory cell. An EEPROM array is also described, the array including a multiplicity of NROM memory cells, wherein each memory cell is connected to a word line and to two bit lines, and wherein each NROM cell is individually erasable and individually programmable without significantly disturbing unselected cells.

Abstract: A non-volatile semiconductor memory device comprises first and second sub-memory arrays and a strapping line disposed between the first and second sub-memory arrays. A programming operation of the first sub-memory array is performed by simultaneously applying a programming voltage to odd and even bit lines connected to memory cells within the first sub-memory array.

Abstract: Systems and methods in accordance with various embodiments can provide for reduced program disturb in non-volatile semiconductor memory. In one embodiment, select memory cells such as those connected to a last word line of a NAND string are programmed using one or more program verify levels or voltages that are different than a corresponding level used to program other cells or word lines. One exemplary embodiment includes using a lower threshold voltage verify level for select physical states when programming the last word line to be programmed for a string during a program operation. Another embodiment includes applying a lower program voltage to program memory cells of the last word line to select physical states. Additional read levels are established for reading the states programmed using lower verify levels in some exemplary implementations.

Abstract: A method for programming a non-volatile memory system. The method includes programming a first non-volatile storage element on a first word line and a first NAND string to store “n” bits of data. A second non-volatile storage element on the first word line and a second NAND string is programmed to store n+1 bits of data. The second non-volatile storage element is a neighbor to the first non-volatile storage element. A third non-volatile storage element on a second word line and the second NAND string is programmed to store n bits of data. The third non-volatile storage element is a neighbor to the second non-volatile storage element. A fourth non-volatile storage element on the second word line and the first NAND string is programmed to store n+1 bits of data.

Abstract: A multi-level non-volatile memory including a memory cell disposed on a substrate is provided. The memory cell includes a control gate, a charge storage layer, a doped region, a select gate, and an assist gate. The control gate is disposed on the substrate. The charge storage layer is disposed between the control gate and the substrate. The doped region is disposed in the substrate at the first side of the control gate. The select gate is disposed on the sidewall of the first side of the control gate and on the substrate between the control gate and the doped region. The assist gate is disposed on the sidewall of the second side of the control gate. An inversion layer is formed in the substrate below the assist gate when a voltage is applied to the assist gate.

Abstract: A read method of a memory device including a MLC includes the steps of performing a data read operation according to a first read command; determining whether error correction of the read data is possible; if, as a result of the determination, error correction is difficult, performing a data read operation according to a second read command; determining whether error correction of read data is possible according to the second read command; and if, as a result of the determination, error correction is difficult, performing a data read operation according to a Nth (N?3, N is an integer) read command.

Abstract: A non-volatile memory array with both single level cells and multilevel cells. The single level and multilevel cells, in one embodiment, are alternated either along each bit line. An alternate embodiment alternates the single and multilevel cells along both the bit lines and the word lines so that no single level cell is adjacent to another single level cell in either the word line or the bit line directions.

Abstract: In a nonvolatile semiconductor storage device having a plurality of NAND strings, each NAND string includes a memory cell block obtained by connecting a plurality of nonvolatile memory cells in series, a first selection gate transistor connected to a data transfer line contact, and a second selection gate transistor connected to a source line contact. The upper surface of an isolation insulating film between adjacent data transfer line contacts is higher than the major surface of a semiconductor substrate in a device area between the first selection gate transistor and data transfer line contact. Alternatively, the upper surface of an isolation insulating film between adjacent source line contacts is higher than the major surface of the semiconductor substrate in a device area between the second selection gate transistor and source line contact.

Abstract: A system and method for programming both sides of the non-volatile portion in a semiconductor memory is disclosed. The present invention erases and then programs the memory stacks in the non-volatile portion of an nvSRAM.

Abstract: A nonvolatile semiconductor memory device includes a latch configured to store data, a plurality of word lines, a driver configured to activate one of the plurality of word lines, and a plurality of nonvolatile memory cells coupled to the respective word lines, each of the nonvolatile memory cells coupled to the latch so as to exchange stored data with the latch upon activation of a corresponding one of the word lines, each of the nonvolatile memory cells including two MIS transistors and configured to store data as an irreversible change of transistor characteristics occurring in one of the two MIS transistors, wherein the driver includes at least one nonvolatile memory cell storing count data responsive to a number of times storing of data has been performed with respect to the plurality of nonvolatile memory cells, and is configured to activate one of the word lines indicated by the count data.

Abstract: A method and apparatus for correcting embedded memory that has been identified as being defective by a memory controller. The address of the defective memory is provided by the memory controller to Built-In Test (BIST) logic in combination with a Built-In Redundancy Analyzer (BIRA) to replace the defective memory element with a redundant element.

Abstract: In order to maintain the integrity of data stored in a flash memory that are susceptible to being disturbed by operations in adjacent regions of the memory, disturb events cause the data to be read, corrected and re-written before becoming so corrupted that valid data cannot be recovered. The sometimes conflicting needs to maintain data integrity and system performance are balanced by deferring execution of some of the corrective action when the memory system has other high priority operations to perform. In a memory system utilizing very large units of erase, the corrective process is executed in a manner that is consistent with efficiently rewriting an amount of data much less than the capacity of a unit of erase.

Abstract: A nonvolatile semiconductor memory device includes a string selection transistor coupled to a bit line. The device also includes a plurality of memory cells coupled in series to the string selection transistor, wherein at least one of the memory cells is configured to be in a programmed state during an erase procedure of the plurality of memory cells.

Abstract: A semiconductor memory device includes a memory cell array, a word line, a source line, a row decoder, and a source line driver circuit. The memory cell array includes a memory cell unit having a plurality of memory cells connected in series. The word line is connected to control gates of the memory cells. The source line is electrically connected to sources of the memory cells positioned on one end sides of the memory cell unit. The row decoder selects the word line. The source line driver circuit is arranged in the row decoder and applies a first voltage to the source line.

Abstract: A NAND type flash memory included with a memory cell array composed of a plurality of electronically rewritable memory cells arranged in a matrix shape, and a data inversion control section which judges whether a polarity of a “1” data or a “0” data is to be inverted based on the number of the “1” data and the “0” data of the data when data is sent to the plurality of memory cells within a simultaneous write data unit and inverts the data and in the case where it is sent to the memory cell array adds an inversion flag bit to the data which shows the inversion of the polarity.

Abstract: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To account for this coupling, the read process for a particular memory cell will provide compensation to an adjacent memory cell in order to reduce the coupling effect that the adjacent memory cell has on the particular memory cell. When reading the adjacent cell to determine the appropriate compensation, margined read voltages can be used.

Abstract: An operation method of a NOR architecture memory includes the following steps. First, a target word line is selected. Next, an initial enable voltage is applied to the target word line to charge the target word line. Then, the initial enable voltage is switched to a target voltage after a pre-charge time to make the target word line be charged to the target voltage. The initial enable voltage is higher than the target voltage. The pre-charge time corresponds to the initial enable voltage and the target voltage.

Abstract: A nonvolatile semiconductor memory for suppressing the access delay due to the parasitic capacitance between bit lines is disclosed. Bit lines are selected by a bit select signal, and the data of the memory cell selected in accordance with the level of data lines by a sense amplifier are read, after which the read data are held in a latch circuit. Then, a control signal is set to “High”, thereby to turn on a NMOS and set the data lines to a grounding potential. As a result, the charges of the selected bit lines are discharged. After that, even if adjacent bit lines are selected next for reading, the effect of the parasitic capacitance between the adjacent bit lines is obviated, and the next data can be read without causing any access delay.

Abstract: A flash based device in configured for soft programming to correct for over-erase effect; however, the soft programming current is limited so as not to exceed the current that can be supplied during soft programming. Additionally, the voltage on the source node of each cell on the flash based device is maintained at a non-zero level, in order to allow for the use of a higher word line voltage, but help prevent an over soft programming effect.

Abstract: A method and device for recovering data in a non-volatile semiconductor memory device that may include controlling a reference current by the non-volatile semiconductor memory device, reading data of at least one memory cell based on the controlled reference current, storing the read data in a buffer memory, and writing the data stored in the buffer memory to the at least one memory cell.

Abstract: A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.