Abstract: A server blade system including a middle plane board and a server blade is provided. The server blade includes a first connector for electrically connecting the middle plane board. The first connector has several pins complying with a specific connector specification. A specific first pin and a specific second pin of the pins are for USB application.

Abstract: A computing device includes a baseboard, a memory coupled to the baseboard, an input/output coupled to the baseboard and a processor system coupled to the baseboard. The processor system includes a circuit board, a central electronic control coupled to the circuit board and a processor component. The device further includes a first structure coupling the processor component to the circuit board and retaining the processor component relative to the circuit board at a selected one of a plurality of positions in both directions along an axis perpendicular to the circuit board. The first structure is movably coupled to one of the processor component and the circuit board for movement in a direction perpendicular to the first axis at least prior to being coupled to the other of the processor component and the circuit board.

Abstract: A test carrier 10 for storage devices 38 comprising a carrier base 12; a slider tray 16 slidably mounted to the carrier base 12, the slider tray 16 having at least one aperture for receiving a storage device 38 therein; at least one storage device connector 20 connected to the carrier base 12; and a tester interface 22, where, when the slider tray 16 is in a first position, the storage device 38 can be received within the at least one aperture of the slider tray 16 and, when the slider tray 16 is in a second position, an interface of the storage device 38 mates with the storage device connector 20; appropriate circuitry contained in the carrier base 12 connecting the tester interface 22 and the storage device connector 20 thereafter allowing the storage device 38 to be tested via the tester interface 22.

Abstract: A system and method for an improved multiple hard-disk-drive data-storage enclosure. Some embodiments position drives in counter-rotating pairs, each simultaneously accessing half the data, such that seek-caused actuator rotational-acceleration vibration cause simultaneous canceling rotational torque. Some embodiments position the edge of a first drive (or drive pair) at an angle to the actuator midpoint of a nearby second drive (or drive pair), such that rotational-acceleration vibration from a seek-caused actuator rotation in the first drive does not cause a rotational movement into the second drive that affects the tracking or seek operation. Some further embodiments position drives in a herringbone pattern to redirect air flow in addition to reducing rotational-acceleration vibration interaction. Other embodiments include a printed wire circuit board mounted to reduce the rotational-acceleration vibration interaction.

Abstract: The invention provides an electronic device that is environment-friendly and capable of achieving satisfactory noise prevention effect at low cost, and a housing implementing such electronic device. The housing has an electronic circuit disposed therein, and includes a component exposure section in which part of a conductive component disposed in the housing is exposed outward, a plate section made of a conductive material having a predetermined thickness, and spreading at a distance from the component exposure section, and a bridge section with the overall thickness thereof larger than the thickness of the plate section, extending along the component exposure section and electrically connecting the plate section and the conductive component.

Abstract: A latch mechanism for fixing a cover unit to a base unit of a foldable electronic device in a closed position is provided. The cover unit includes two locking portions. The base unit defines two slots. The latch mechanism includes a locking member, and at least one resilient member. The locking member is configured for being slidably received in the base unit. The locking member includes two protrusions. The locking portions of the cover unit extend through the corresponding slots of the base unit, and engage with the corresponding protrusions of the locking member for fixing the cover unit in the closed position. The resilient member is engagable with the locking member, for keeping the locking member in a locked position.

Abstract: A method and incorporated assembly is provided to enhance structural integrity and prevent interface deflection in a computer rack having a midplane and capable of housing a plurality of nodes. The assembly comprises at least one structural filler book capable of being disposed above or below said midplane where any node may be disposed having geometry and material properties to resist and counteract the plugging force of said node an causing a cancellation effect. The filler book have at least two horizontal supports being connected to one another via a vertical support and a plenum an air for directing air flow. The filler book is being secured to said rack or midplane via an engagement component disposed on one of its horizontal supports.

Abstract: A server chassis is provided for receiving a functional module therein. The server chassis includes a base with an opening defined in an end thereof for the functional module inserted therethrough, and an air flap apparatus engaging with the base. The air flap apparatus includes a shielding panel pivotably attached to the base, and a resilient member connected to the base and the shielding panel to urge movement of the shielding panel.

Abstract: The disclosed embodiments include a plurality of plenums for distributing cooling air throughout the switch. The switch is divided into separate cooling domains. Each PCB receives a separate supply of cooling air, so that no PCB is located upstream or downstream from another PCB. The present embodiments thus eliminate the problem of stack rise, which can decrease switch performance.

Abstract: A noise-reducing attachment apparatus for a heat exchanger door is provided for facilitating attenuation of noise emanating from an electronics rack. The apparatus includes a frame structure configured to coupled to the heat exchanger door. The door includes in air opening and air-to-liquid heat exchanger, and air passing through the air opening also passes across the heat exchanger. The air opening facilitates passage of external air through the electronics rack. The frame structure defines in part an airflow channel through the apparatus, wherein air passing through the air opening also passes through the airflow channel when the apparatus is operatively coupled to the door. An acoustically absorptive material, which is coupled to the frame structure and at least partially defines the airflow opening through the apparatus, is selected and positioned to attenuate noise emanating from the electronics rack when the apparatus is coupled to the heat exchanger door.

Abstract: A heat dissipation device for at least a heat-generating electronic component includes a heat sink, a fan for providing an airflow through the heat sink and a fan holder coupling the fan to the heat sink. The heat sink has a first locking part and a second locking part opposite to the first locking part. The fan holder has a first engaging part engaging with the first locking part at one side of the heat sink and a second engaging part engaging with the second locking part of the heat sink at an opposite side thereof. The first engaging part has a horizontally extending fixing arm and a barb extending downwardly from the fixing arm and hooking with a top side of the heat sink.

Abstract: An electronic module packaging system and an electronic module packaging apparatus are disclosed. The electronic module packaging system includes an exterior packing box, an electronic module packaging apparatus, and antistatic packing foam holding the electronic module packaging apparatus within the exterior packing box. The electronic module packaging apparatus includes a top component made of an antistatic material, and a bottom component made of a conductive material. The bottom component includes multiple support members to hold an electronic module in a stable position. The top component and the bottom component may be coupled with multiple securing clips.

Abstract: A power control system may use power semiconductor devices such as insulated gate bipolar transistors (IGBT's) in a switching unit to provide motor control. The IGBT's may be cooled with a system that is configured and sized to provide proper cooling at steady-state operating conditions of the switching unit. The IGBT's may be placed in thermal communication with a compartment that may contain phase change material (PCM). When and if the switching unit is operated under transient high load conditions, excess heat may be absorbed by melting of the PCM. When steady state operating conditions are restored the PCM may solidify and release its latent heat to a coolant. The PCM may thus act as a thermal buffer for the cooling system and thus may provide that the cooling system may be minimally sized.

Abstract: In some embodiments, a heatsink includes a thermally conductive core and at least ten thermally conductive fins extending quasi-radially from the thermally conductive core, wherein most of the fins are of uniform length, and wherein at least a portion of the thermally conductive core is shaped such that the fins having uniform length form a substantially rectangular cross sectional form factor. Other embodiments are disclosed and claimed.

Abstract: An apparatus for coupling a heat-generating device to a heat-removing device. The apparatus includes a thermally-conductive plate having a first side and a second side. The apparatus also includes a plurality of first channels that intersect with a plurality of second channels formed on at least one of the first side and the second side. The formation of the first channels and the second channels weaken the thermally-conductive plate. The apparatus further includes a plurality of protrusions formed by the intersection of the first channels and the second channels. The protrusions are deformable by coupling the thermally-conductive plate between the heat-generating device and the heat-removing device.

Abstract: A method and apparatus used for actuation is provided. In one embodiment, the apparatus comprises an actuation body having a gradually tapered wider end received at one end by an expandable member and at an opposing end by a drive shell. The actuation body being movable from a first position to a second position by means of the drive shell such that this movement causes a looser or tighter fit at the wider end with respect to the expandable member.

Abstract: A DC-DC converter comprising a soft-magnetic, multi-layer substrate provided with a laminated coil constituted by connecting pluralities of conductor lines, and a semiconductor integrated circuit device comprising a switching device and a control circuit, which are mounted on the soft-magnetic, multi-layer substrate; the semiconductor integrated circuit device comprising an input terminal, an output terminal, a first control terminal for controlling the ON/OFF of the switching device, a second control terminal for variably controlling output voltage, and pluralities of ground terminals; the soft-magnetic, multi-layer substrate comprising first external terminals formed on a first main surface, first connecting wires formed on the first main surface and/or on nearby layers, second connecting wires formed between the side surface of the multi-layer substrate and a periphery of the laminated coil, and second external terminals formed on a second main surface; and terminals of the semiconductor integrated circuit

Abstract: A plurality of wiring patterns are formed so as to extend in parallel with each other. A plurality of test terminals are formed in a substantially rectangular shape such that respective widths thereof increase toward respective one sides from respective ends of the plurality of wiring patterns. The plurality of test terminals in each group are arranged so as to be aligned along a length direction of the wiring patterns. The wiring patterns are formed so as to be longer in the order, and the test terminals are further away from a mounting region in the order. An interval (width of a plating resist) between the test terminals in each group and the wiring patterns in the other group adjacent thereto is set to decrease in the order.

Abstract: The present invention concerns an electronic assembly with a heat sink in particular for a discharge lamp control module for a motor vehicle headlight. The electronic assembly with heat sink comprises essentially a printed circuit and a housing able to serve for thermal insulation and/or for electrical insulation and which comprises a heat sink. The heat sink is interposed between at least one face of the printed circuit and a face of the housing, the said heat sink extending over a major part of the face of the printed circuit and comprising an adhesive face for securing it to the printed circuit on the one hand and an adhesive face for securing it to the face of the housing on the other hand.

Abstract: A latch mechanism for removably securing a module in a bay of an electronic device. The latch mechanism includes a first wireform configured to move along a first wall of the bay to latch a first side of the module and a tang configured to move substantially perpendicularly to a second side of the module to latch the second side of the module. The latch mechanism includes a control member operatively connected with the first wireform and the tang to actuate the first wireform and the tang simultaneously in response to user input such that when the module is inserted into the bay, the first wireform and the tang simultaneously latch the first side of the module and the second side of the module.

Abstract: A method includes populating components in a cavity of a substrate, disposing a polymer over the components and within the cavity. The polymer is cured and a thin film is formed on the polymer. In addition, a method includes forming an EMI shield within a medical device by depositing a thin film of metal on a surface within the medical device. The thin film of metal, of gold, aluminum, or copper, is formed by vapor deposition or sputtering. An apparatus includes a first substrate assembly including a first substrate having a cavity. A first set of electronic components are disposed within the cavity, and a first polymer is disposed over the first set of components. Deposited on an outer surface of the first polymer by vapor deposition is a thin film of metal. The thin film of metal is electrically coupled with a ground. A second substrate assembly including a second substrate is coupled with the first substrate assembly.

Abstract: An electromagnetic interference (“EMI”) shield that can help control the emission of electromagnetic radiation from an optoelectronic module in which the EMI shield is positioned. In one example embodiment, an EMI shield includes a base and plurality of flanges extending from a perimeter of the base. The base defines an optical subassembly (“OSA”) opening and a plurality of complementary structures. The OSA opening is configured to receive an OSA. Each complementary structure is configured to engage a complementary structure of an OSA connector block.

Abstract: A capacitor charging circuit is provided with a primary side output voltage sensing circuit for generating a control signal indicative of whether the output voltage has reached a desired level. The control signal is unaffected by voltage spikes occurring when the main switch is turned off. In one embodiment, the circuit filters the primary side voltage for comparison to a reference voltage in order to provide the control signal. In another embodiment, an AND gate provides the control signal indicating that the output voltage has reached the desired level only in response to the primary side voltage being greater than a reference voltage and the secondary current being discontinuous. In a further embodiment, an AND gate provides the control signal indicating that the output voltage has reached the desired levels only in response to a predetermined delay occurring after the primary side voltage becomes greater than a reference voltage and the secondary current being discontinuous.

Abstract: The invention concerns a method for controlling a direct voltage source with a first direct voltage source (2) and a voltage monitoring device (24), which monitors an output voltage of the first direct voltage source (2) and acts upon a control device (31), the control device (31) controlling the working state of the first direct voltage source (2). Further, the invention concerns a voltage supply device (22) with which the method can be used. In this connection it is endeavored to reduce the risk of an increase in voltage in a circuit with several direct voltage sources. For this purpose, a second direct voltage source (3) produces a voltage change at the voltage monitoring device (24).

Abstract: A night vision system comprising a power system having a low voltage unit coupled to a high voltage unit; the low voltage unit including a low voltage controller generating a pulse width code; the high voltage unit including an opto-isolator for receiving the pulse width code from the low voltage controller, a high voltage controller operative in response to the pulse width code to generate an output pulse, a pulse shaping module receiving the output pulse and generating a control pulse; and power electronics operative in response to the control pulse.

Abstract: A power converter controlling apparatus that can prevent burnout caused by overcurrent and/or overvoltage generated by low power index operation or output short circuit in a high frequency power converter employing a digital controlling method, and a method thereof. The power converter controlling apparatus includes a digital controller which outputs a gate signal for controlling intermittent operation of a predetermined switch based on inputted control data, a detector which generates a detection signal in response to generation of overcurrent and/or overvoltage, and a registration maintenance unit for maintaining a state where the output of the gate signal is shut off, when the detection signal is generated.

Abstract: A dual input AC/DC power converter (10) having dual inputs (12, 14) adapted to receive both an AC and DC input and provide a selectable DC voltage output (16) and a second DC output (18). The dual input AC/DC power converter (10) comprises a power converter circuit (20) having an AC-to-DC converter (22), a DC-to-DC booster converter (24), a feedback circuit (26), a filter circuit (25) and a DC-to-DC buck converter (28). Advantageously, the power converter (10) resolves many of system management problems associated with carrying all of the different interface components necessary to power a wide variety of mobile products from either an AC or DC power supply. In addition, the power converter (10) also advantageously includes dual output voltage terminals (16/18) to allow for multiple mobile devices of varying power requirements to be powered, simultaneously, by a single converter.

Abstract: A programmable power supply provides multiple output channels that may be independently driven to vary the frequency and duty cycle of each channel. The power supply includes the capability of receiving a program via a program interface on the power supply. The power supply also includes the capability of reading a program from a device that is plugged into the power supply's output connector. In this manner, a device to be powered (such as an EL panel sign with multiple segments) may contain a program that specifies how the segments are to be driven. This allows the power supply to dynamically reconfigure itself for many different signs by simply plugging a different sign into its output connector. The preferred embodiments also provide an improved connector system for EL panel signs, and includes output compensation to automatically compensate for degradation in an EL panel over time.

Abstract: A high performance memory based computation system comprises an array of memory cells. Each memory cell stores a logic data corresponding to a chosen combination of inputs based on a specific logic function. For improved performance, the memory cell array can be divided into sub-blocks; and the sub-blocks can be serially disposed or juxtaposed. The performance of the memory based computation system can further be improved by removing the repeated memory cell rows, column, and/or sub-arrays.

Abstract: A ferroelectric memory device includes: a memory cell having a transistor and a ferroelectric capacitor connected in series between a bit line and a plate line, and a connecting section below the ferroelectric capacitor; a dummy cell having a transistor, a ferroelectric capacitor and a connecting section, wherein the dummy cell has an electrically disconnected section among the bit line, the transistor, the ferroelectric capacitor, the connecting section and the plate line.

Abstract: In a method of providing an operating characteristic of a resistive memory device, material of an electrode thereof is selected to in turn provide a selected operating characteristic of the device. The material of the electrode may be reacted with material of an insulating layer of the resistive memory device to form a reaction layer, the selected operating characteristic being dependent on the presence of the reaction layer.

Abstract: One embodiment of the invention relates to a method for conditioning resistive memory cells of a memory array with a number of reliable resistance ranges, where each reliable resistance range corresponds to a different data state. In the method, group of at least one resistive memory cell is accessed, which group includes at least one unreliable cell. At least one pulse is applied to the at least one unreliable cell to shift at least one resistance respectively associated with the at least one unreliable cell to the highest of the reliable resistance ranges. Other methods and systems are also disclosed.

Abstract: An array of non-volatile memory cells arranged in logical columns and logical rows, and associated circuitry to enable reading or writing one or more memory cells on a row in parallel. In some embodiments, the array of memory cells may include a phase change material. In some embodiments, the circuitry may include a write driver, a read driver, a sense amplifier, and circuitry to isolate the memory cells from the sense amplifier with extended refresh.

Abstract: Between the value of an electric current and the supply duration for which the electric current is supplied that cause magnetization reversal, there is the relation of monotonous decrease. This means that, as the supply duration is shortened, the threshold current value for causing the magnetization reversal is larger. Therefore, in terms of suppressing occurrence of read disturb, the read current supply duration may be shortened to increase the threshold value of the current causing the magnetization reversal and thereby ensure a sufficient read disturb margin. Therefore, the read current supply duration may be shortened relative to the write current supply duration ensure the read disturb margin and suppress occurrence of read disturb.

Abstract: A toggle magnetic random access memory includes a first memory array, a second memory array and a controller. The first memory array includes a plurality of first memory cells including magnetoresistive elements. The second memory array includes a plurality of second memory cells including magnetoresistive elements and differs from the first memory array in write wirings used for writing. The controller controls the first memory array and the second memory array such that a first state in which a first burst write operation in the first memory array is executed and a second state in which a second burst write operation in the second memory array is executed are alternately executed in a continuous burst write mode. Accordingly, the continuous burst write operation can be executed at the high speed without any drop in the reliability and any increase in the circuit area.

Abstract: In a method for obviating the effect of disturb voltages in a data storage apparatus employing passive matrix addressing, an application of electric potentials for an addressing operation is according to a voltage pulse protocol. The data storage cells of the apparatus are provided in two or more electrically separated segments each constituting non-overlapping physical address subspaces of the data storage apparatus physical address space. A number of data storage cells in each segment are preset to the same polarization by an active voltage pulse with a specific polarization. In a first addressing operation one or more data storage cells are read by applying an active pulse with the same polarization to each data storage cell and recording the output charge response. On basis thereof the output data in subsequent second addressing operation are copied onto preset data storage cells in another segment of the data storage apparatus, this segment being selected on the basis of its previous addressing history.

Abstract: A memory element, a threshold switching element, or the series combination of a memory element and a threshold switching element may be used for coupling conductive lines in an electrically programmable matrix array. Leakage may be reduced by optionally placing a breakdown layer in series with the phase-change material and/or threshold switching material between the conductive lines. The matrix array may be used in a programmable logic device.

Abstract: A memory device as described herein includes a memory member contacting first and second interface structures. The first interface structure electrically and thermally couples the memory member to access circuitry and has a first thermal impedance therebetween. The second interface structure electrically and thermally couples the memory member to a bit line structure and has a second thermal impedance therebetween. The first and second thermal impedances are essentially equal such that applying a reset pulse results in a phase transition of an active region of the memory member spaced away from both the first and second interface structures.

Abstract: An integrated circuit includes an array of resistance changing memory cells and a first circuit. The first circuit is configured to set a selected memory cell to a crystalline state by applying a decreasing stair step pulse to the selected memory cell. The pulse is based on a reset current distribution for the array of memory cells.

Abstract: When a phase-change element that can transition between a reset state (amorphous state) and a set state (crystalline state) is to be caused to transition to the reset state, a first pulse having a first voltage is applied to the phase-change element. The first voltage is higher than the threshold voltage in the reset state, and can cause current to flow that corresponds to an amount of generated heat required for placing the element in the reset state. When the phase-change element is to be caused to transition to the set state, a second pulse having a second voltage and the same time width as the first pulse is applied to the phase-change element. The second voltage that is higher than the threshold voltage but lower than the first voltage, and can cause only a current to flow that does not attain the necessary amount of generated heat.

Abstract: Method of magnetization reversal of the magnetization (M) of at least one first magnetic memory element of an array of magnetic memory elements comprising the steps of: applying a first magnetic field pulse to a first set of magnetic memory elements, and applying a second magnetic field pulse to a second set of magnetic memory elements, such that during the application of the first and second magnetic field pulse the magnetization (M) of said first magnetic memory element which is to be reversed upon the field pulse decay performs approximately an odd number of a half precessional turns, wherein the magnetization (M) of at least one second magnetic memory element which is not to be reversed upon the field pulse decay performs approximately a number of full precessional turns.

Abstract: A data reading circuit of a magnetic memory applicable for reading data of a magnetic memory includes a first transistor, a second transistor connected to the first transistor in series, a third transistor, a fourth transistor connected to the third transistor in series, a first transmission gate electrically connected to the first transistor, a second transmission gate electrically connected to the first and third transistors, a comparison circuit having two input ends respectively connected to the first transistor, and a storage capacitor having an end electrically connected to the first transistor and the other end connected to a power end.

Abstract: A method and system for extending the life span of a flash memory device. The flash memory device is dynamically configurable to store data in the single bit per cell (SBC) storage mode or the multiple bit per cell (MBC) mode, such that both SBC data and MBC data co-exist within the same memory array. One or more tag bits stored in each page of the memory is used to indicate the type of storage mode used for storing the data in the corresponding subdivision, where a subdivision can be a bank, block or page. A controller monitors the number of program-erase cycles corresponding to each page for selectively changing the storage mode in order to maximize lifespan of any subdivision of the multi-mode flash memory device.

Abstract: A nonvolatile memory with a modified channel region interface, such as a raised source and drain or a recessed channel region is included.

Abstract: A memory cell includes a first transistor and a second transistor. The first transistor is configured as an erase capacitor, and the second transistor is configured as a program transistor. Gates of the first and second transistors are coupled together to form a floating gate. During an erase operation, a first voltage (like 12V-24V) is applied to the first transistor, such as to a source, a body, and a drain of the first transistor. A second voltage (like ground) is applied to the second transistor, such as to a source and a body of the second transistor. A drain of the second transistor could be grounded. The first and second voltages cause electron discharge from the floating gate through the first transistor and electron injection through the second transistor onto the floating gate. This helps to prevent an over-erase condition from forming in the memory cell.

Abstract: Provided are a circuit and method for generating a program voltage, and a non-volatile memory device using the same. The circuit, which generates a program voltage for programming a memory cell of a semiconductor memory device, includes a program voltage controller and a voltage generating unit. The program voltage controller generates a program voltage control signal according to program/erase operations information. The voltage controller generates a program voltage in response to the program voltage control signal.

Abstract: A semiconductor memory device includes first and second memory cell blocks, a block decoder, and first and second block switches. The first and second memory cell blocks have a plurality of memory cells connected in a string structure and are respectively disposed in neighboring planes. The block decoder outputs first and second block select signals in response to pre-decoded address signals and first and second plane select signals, which are respectively enabled according to an enable state of the planes. The first and second block switches connect global word lines to word lines of the first and second memory cell blocks in response to the first and second block select signals, respectively.

Abstract: NAND flash memory cell array having control gates and charge storage gates stacked in pairs arranged in rows between a bit line diffusion and a common source diffusion, with select gates on both sides of each of the pairs of stacked gates. The gates in each stacked pair are self-aligned with each other, and the charge storage gates are either a nitride or a combination of nitride and oxide. Programming is done by hot electron injection from silicon substrate to the charge storage gates to build up a negative charge in the charge storage gates. Erasing is done by channel tunneling from the charge storage gates to the silicon substrate or by hot hole injection from the silicon substrate to the charge storage gates. The array is biased so that all of the memory cells can be erased simultaneously, while programming is bit selectable.

Abstract: The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information.

Abstract: Techniques are described to monitor charging of an integrated circuit during manufacturing processes. In one example, an integrated circuit includes first and second pads adapted to be charged by charge carriers during manufacture of the integrated circuit. The integrated circuit also includes a reference nonvolatile memory cell comprising a floating gate and a control gate, wherein the control gate is coupled to the first pad. The integrated circuit further includes a charging protection device coupled to the control gate of the reference memory cell and adapted to limit the gate voltage of the control gate induced by the charge carriers. In addition, the integrated circuit includes a charging monitor nonvolatile memory cell comprising a floating gate and a control gate, wherein the control gate is coupled to the second pad but not to a charging protection device adapted to limit the gate voltage of the control gate.