Abstract: A memory device includes a group of memory cells organized in rows and columns and a first addressing circuit for addressing said memory cells of said group on the basis of a cell address. The device further includes a plurality of sets of reference cells, associated to the group, each of said set having a plurality of reference cells, and a second addressing circuit for addressing one of the reference cells during operations of read and verify of addressed memory cells.

Abstract: A method and apparatus for testing correct operation of a page decoder in a memory is provided. In one implementation, the method includes erasing the memory to reset all memory cells associated with each of the N pages in the memory, and iteratively generating a unique bit sequence of M bits and programming the unique bit sequence into a plurality of the N pages at a given time until each of the N pages contains a unique bit sequence relative to other pages in the memory. Responsive to each of the N pages having a unique bit sequence, the method further includes using the page decoder to read out each unique bit sequence associated with the N pages to verify correct operation of the page decoder.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: a memory cell array having: a cell string including a plurality of memory cells connected in series; a plurality of word lines respectively connected to the plurality of memory cells; a source side selecting gate connected to one end of the cell string; and a drain side selecting gate connected to the other end of the cell string; a word line selector that selects one of the word lines connected to a target memory cell to be written; and an equalizing unit that equalizes voltages of the plurality of word lines after data write of the target memory cell is finished.

Abstract: An electronic circuit arrangement includes at least one memory element in which at least two electrical quantities can be stored. A switching unit is electrically connected to the memory element and has at least one first circuit path and a second circuit path. A storage unit has a first partial storage unit and a second partial storage unit. Each partial storage unit is set up for storing at least one electrical quantity. The switching unit is set up in such a way that it can sequentially pass a first one of the at least two electrical quantities along the first circuit path to the first partial storage unit and a second one of the at least two electrical quantities along the second circuit path to the second partial storage unit.

Abstract: A computational memory device includes an array of memory cells arranged in rows and columns, and a pair of read word lines associated with each row of the array. The array is configured to implement, for a given cycle, either a read operation of data contained in a single selected row, or one of a plurality of different bit wise logical operations on data contained in multiple selected rows.

Abstract: A memory system having a plurality of DRAMs which are selectively provided non-inverted or inverted signals. The DRAMs have the ability to accept non-inverted or inverted address/command signals from a register that drives a plurality of signals simultaneously. The system includes DRAM receivers with programmable input polarity and a register with programmable output polarity.

Abstract: A buffer component for a memory module having a plurality of memory components includes item of access information in accordance with a data transmission protocol, the address, clock, control and command signals depending on the access information, a second data interface for driving a clock signal and address and command signals to the plurality of memory components and for driving a control signal to a group of the plurality of memory components in accordance with a signaling protocol, wherein an activation of the memory components and an acceptance of the address and command signals are effected in a manner dependent on the control signals, and a control unit which applies the address and command signals to the plurality of memory components during a first clock period of the clock signal and applies the control signal for activating the group of the plurality of memory components to the group of the plurality of memory components to be activated when address and command signals are present, in a succeedin

Abstract: A latch structure includes a first inverter that includes a first PMOS transistor and a first NMOS transistor, and a second inverter that includes a second PMOS transistor and a second NMOS transistor, receives an output signal of the first inverter, and outputs an input signal to the first inverter. The sources of the first and second transistors of the same type are connected to a common straight source line.

Abstract: An internal voltage generator stably supplies an internal voltage in a semiconductor device. The internal voltage generator includes: a first internal voltage generating means for supplying a first internal voltage which has a level corresponding to a first reference voltage using an external voltage; a second internal voltage generating means for supplying a second internal voltage which has a level corresponding to a second reference voltage using the external voltage; and a third internal voltage generating means for supplying a third internal voltage which has a level corresponding to a third reference voltage generated based on the first internal voltage, using the second internal voltage as a power source.

Abstract: A driver circuit for an integrated circuit device includes a transistor that has a gate terminal, a source terminal, and a bulk substrate terminal. The source terminal is connected to the bulk substrate terminal. A pull-up circuit is connected between a power supply node and the source terminal. The pull up circuit is configured to increase a voltage at the source terminal and the bulk substrate terminal of the transistor responsive to a control signal.

Abstract: An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating toggling Read/Write control line at cycle frequency. Control line transition terminates access and initializes another burst access. Write cycle times are maximized thereby allowing increases in burst mode operating frequencies. Logic near sense amplifiers control write-data drivers thereby providing maximum write times without crossing current during I/O line equilibration. By gating global write-enable signals with global equilibrate signals locally at sense amps, local write-cycle control signals are provided and valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory.

Abstract: An automatic redundancy system may exploit an existing microprocessor management system on chip for carrying out autonomously, without communicating with an external testing machine, the operations of: writing data in the memory array according to one or more pre-established test patterns, verifying data successively read from the memory array, and substituting failed elements of the memory array with equivalent redundancy structures. A logic structure may detect and store memory array failures upstream of the output data path. Thereby, data collection relating to failures may be accomplished more quickly and without any interaction with the testing machine apart from communicating the end of the execution of the redundancy process.

Abstract: A semiconductor memory device includes: an input pad set configured to receive an external input signal and a reference voltage; an input buffer set configured to detect and transmit the input signal to an internal circuit of the semiconductor memory device by comparing the input signal with the reference voltage; and a reference voltage generation circuit configured to generate the reference voltage to supply the reference voltage to the input pad set and the input buffer set during a test operation, the reference voltage generation circuit being deactivated after the semiconductor memory device is packaged.

Abstract: A semiconductor memory device includes a memory cell array, word line, row decoder, bit line, sense amplifier, dummy cell array, dummy bit line, sense amplifier activation circuit, and signal interconnection. The word line is connected to memory cells arrayed in the column direction. The row decoder is connected to the word line. The bit line is connected to memory cells arrayed in the row direction. The sense amplifier is connected to the bit line. Dummy cells are arrayed in the row direction between the row decoder and the memory cell array. The dummy bit line is connected to the dummy cells. The sense amplifier activation circuit transmits a sense start signal for setting a sense start timing to the sense amplifier through the signal interconnection. In this arrangement, the signal delay of the word line is set to be equal to that of the signal interconnection.

Abstract: A memory device that can provide good timing margins for read and write operations is described. In one design, the memory device includes a memory array, a timing control circuit, and an address decoder. The memory array includes memory cells for storing data and dummy cells to mimic the memory cells. The timing control circuit generates at least one control signal used for writing data to the memory cells and having timing determined based on the dummy cells. The timing control circuit may generate a pulse on an internal clock signal with a driver having configurable drive strength and a programmable delay unit. The pulse duration may be set to obtain the desired write timing margin. The address decoder activates word lines for rows of memory cells for a sufficiently long duration, based on the internal clock signal, to ensure reliable writing of data to the memory cells.

Abstract: A semiconductor device temperature sensor produces a reference level for temperature detection from two or more reference levels of different temperatures to detect a temperature. The temperature sensor is applied for detecting the temperature of a semiconductor storage device having a memory unit which requires a refresh action. A refresh cycle control circuit provided in the semiconductor storage device controls the cycle of the refresh action for the memory unit in response to an output of the temperature sensor.

Abstract: Partial refresh information indicating enabling/disabling of a refresh operation is set according to an external input and is output as a partial set signal. A refresh request signal is output periodically corresponding to a memory block for which a refresh operation is enabled. The partial set signal is masked so as to enable a refresh operation for all of the memory blocks during a period in which the partial refresh information is changed by the external input. Thus, it is possible to prevent disabling of a refresh operation in response to a refresh request even when timing of changing the partial refresh information and timing of occurrence of the refresh request signal overlap. Consequently, the refresh operation can be executed securely, and malfunctioning of the semiconductor memory can be prevented.

Abstract: A self-refresh control circuit includes a first constant current generating circuit that generates a constant current to change depending on the temperature, a second constant current generating circuit to generate a constant current not depending on the temperature, a current-cycle converting circuit selectively connected to the first constant current generating circuit and the second constant current generating circuit and converting the constant currents inputted from the first constant current generating circuit and the second constant current generating circuit into a test refresh cycle used for setting the refresh cycle.

Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

Abstract: Disclosed herein are a semiconductor memory device and word line addressing method. The semiconductor memory device comprises a memory array comprising a plurality of word lines arranged in a predetermined sequence, and a word line driver adapted to sequentially address the plurality of word lines in a discontinuous manner relative to neighboring word lines. The method comprises addressing a plurality of word lines in a discontinuous manner relative to the predetermined sequence, such that neighboring word lines in the plurality of word lines are not coincidently addressed.

Abstract: A semiconductor memory device including a memory cell array, a first row decoder adjacent the memory cell array, and a second row decoder adjacent the memory cell array. A memory cell array may include first and second memory cell blocks on respective first and second semiconductor layers. The first memory cell block may include a first word line coupled to a first row of memory cells on the first semiconductor layer, the second memory cell block may include a second word line coupled to a second row of memory cells on the second semiconductor layer, and the first word line may be between the first and second semiconductor layers. The first row decoder may be configured to control the first word line, and the second row decoder may be configured to control the second word line. A first wiring may electrically connect the first row decoder and the first word line, and a second wiring may electrically connect the second row decoder and the second word line.

Abstract: There are provided a semiconductor memory device and a burn-in test method thereof. A semiconductor memory device according to an aspect of the invention includes a plurality of memory cell blocks, each of which includes a plurality of memory cells that are respectively coupled to a plurality of word lines and a plurality of bit lines, a word line control unit activating word lines in memory cell blocks that correspond to row address signals and word lines in memory cell blocks that do not correspond to the row address signals, during a test operation, and a write circuit writing data in the memory cell blocks that correspond to the row address signals and not writing data in the memory cell blocks that do not correspond to the row address signals, during the test operation.

Abstract: A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data.

Abstract: A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data.

Abstract: Disclosed is a system that generates a write count value for indicating whether data can be read from a FIFO and a system that generates a read count value for indicating whether data can be written to a FIFO. Each of these systems operates in two separate clock domains. In the system that generates a write count value, write strobes are stored in parallel in a register in a first clock domain. The plurality of synchronizers trigger on a rising edge of the write strobe that is stored in the parallel register and generate an increment pulse in a second clock domain. An up/down counter reads the increment pulse in parallel and increments the up/down counter in parallel. A decrement signal from a read strobe decrements the up/down counter. The output of the counter is fed to a register that provides a write counter value to handshake logic that indicates whether data can be read from a FIFO without underflowing the FIFO.

Abstract: A method for measuring water-flow noise over a hydrophone comprising: coupling the hydrophone to a distal end of a hydrodynamic-drag-reduced beam, which has a proximal end that is rotatably connected to a frame; pivoting the beam through water; and recording the water-flow noise generated by the water flowing around the hydrophone.

Abstract: The present invention relates to an improved autonomous node seismic recording device having an integrated modular design and one or more features that assist coupling of the unit to the sea floor in order to improve the vector fidelity of seismic signal measurement.

Abstract: Marine towed streamer seismic data are combined from a first survey and a second survey, wherein the first survey and the second survey are shot with a bin size of L×L and the second survey is shot with a shooting direction rotated 90° relative to the shooting direction of the first survey. The combined seismic data from the first and second surveys are binned on a bin grid with a bin size of L 2 × L 2 and with a bin grid orientation rotated 45° relative to the shooting directions of the first and second surveys. Then, seismic data processing is applied to the binned seismic data to create an image of the Earth's subsurface.

Abstract: Pressure records and vertical particle velocity records from dual sensor towed streamer data are transformed to the inline wavenumber domain. A series of scaling filters are applied to the transformed vertical particle velocity records at each inline wavenumber, wherein each of the series of scaling filters is calculated for a different cross-streamer wavenumber range and in blocks of inline traces in which all seismic events are approximately linear. The pressure spectrum and the scaled vertical particle velocity spectrum are combined to separate upgoing and downgoing wavefield components. The separated upgoing and downgoing wavefield components are inverse-transformed back to the time-space domain.

Abstract: A method and apparatus for processing acoustic data recorded by a subterranean receiver array. The method includes emitting an acoustic signal into a formation, receiving the signal after it passes through the array, and processing the data with semblance and phase velocity processing. Semblance and phase velocity plots are generated and combined into a single plot. The phase velocity processing creates phase separation lines, the phase separation line that crosses the closest contour of the semblance plot is identified. The point where the intersecting phase separation line crosses an associated tool line marks the slowness and travel time that provides maximum coherence.

Abstract: An acoustic borehole logging system for generation and detection of multipole modes used to determine elastic properties of earth formations characterized as inhomogeneous anisotropic solids. The system concurrently generates and senses monopole, dipole, quadrupole and any higher order pole in the borehole/formation system in order to characterize the elastic properties and stress state of material penetrated by the borehole. Multipole modes of all orders are induced simultaneously without the need for separate transmitter and receiver systems. Performance of the logging system is not compromised due to eccentering of the axis of the tool in the borehole, tool tilt with respect to the axis of the borehole, or mismatch of response sensitivity of multiple receivers within the tool.

Abstract: An underwater recognition device, system and method is provided. The system includes an underwater information collection sub-system for collecting sensor signals for underwater recognition. An underwater information processing sub-system is also provided, having at least one input port coupled to the underwater information collection sub-system and creating numerical or graphical representations of underwater information. In order to facilitate presentation of the information to a user, a speech signal processing sub-system integrated with the underwater information processing sub-system or coupled to an output port of the underwater information processing sub-system is provided. The speech signal sub-system processes numerical or graphical representations of underwater information into speech output signals.

Abstract: Sampling of a captured signal is synchronized to a tonal which may be unstable in frequency detected in the signal to cause it and all of its harmonics, sub-harmonics and fundamental to appear to have a substantially constant frequency relative to the sampling rate even if some related signals are otherwise undetectable amid noise. By adjusting an integration period of a fast Fourier transform to extract an intrinsic bandwidth, substantial signal processing gain can be obtained for the tonal and harmonically related signals, even if otherwise undetectable. Signal processing may be performed in either the time domain or the frequency domain. Recursive processing is performed to observe unrelated tones by grouping of tones which are harmonically related and supports detection of relationships between acoustic signal sources.

Abstract: To provide a portable electronic timepiece capable of downsizing a product without reducing a display area. Zebra rubbers are respectively fixed attached to left and right side faces of a contact member attached portion of a case by making a fixed contact portion constituting a button shaft opposed face thereof disposed on an extension of a button shaft and bringing a section connecting portion thereof into contact with connecting patterns of a contact/main board connecting portion of a main board. When the button shaft is inserted into a button shaft guide hole, a front end thereof is brought into contact with a surface of a bowl type rubber switch member having a section in a channel-like shape.

Abstract: Provided is a watch capable of performing digital display as well as analog display. The watch can offer digital display without posing disadvantages peculiar to a liquid crystal panel. On the other hand, the watch can reduce the restrictions in design and make the digital display larger and easier to see. The watch includes a light-shielding plate 22 on the rear side of the dial 24. In the light-shielding plate, light-transmitting holes 23 are made piercing from a front of the light-shielding plate to a rear thereof. Thin chip LEDs 17 are inserted in the light-transmitting holes, and mounted on a circuit board 16. The circuit board is placed on the rear side of the light-shielding plate. On the rear side of the circuit board, an analog movement 13 is provided, and an LED drive circuit 33 for driving the LEDs is placed. Thus, the LEDs 17 for digital display are placed on the rear side of the dial.

Abstract: A display mechanism is described, driven by the hour wheel of a mechanical or quartz horological movement, the hour wheel driving a cam controlling a rack turning about an axis and arranged in engagement with a pinion, secured to an hour hand, the cam having a configuration allowing different spaces or angles between the hours to be displayed.

Abstract: An optical system (20) for efficiently collimating an elliptical light beam includes a light source (21), a first lens (22), a second lens (23), and a third lens (24). The light source is adapted for providing an elliptical light beam defining different diverging angles in different directions, wherein any cross-section of the elliptical light beam emitted from the light source defines a long axis and a short axis which are perpendicular to each other. The first lens, the second lens, and the third lens are used for reconfiguring the elliptical light beam, thus obtaining a round light beam having equivalent short axis and long axis, and equivalent diverging angles in both horizontal direction and vertical direction. Optical centers of the first lens, the second lens, and the third lens commonly define a common optical axis along which the elliptical light beams travels.

Abstract: A method of automatically pausing an optical pickup in a DVD-RAM disc drive includes driving a DVD-RAM disc; determining whether a tracking error signal is generated during the driving of the DVD-RAM disc; generating a land/groove signal to discern land tracks and groove tracks of the DVD-RAM disc; determining from which track the tracking error signal has been generated in response to the determination that the tracking error signal has been generated; generating a jump signal in response to a state of the land/groove signal varying; and moving the optical pickup back by ½ of a track in response to the jump signal.

Abstract: A focusing controller and a method thereof for an optical disk drive. The focusing controller includes a filter which filters out a high-frequency component of the track error signal to output an adjusted signal, a coupler which couples the focus error signal with the adjustment signal to generate a coupled signal. The focusing controller further includes a focus compensator which receives the coupled signal and output the focus control signal to control position of the pick up head of the optical disk drive out of focus such that the coupling of the track error signal with the focus error signal is improved and also the stability of the servo system. While seeking ended, the offset signal is removed to resume the position of the optical pick-up head to the normally focus position.

Abstract: The adjustment of regional code information in which a first region code and a first nation code associated with the first region code are received from an optical disc. At least one of a broadcasting signal or an IP address are received at an electronic device, such as a DVD player. A second nation code is extracted from the broadcasting signal and/or the IP address, and a second region code associated with the second nation code is determined. The second region code is compared with the first region code, and the second region code and the second nation code are stored at the device if the first region code and the second region code do not match.

Abstract: There are included a plurality of record information recording areas (OPC areas PCA0, user data areas 109-0 or spare areas SA) for recording record information; a management information recording area (management area MA) for recording a plurality of management information for managing the respective ones of the plurality of record information recording areas; and a reliability information recording area (management area MA) for recording a plurality of reliability information (reliability flag group 150) that indicate, for each of the plurality of management information (120, 130 or 140), reliability as to whether the plurality of management information are correctly updated.

Abstract: As an optical disc is being rotated within an optical drive, an optical mechanism of the optical drive traces a discrete spiral path relative to the optical disc. As the discrete spiral path is traced by the optical mechanism of the optical drive, the optical mechanism selectively writes to the optical disc.

Abstract: A recording/reproduction apparatus, comprising a first recording section for recording test information onto a medium using at least one recording power, a reproduction section for reproducing at least one test signal indicating the test information from the medium, and a second recording section for recording information onto the medium using one of the at least one recording power. The reproduction section comprises a decoding section for performing maximum likelihood decoding of the at least one test signal and generating at least one binary signal indicating a result of the maximum likelihood decoding, a calculation section for calculating a reliability of the result of the maximum likelihood decoding based on the at least one test signal and the at least one binary signal, and an adjustment section for adjusting a recording power for recording the information onto the medium to the one recording power based on the reliability.

Abstract: A method for determining recording laser power on a super-resolution optical recording medium, on which information is recorded on a super-resolution optical recording medium by irradiating a laser beam modulated into a recording pulse train according to recording data to thereby form a recording mark train including recording marks and spaces smaller than the resolution limit of a reproduction optical system and recording marks and spaces equal to or larger than the resolution limit, is provided. At the time of recording, the method determines a minimum value and a maximum value of recordable laser powers determined by test-writing before recording, and determines a maximum value of a recordable range of laser power by adding to the minimum value one-third of a difference between the maximum value of the recordable laser powers and the minimum value. The method determines an optimal range of recording laser power from the minimum value of recordable laser powers to the maximum value of the recordable range.

Abstract: A disc with a temporary defect management information area and a defect management area includes a defect management area that is present in at least one of a lead-in area, a lead-out area, and an outer area, a temporary defect information area which is formed in the data area and in which temporary defect information is recorded, and a temporary defect management information area which is present in at least one of the lead-in area, and the lead-out area. Accordingly, it is possible to record user data in a recordable disc, especially, a write-once disc, while performing defect management thereon, thereby enabling efficient use of a defect management area having a limited recording capacity.

Abstract: To discriminate a disk in a short time, a calculating part 16 measures an amplitude of one of a focus error signal and a tracking error signal, which are output from a differential signal generating part 15, several times, and outputs the measured amplitudes to a controller 20. The controller 20 compares the input amplitudes with threshold values stored in a memory 21, respectively, and determines whether or not an amplification gain of one of the focus error signal and the tracking error signal is changed. If it is determined that the amplification gain of one of the focus error signal and the tracking error signal is changed, the controller 20 changes the amplification gain of one of the focus error signal and the tracking error signal to an amplification gain represented by one of the threshold values and discriminates the kind of an optical disk based on the changed amplification gain.

Abstract: A BCA (Burst Cutting Area) code including a unique disk code indicating the type of a disk is written in a BCA code area of the disk. If the disk is mounted into the optical disk player, the optical disk player reads data written in the BCA code area, extracts the disk code contained in the read data, and confirms the type of the disk corresponding to the extracted disk code by retrieving a disk code table in which disk codes corresponding to the types of disks are mapped.

Abstract: An S-curve discriminating portion discriminates that a recording face of an optical disk is opposed to a pickup when a normal S-curve appears in a waveform of a focus error signal Fe that appears when an objective lens fluctuates vertically, while discriminates that a label face is opposed when the waveform of the focus error signal is distorted and two S-curves with large and small magnitudes appear. A signal indicating this discriminated result is supplied to a control portion for controlling respective portions of an optical disk drive.

Abstract: The present invention relates to apparatuses and processes for recording dye-based recordable DVD media in higher quality at higher linear recording velocity, and provides an apparatus for recording a dye-based recordable DVD medium comprising a shortest mark recording unit, a second mark recording unit, and a cooling pulse irradiating unit, wherein the dye-based recordable DVD medium comprises a substrate and a recording layer formed on the substrate, the substrate comprises a guide groove to which wobble is formed, and the recording layer comprises at least an organic dye, the shortest mark recording unit is configured to record each of the shortest marks by use of one pulse beam of which the rear edge is more energized than the front edge, the second mark recording unit is configured to record each of the marks other than the shortest marks by use of one pulse beam of which the two sites of front and rear edges are energized, the cooling pulse irradiating unit is configured to irradiate cooling pulse laser

Abstract: A method and apparatus for overwriting data in a probe-based data storage device wherein data is represented by the presence and absence of pits formed in a storage surface by a probe of the device is provided. Input data is first coded such that successive bits of a given value x in the coded input data (b0, b1, b2, . . . ,) are separated by at least d bits of the complementary value {tilde over (x)}, where d is a predetermined number?2. Overwrite data bits (v0, v1, v2, . . . ,) are then generated by encoding the coded input data bits (b0, b1, b2, . . . ,).