Abstract: One example of a test board includes first and second communication ports configured for communication with a master device and a DUT, respectively. A bit error rate tester of the test board is arranged for communication with the master device and with the DUT by way of the first and second communication ports, respectively, and the bit error rate tester includes at least one IC whose maximum data rate is temperature sensitive. Finally, the test board includes a temperature control system arranged to control the IC temperature so that a maximum data rate of the IC can be adjusted through the use of thermal effects.

Abstract: In one embodiment, a laminated printed circuit board translator is provided. In some embodiments, the translator includes a receiving board adapted to receive a pin, the receiving board includes a plated via extending through the receiving board and has a hole for receiving a pin. An interface board laminated with the receiving board has a controlled depth via extending through it to contact a conductive trace. The conductive trace extends between the receiving board and the interface board to connect the plated via of the receiving board with the controlled depth via of the interface board. The controlled depth via is configured so that it is capable of being plated through a single sided drilled opening in the interface board. Some embodiments have a pad on the interface board connected to the controlled depth via.

Abstract: A semiconductor device, in which a test element group (TEG) including check patterns is formed together with a chip on a wafer so as to measure electric characteristics thereof, includes an interface circuit for selecting the check pattern from the test element group, a protection resistor connected in series with the test element group so as to protect the test element group, and a dummy element connected in series with the test element group. It allows the TEG test, which can be performed after packaging, to be easily performed at a high precision irrespective of dispersions of parasitic resistances and protection resistors. The test result is corrected based on the calculated values of the parasitic resistance and protection resistor and is then stored in a specific table form, wherein a pass/fail decision is made as to whether or not the test result falls within the prescribed range.

Abstract: A wafer level test structure in which, a heating plate is formed on the wafer for heating a structure to be tested positioned above or adjacent to the heating plate. The heating plate produces heat by electrically connecting to a current. Thus, the heat provided by the heating plate and the electric input/output into/from the structure to be tested are controlled separately and not influenced each other.

Abstract: A method evaluates a motor assembly having a first permanent magnet motor in a transmission of an automotive drive system at an end of manufacturing line evaluation. The first motor includes a first rotor with a first plurality of magnets mounted thereon, and a first stator with a first plurality of windings in proximity to the first rotor and coupled to a first inverter. The method includes spinning the first motor with an input dynamometer machine to a predetermined speed such that the first rotor of the first motor induces a first voltage on the first inverter; measuring the first voltage on the first inverter; calculating a first voltage constant of the first motor from the first voltage; comparing the first voltage constant to accepted voltage constants; and identifying the motor as not acceptable if the first voltage constant is outside of a range of the accepted voltage constants.

Abstract: An integrated circuit apparatus includes a switching circuit that provides respective signal paths to permit a mission signal, a test signal, and a boundary scan test signal to share an output terminal. The signal path associated with the mission signal imposes a smaller switching delay than do the signal paths associated with the test and boundary scan test signals.

Abstract: In a logic circuit, a first switching device is connected between a first voltage and an output terminal through which an output signal is output. The switching device is selectively activated and deactivated based on an input signal. A second switching device is connected to a ground voltage and is selectively activated and deactivated based on the input signal. A control circuit outputs a control signal in response to the input signal. The control signal has a first voltage level during a first time period in which a state of the input signal changes, and has a second voltage level during a second time period in which a state of the input signal is constant. The second voltage level is lower than the first voltage level. A field relaxation circuit is connected between the terminal through which the output signal is output.

Abstract: A level conversion circuit capable of realizing low-power/high-speed operation and suppression of variations in input/output characteristics due to variations in source voltage and temperature and device variation. The level conversion circuit comprises: a source follower circuit including a first transistor to input an AC signal of CML level thereto and a second transistor to input a control voltage thereto; and a control-voltage generating circuit to generate the control voltage to be inputted to the second transistor. The control-voltage generating circuit comprises: a replica source follower circuit which is a replica of the source follower circuit including a third transistor to input a central voltage of CML level thereto and a fourth transistor to input the control voltage thereto; and a comparator which controls the control voltage, thereby equalizing an output voltage of the replica source follower and a threshold voltage of a CMOS circuit.

Abstract: The present invention provides for a device to reduce the voltage swing for control signals. An input signal with a maximum potential of DVDD and minimum potential of AVSS is level shifted to a maximum potential of AVDD and a minimum potential of AVDD-DVDD. A series of control signals are generated from the level shifted input signal by standard logic cells. The shifting of the input signal reduces the voltage swing for the control signals. These control signals are then used to drive a device operating at a potential of AVDD.

Abstract: A plurality of transistors are connected between an I2C bus operating at a first voltage level and an I2C bus operating at a second voltage level and a main control electrode of at least one transistor is connected to a first power supply terminal and a main control electrode of the other at least one transistor is connected to an intermediate level between the first voltage level and the second voltage level, whereby a withstand voltage required to a transistor of the bidirectional level shift circuit of the I2C bus can be lowered.

Abstract: A high-voltage tolerant output driver for use in a switching regulator is provided herein. The driver allows the switching regulator to regulate supply voltages that exceed device breakdown limits for the process technology from which the high-voltage tolerant output driver is fabricated. Unregulated supply voltages can vary over a wide range. The regulator only needs two intermediate voltages.

Abstract: Embodiments disclosed herein provide sleep mode solutions for retaining state information while reducing power in a logic block.

Abstract: A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m.times.N where m is the number of word width bits per memory chip and N is the number of memory chips.

Abstract: An output driving circuit is disclosed, providing an output signal at an output node and comprises an inverter and an output driver. A first P-type transistor and a first N-type transistor of the inverter are coupled in series between high and low voltage sources and controlled respectively by first and second driving signals. A gate oxide layer of the first N-type transistor is thinner than that of the first P-type transistor. The inverter generates a first driving signal. A second P-type transistor and a second N-type transistor of the output driver are coupled in series at the output node between the high and low voltage sources. The second P-type transistor and the second N-type transistor are controlled respectively by the first driving signal and a second driving signal. A falling time of the first driving signal is longer than a falling time of the second driving signal.

Abstract: In an embodiment, an analog voltage recovery circuit comprising a plurality of capacitors having first terminals connected to a node having the analog voltage, and comprising a state machine, where during an operating mode the second terminals of the plurality of capacitors are coupled to a first rail, and where during a digitization mode the state machine couples the second terminals of a set of the plurality of capacitors to a second rail so that the analog voltage is closer to the second rail voltage than during the beginning of the digitization mode. In an embodiment, the analog voltage recovery circuit brings the node voltage to the second rail voltage at the end of the digitization mode, and then floats the node and couples the second terminals of the plurality of capacitors to the first rail to approximately restore the analog voltage. Other embodiments are described and claimed.

Abstract: A delay locked loop (DLL) circuit includes a basic loop, a coarse loop, a delay model and a fine loop. The basic loop generates a plurality of first clock signals, based at least in part on an input clock signal, a feedback clock signal and a fine loop output signal. The first clock signals respectively have a phase difference. The coarse loop generates a plurality of output clock signals, based at least in part on the input clock signal, the feedback clock signal and the first clock signals. The plurality of output clock signals respectively have a phase difference. The delay model generates the feedback clock signal by delaying one of the output clock signals by a first time period. The fine loop generates the fine loop output signal, based at least in part on the input clock signal and the feedback clock signal.

Abstract: A delayed locked loop supports increased operation frequency in a semiconductor memory device. An output driver for use in a delay locked loop includes a first driving block for receiving an output from the delay locked loop to generate a first DLL clock for outputting read data corresponding to a read command, and a second driving block for receiving an output from the delay locked loop to generate a second DLL clock for reducing current consumption during a write operation, wherein the first driving block has larger delay amount than the second driving block.

Abstract: A clock signal transmission circuit having a variable initial value for a wait time that is required until a clock signal stabilizes. The clock signal is generated from an original clock signal. The wait time setting unit generates a plurality of wait time signals to wait until the original clock signal stabilizes before providing the clock signal to the internal circuit. A wait time determination unit selects one of the wait time signals and provides the selected wait time signal to a clock control unit. The wait time determination unit includes a data holding circuit which generates a selection signal in accordance with the initial value, a selection circuit which selects one of the wait time signals based on the selection circuit, and an initial value setting circuit enabling the initial value to be varied.

Abstract: A system for controlling a slew rate of a signal, such as used in an imaging device, comprises a counter for measuring a duration that the signal drops from a maximum voltage to a predetermined reference voltage; a register for retaining a desired duration that the signal drops from the maximum voltage to the predetermined reference voltage; and a comparator for comparing the measured duration to the desired duration, the comparator being operative of a current source for the signal. An anti-oscillation circuit prevents the system from oscillating between two discrete durations.

Abstract: A semiconductor integrated circuit has an active mode and a sleep mode. The semiconductor integrated circuit is constructed by alternately connecting a plurality of combinational logic circuits and a plurality of flip-flops. The flip-flops include a retention flip-flop that is supplied with electric power and retains the data in the sleep mode, and a non-retention flip-flop that is not supplied with electric power during the sleep mode. The non-retention flip-flop includes an initializing circuit that initializes the non-retention flip-flop when the semiconductor integrated circuit is switched from the sleep mode to the active mode.

Abstract: A latch circuit (1) comprising a first input device (10a) in a first branch (4a) and a second input device (10b) in a second branch (4b). The latch circuit comprises a first estimator unit (40a) adapted to generate a first estimate of a current generated by the first input device (10a) and a second estimator unit (40b) adapted to generate a second estimate of a current generated by the second input device (10b). The latch circuit further comprises a control-voltage unit (50) operatively connected to the first and the second estimator unit (40a, 40b). The control-voltage unit is adapted to generate a control voltage based on a sum of the first estimate and the second estimate. Further, the latch circuit (1) comprises a first and a second voltage-controlled current unit (30a, 30b) adapted to generate currents at least based on the control voltage. The first voltage-controlled current unit (30a) is operatively connected to the first branch (4a).

Abstract: A scan flip-flop circuit including a data input, a scan input, a data output, a flip-flop, a multiplexer and a delay element is provided. The multiplexer allows selection of either the scan input or the data input for presentation at the input of the flip-flop. The flip-flop provides an output signal at the output of the scan flip-flop. The delay element is in a signal path between the scan input and the input of the flip-flop, and provides a signal propagation delay between the scan input and the input of the flip-flop. The delay between the scan input and the input of the flip-flop is substantially larger than the signal propagation delay between the data input and the input of the flip-flop. The delay in the scan path reduces the need for external buffers to avoid hold-time violations during scan testing of integrated circuits.

Abstract: A latch is provided that includes a first inverter, a second inverter, a first latch circuit and a second latch circuit. The first inverter to receive the first clock signal from an input port and to provide a clock signal. The second inverter to receive the first clock signal from the input port and to provide a clock signal. The first latch circuit is to store data and to receive a clock signal from the second inverter. The second latch circuit is further to store data and to receive a clock signal from the first inverter.

Abstract: An internal voltage detection circuit and an internal voltage generation device using the same are disclosed. The internal voltage detection circuit includes a first detect signal generator for generating a first detect signal to detect a level of an internal voltage corresponding to an operating temperature of a memory cell, a second detect signal generator for generating a second detect signal to detect a specific level of the internal voltage corresponding to a preset temperature, and a detect signal clamp unit for comparing a level of the first detect signal and a level of the second detect signal with each other and clamping the first detect signal according to a result of the comparison.

Abstract: A single input level shifter, which performs a stable level-shifting operation without increasing its area when used with a thin film transistor (“TFT”) having a variety of different characteristics, and includes an intermediate voltage signal providing unit for providing an intermediate voltage signal having a voltage between a supply voltage and an input signal voltage, an inverting unit for receiving the intermediate voltage signal and providing an inverted intermediate voltage signal, and a voltage signal comparing unit for comparing the intermediate voltage signal with the inverted intermediate voltage signal and providing the supply voltage or the ground voltage according to the comparison. A TFT liquid crystal display (“LCD”) device employs the single input level shifter.

Abstract: A signal generating and switching apparatus and a method thereof are provided. According to a simple layout technique, the signal switching apparatus is formed in each layer of a plurality of metal layers in an integrated circuit. When there is a need to correct any one of the plurality of conductive layers in the integrated circuit, the changing of the signal switching apparatus in that conductive layer can be achieved by changing mask patterns of the conductive layer. As a result, the transmission path of signals in the conductive layer is changed, and the purpose to change output logic signals is achieved. Therefore, there is no need to change additional conductive layers, thereby significantly reducing the correcting cost of the integrated circuit.

Abstract: The signal switch has flat resistance across the input/output voltage range when in the ON state while still isolating input/output nodes from overshoots and undershoots when in the off state.

Abstract: A driving circuit for an emitter-switching configuration of transistors having first and second control terminals connected to the driving circuit, forms a controlled emitter-switching device having in turn respective collector, source and gate terminals. The driving circuit comprises a driving block coupled between the collector terminal and the source terminal of the controlled emitter-switching device and connected to the first control terminal of the emitter-switching configuration.

Abstract: A body-bias voltage source having an output monitor, charge pump, and shunt. A shunt circuit having on/off control is coupled to the output monitor and to the output of the charge pump. Upon sensing that the output voltage of the charge pump is above a desired value, the output monitor may disable the charge pump circuit and may enable the shunt circuit to reduce the voltage at the output of the charge pump. When the voltage output of the charge pump is below the desired value, the output monitor may disable the shunt circuit and may enable the charge pump circuit. A shunt circuit having proportional control may be substituted for the shunt circuit with on/off control.

Abstract: There is an internal voltage generating circuit for providing a stable high voltage by making a response time short. The internal voltage generating circuit includes a charge pump unit for generate a high voltage being higher than an external voltage in response to pumping control signals and a supply driving control signal; a pumping control signal generating unit for outputting the pumping control signals to the charge pump unit based on a driving signal; and a supply driving control unit for receiving the driving signal to generate the supply driving control signal to the charge pump unit.

Abstract: A system may comprise a control system that controls a state of a switch network, the control system having first and second thresholds that determine the state of the switch network based on the relative voltages at an input and an output of the switch network. A scaling network is coupled across the input and the output of the switch network and providing a gain scaling signal to a first input of the control system. An offset network is coupled to the output of the switch network and providing an offset signal to a second input of the control system, the first threshold being set independently of the second threshold based on the gain scaling signal and the offset signal.

Abstract: A leakage current control circuit with a single low voltage power supply is provided. The circuit includes a first power supply line, a second power supply line, a ground line, a high voltage generating circuit, a power transistor and a control circuit. The high voltage generating circuit generates a voltage in response to an internal sleep signal. The gate electrode of the power transistor is connected to the output of the high-voltage generating circuit such that the power transistor is controlled by the high voltage generating circuit. When the power transistor turns on, the circuit is in operation mode; when the power transistor is off, the circuit is in sleep mode. The control circuit connects to the first power line, the second power line, and the ground line to output the internal sleep signal in response to the sleep signal.

Abstract: A short-circuit charge-sharing technique which allows charge-sharing between two or more circuits with a simple shorting transistor controlled to achieve the desired operating voltage levels. The shorting transistor which can be either a P-channel Metal Oxide Semiconductor (PMOS) or an N-channel Metal Oxide Semiconductor (NMOS) device and can be controlled utilizing the same clock that enables the drive of the signals between which charge-sharing occurs. In operation, the desired operating voltage levels can be regulated by increasing and decreasing the pulse width of the control circuit output to the gate of the shorting transistor.

Abstract: An integrated, multi-band radio frequency (RF) filter is capable of modifying a filter response thereof in response to control information. Switching elements within the filter can be changed between on and off conditions to modify the filter response. In one implementation, the integrated, multi-band filter is integrated on a front end module chip to be used within a multi-radio wireless device. In at least one embodiment, linearity enhancement circuitry is provided within a multi-band filter to improve linearity and reduce insertion loss.

Abstract: Loop filters are provided, in which a first resistor comprises a first terminal coupled to a first node, and a second terminal coupled to a second node; a first capacitor is coupled between the second node and a ground voltage, a second resistor comprises a first terminal coupled to the first node and a second terminal coupled to a third node. An operational amplifier comprises a non-inversion input terminal coupled to the second node, an inversion input terminal coupled to the third node, and an output terminal, and a second capacitor is coupled between the output terminal of the operational amplifier and the third node.

Abstract: An integrated circuit comprises a pin coupled to receive signals from outside the integrated circuit and an input network. The input network equalizes incoming signals by attenuating lower frequency input signals more than higher frequency input signals received at the pin. The input network is configured to generate a DC bias voltage at an output of the input network in response to an AC coupled input signal or a DC coupled input signal received at the pin with a wide common-mode range.

Abstract: Systems and methods in which an ultrasonic signal is introduced into an audio signal before the audio signal is amplified by a switching amplifier. The added ultrasonic signal (e.g., a tone at half the amplifier's switching frequency) shifts the signals input to a set of power switches so that they do not switch nearly simultaneously. The ultrasonic signal causes the output current to be well defined to eliminate dead time distortion at low signal levels. Adding the tone ultrasonic signal causes the distortion to shift to an amplitude greater than zero. Signals that exceed this amplitude will experience the distortion, but the distortion will be less noticeable than in lower-amplitude signals. Signals that do not exceed this amplitude will not experience the distortion at all. Adding an ultrasonic signal may also draw energy away from the switch frequency and its harmonics to interference with AM radio reception.

Abstract: A system for amplifying a signal is provided. The system includes a plurality of driver stages, each having an input, an output, and a disable control. An output stage having an input is coupled to the outputs of the plurality of driver stages. A plurality of disable control signals is provided to the driver stages so as to controllably enable and disable one or more of the driver stages.

Abstract: When an input signal level is small, the electrical length of a phase line 21 and the electrical length of a phase line 23 are set in such a manner that the impedance seen by looking into the output side from an impedance reference point 11 at the output side of a carrier amplifier 3 becomes 2R+? (where R is a load resistance and ? is positive), and the electrical length of a phase line 22 is set at a difference between the electrical length of the phase line 21 and the electrical length of the phase line 23.

Abstract: A high-frequency power amplifier of the present invention comprises a power supply unit for including a transistor for switching whose drain electrode—source electrode or collector electrode—emitter electrode are on/off controlled according to a pulse signal corresponding to an envelope signal of a high-frequency signal applied to a gate electrode or to a base electrode, and for generating a voltage corresponding to the envelope signal by means of on/off operation of the transistor for switching; and a transistor for power amplification which is a source electrode grounded type or an emitter electrode grounded type, to which a voltage generated by the power supply unit is supplied as an operating voltage, in which the high-frequency signal is applied to the gate electrode or to the base electrode. Further, the transistor for switching in the power supply unit and the transistor for power amplification are arranged so that the source electrodes or the emitter electrodes are commonly connected in one package.

Abstract: Methods and apparatus to reduce voltage bounces and spike voltages in switching amplifiers are disclosed. An example apparatus to reduce spike voltages in a switching amplifier disclosed herein comprises an input to sense an output voltage of the switching amplifier, and a pull-down circuit to electrically couple the apparatus with a transistor in the switching amplifier, wherein the pull-down circuit is configured to vary in strength based on the output voltage sensed by the input.

Abstract: A new Class L amplifier which dynamically switches between multiple pairs of power rails, and has the ability to select the most advantageous combination of rails for the minimization of power dissipation in the amplifier. In one embodiment, a bridged amplifier system includes two Class L amplifiers to drive a load.

Abstract: Sharing one or more load inductors comprises receiving a first input signal at a first terminal of a first amplifier and amplifying the first input signal using the first amplifier. The first amplifier is coupled to one or more load inductors at a second terminal of the first amplifier and is coupled to one or more dedicated source inductors at a third terminal of the first amplifier. Also, a second input signal is received at a first terminal of a second amplifier amplifying the second input signal using the second amplifier. The second amplifier is coupled to the one or more load inductors at a second terminal of the second amplifier and is coupled to one or more dedicated source inductors at a third terminal of the second amplifier.

Abstract: An input bias cancellation stage for an audio operational amplifier is provided. The input bias cancellation stage includes an input differential pair, a current mirror, and a bias duplicator transistor that substantially duplicates the input bias current. The bias duplicator transistor receives substantially the same emitter current as the transistors in the input differential pair, and has substantially the same Vce as the transistors in the input differential pair. The current mirror mirrors the duplicated bias current and subtracts it from the bases of the transistors in the input differential pair so that the input bias current is substantially cancelled.

Abstract: There is provided a variable-gain amplifier, including two cascode amplifiers and an attenuator. The cascode amplifiers are mutually connected in parallel via the attenuator.

Abstract: A device and a method including current measurement and/or amplification is disclosed. One embodiment provides supplying a current to be measured to a current amplifier. The current is amplified by the current amplifier. The amplified current or a current generated is fed back therefrom to the current amplifier. The current amplifier may include a current mirror. Furthermore, at least one delay means may be used by which the process of current amplification and/or current feedback may be delayed correspondingly.

Abstract: A frequency detecting and converting apparatus comprises a plurality of frequency-dividers, a multiplexer, a pulse width detector, a comparing unit and an encoder. The invention automatically detects the operating frequency of an input clock signal, divides the frequency of the input clock signal by a pre-defined integer according to the detected operating frequency and finally generates an output clock signal with an operating frequency required for an integrated circuit.

Abstract: A system, apparatus and method for providing phase lock conditions detection such as a quality of phase lock and loss of lock detection. A phase locked loop (PLL) circuit may comprise an oscillator for providing an output frequency, as well as a detector for detecting the output frequency of the oscillator, comparing the output frequency with a reference signal and outputting a first and second signals as a function of the comparison. The PLL circuit may further include an amplifying circuit for receiving the first and second signals, monitoring a deviation of the first and second signals from a predetermined threshold, and generating a third signal as a function of the deviation. The PLL circuit may further comprise a comparison circuit for receiving the third signal, comparing the third signal to a window threshold, and generating a fourth signal as a function of the comparison.

Abstract: A real time clock integrated circuit (RTC IC) and an electronic apparatus thereof are provided. In the RTC IC, only a low-power oscillator is used for generating a standard clock for a real time counter, and the standard clock with a frequency drift of the low-power oscillator is compensated through table lookup. Accordingly, the power consumption, fabrication cost and design complexity of the RTC IC are reduced and the counting operation duration of the RTC IC is prolonged.

Abstract: An oven controlled crystal oscillator capable of uniformly transmitting heat from the heat generator to improve the frequency-temperature characteristics. The oven controlled crystal oscillator includes a high thermal conductivity plate having high thermal conductivity and provided on one side of a substrate, where the crystal resonator is provided, in such a manner to contact the resistors, the transistor, the crystal resonator, and the temperature sensor. This structure can transmit heat from the resistors and the transistor as the heat generator to the crystal resonator and the temperature sensor rapidly with less heat loss to assure a uniform temperature inside the substrate, thereby improving the frequency-temperature characteristics.